US 7920018

Summary of US Patent 7920018

Title: Booster circuit

Current Assignee: Advanced Memory Technologies LLC (as of April 22, 2024)

Inventor: Seiji Yamahira

Filing Date: July 14, 2010

Issue Date: April 5, 2011

Abstract: A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared.

Independent Claims Overview:

Claim 1:
This claim describes a booster circuit featuring two rows of boosting cells (a first row with N stages and a second row with M stages). Each boosting cell includes a switching element within a triple-well structure (a first-conductivity type first well region on a substrate, and a second-conductivity type second well region within the first well region). These switching elements transfer charges between a first and a second terminal. A key feature is at least one analog comparison circuit that compares the input potentials of boosting cells on the same stage from both rows. This analog comparison circuit then outputs a "well bias potential," which is applied to the first well region of the switching element in at least one boosting cell of both rows. The purpose of this control is to reduce current consumption and layout area while suppressing the substrate biasing effect of the switching elements.

Claim 12:
This claim describes a booster circuit also having a first boosting cell row (N stages, N≧2) and a second boosting cell row (M stages, M≧2), each with boosting cells. Similar to Claim 1, each boosting cell includes a switching element in a triple-well structure, configured to transfer charges between a first and second terminal. A distinguishing feature of this claim is that the potential of the first well region of the switching elements in the boosting cells, specifically those on the second stage or succeeding stages in both rows, is controlled based on the input potentials of boosting cells from the first and second boosting cell rows. Crucially, the input potential for each boosting cell in the first row is different from the input potential of each boosting cell in the second row.

CAFC 2026 Dockets:

A search for CAFC 2026 dockets related to US7920018B2 did not yield specific docket entries in the provided search results. The search returned general information on how to access case information from the U.S. Court of Appeals for the Federal Circuit, but no specific cases mentioning US7920018B2 within the 2026 dockets were found. Therefore, I cannot definitively report on any active CAFC litigation for this patent at this time with the information available.

US patent 7920018 has been involved in the following litigation:

• PTAB Case IPR2025-01450

  • Plaintiff(s): Unified Patents
  • Defendant(s): SK Hynix, Inc.
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2025-01450
  • Filing Date: August 29, 2025 (Effective date)
  • Outcome/Current Status: Not Instituted - Procedural.

• US case filed in Texas Western District Court

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Jurisdiction: Texas Western District Court
  • Case Number: 1:25-cv-01036
  • Filing Date: Not specified in the provided information.
  • Outcome/Current Status: Active.

• US case filed in Texas Eastern District Court

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:24-cv-01078
  • Filing Date: Not specified in the provided information.
  • Outcome/Current Status: Active.

Proceedings overview

There is one AIA trial proceeding on file for US patent 7920018. This proceeding resulted in an institution denial, meaning no claims were challenged on the merits by the PTAB. This gives a defendant a posture where the patent's claims remain untested by an AIA trial proceeding, and no claims have been invalidated through this mechanism.

IPR2025-01450 — SK hynix Inc. v. Advanced Memory Technologies LLC

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Discretionary Denial. This means the PTAB declined to institute the review, and the merits of the challenged claims were not evaluated.
• Judge panel: Not publicly available as the case was discretionarily denied before institution.
• Petition grounds: Details not publicly available in the patent record for a non-instituted IPR.
• Institution decision: Denied (Discretionary Denial) on 2026-02-27. The PTAB issued a decision declining to institute Inter Partes Review under 35 U.S.C. § 314(a). The specific reasoning for the discretionary denial (e.g., NHK-Fintiv factors, parallel litigation) is not detailed in the available patent record without access to the full PTAB order.
• Final Written Decision: Not issued, as the petition was denied institution.
• Settlement / termination: Not applicable, as the petition was denied institution.
• Appeal: Not applicable, as no Final Written Decision was issued.
• Defensive value: The patent owner prevailed in preventing institution of this IPR. This means that, for SK hynix Inc. and its privies, grounds raised or that reasonably could have been raised in this petition are subject to estoppel if a district court action is ongoing or later initiated. However, no claims of US7920018 were invalidated.

Strategic summary

All claims of US7920018 remain UNTESTED by a full AIA trial. The single IPR filed, IPR2025-01450, was denied institution, meaning the PTAB did not proceed to a full review of the challenged claims. Consequently, no claims have been canceled or sustained on the merits by a Final Written Decision at the PTAB.

Regarding estoppel, since IPR2025-01450 was denied institution, statutory estoppel under 35 U.S.C. § 315(e)(2) generally applies to the petitioner (SK hynix Inc.) and its privies for any grounds that were raised or reasonably could have been raised in that petition, should they face future litigation regarding this patent. However, for other potential defendants, this denial does not create estoppel, and the prior art relied upon in this IPR (though not publicly detailed here) may still be available to challenge the patent in other proceedings or forums. There are no clear pattern signals of aggressive PTAB appeals by the patent owner, nor is there evidence of multiple IPRs by the same petitioner or defensive aggregator involvement in the provided data.

Recommended next steps

For a defendant facing assertion of US7920018, it is important to understand the specific prior art and grounds raised by SK hynix Inc. in IPR2025-01450, even though the petition was denied. While the full reasoning for the discretionary denial is not available in the provided public snippets, retrieving and reviewing the PTAB's Institution Decision for IPR2025-01450 (available at the USPTO PTAB Decisions portal) is crucial. This document would detail the PTAB's reasoning for the denial, which could inform future PTAB strategies.

Given that all claims remain untested by the PTAB, a defendant could consider filing their own IPR petition if a strong prior art case exists, as the patent has not been "hardened" by surviving institution and a Final Written Decision. The absence of further PTAB activity on an active patent that has reportedly been litigated (as indicated by the "Family has litigation" status) suggests potential strategic decisions by other parties or a lack of strong, novel prior art grounds presented so far.## Proceedings overview
There is one AIA trial proceeding on file for US patent 7920018. This proceeding resulted in a discretionary denial of institution, meaning no claims were challenged on the merits by the PTAB. This gives a defendant a posture where the patent's claims remain untested by an AIA trial proceeding, and no claims have been invalidated through this mechanism.

IPR2025-01450 — SK hynix Inc. v. Advanced Memory Technologies LLC

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Discretionary Denial. This means the PTAB, specifically the USPTO Director, declined to institute the review, and the merits of the challenged claims were not evaluated.
• Judge panel: John A. Squires, Under Secretary of Commerce for Intellectual Property and Director of the United States Patent and Trademark Office.
• Petition grounds: Specific petition grounds (which claims, what art, what statutory basis) are not publicly detailed for this non-instituted IPR.
• Institution decision: Denied (Discretionary Denial) on 2026-01-09. The denial was issued by Director John A. Squires, who assumed personal control over institution decisions in October 2025. The decision was likely influenced by the ongoing parallel district court litigation between Advanced Memory Technologies, LLC and SK Hynix Inc. in the Eastern District of Texas (Case No. 2:24-cv-01078), where a trial date was set for October 5, 2026, prior to the projected Final Written Decision deadline of March 1, 2027, for the IPR. This aligns with PTAB policy to deny IPR institution when parallel district court litigation is well underway and likely to resolve validity issues first, often referred to as Fintiv factors.
• Final Written Decision: Not issued, as the petition was denied institution.
• Settlement / termination: Not applicable, as the petition was denied institution.
• Appeal: Not applicable, as no Final Written Decision was issued. Institution decisions are generally unappealable.
• Defensive value: The patent owner, Advanced Memory Technologies LLC, prevailed in preventing the institution of this IPR. For SK hynix Inc. and its privies, estoppel under 35 U.S.C. § 315(e)(2) would likely apply to any grounds raised or that reasonably could have been raised in this petition, in subsequent litigation. For other potential defendants, no claims of US7920018 were invalidated, and the prior art relied upon in this IPR is not publicly known, leaving the patent's claims untouched by this PTAB proceeding.

Strategic summary

All claims of US7920018 remain UNTESTED by a full AIA trial. The single IPR filed, IPR2025-01450, was denied institution by the USPTO Director. This means the PTAB did not proceed to a full review of the challenged claims, and consequently, no claims have been canceled or sustained on the merits through this mechanism.

Regarding estoppel, since IPR2025-01450 was denied institution, statutory estoppel under 35 U.S.C. § 315(e)(2) will likely apply to the petitioner, SK hynix Inc., and its privies. This bars them from asserting in district court or the ITC any invalidity ground raised or that reasonably could have been raised in the IPR petition. For other potential defendants, this specific denial does not create statutory estoppel, and the patent's claims can still be challenged in future proceedings using relevant prior art. The denial itself was a discretionary one, likely due to the scheduling of a parallel district court trial, reflecting the USPTO Director's policy to focus IPRs as an alternative to, rather than a duplicate of, district court litigation.

No specific "pattern signals" like multiple IPRs by the same petitioner or aggressive PTAB appeals by the patent owner can be identified from the single non-instituted proceeding. The fact that the patent is currently involved in district court litigation (Advanced Memory Technologies, LLC v. SK Hynix Inc., Case No. 2:24-cv-01078 (E.D. Tex.)) is a key signal, and the discretionary denial of the IPR reflects the PTAB's recent stance on parallel proceedings.

Recommended next steps

For a defendant facing assertion of US7920018, it is critical to obtain and thoroughly review the Institution Decision for IPR2025-01450. This decision, issued by Director John A. Squires on 2026-01-09, will contain the specific reasoning for the discretionary denial, which is essential for understanding the PTAB's perspective on this patent and any potential future IPR filings. While summary orders often lack detailed reasoning, more significant cases or those presenting novel issues may include more context.

Given that the claims of US7920018 remain untested on the merits at the PTAB, a defendant should evaluate their own prior art and potential invalidity arguments. If strong prior art exists, a new IPR petition could still be a viable strategy, provided it navigates the current PTAB discretionary denial factors, particularly those related to parallel litigation (e.g., ensuring an IPR functions as a "true alternative to litigation" and considering the timing relative to any district court trial dates). The patent owner, Advanced Memory Technologies LLC, is known to be a patent assertion entity ("patent troll"). This context may influence enforcement strategies and settlement discussions.

Inventors

• Seiji Yamahira (Panasonic Corp)

Unusual patterns: Not determinable from the provided text whether the inventor departed the original assignee within 12 months of filing.

Original assignee

The original assignee on the issued patent US7920018 is Panasonic Corp. Panasonic Corp is a multinational electronics company that ships a wide range of products, including consumer electronics, home appliances, and industrial solutions. Given their diverse product lines that include electronic components and semiconductor packaging materials, it is highly probable they shipped products embodying the claims related to booster circuits for semiconductor memory devices. Panasonic Corp is currently operating.

Assignment timeline

• 2020-08-17 (executed) / recorded 2020-08-24 — Reel 053570/0429
  • Conveyance: Assignment
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: Panasonic Corp. This is an internal corporate reorganization.
  • Context: Internal corporate reorganization.
• 2020-09-02 (executed) / recorded 2024-03-20 — Reel 066849/0802
  • Conveyance: Change of Name
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: Not specified in the provided text.
  • Context: Corporate name change.
• 2024-03-25 (executed) / recorded 2024-04-22 — Reel 067184/0869
  • Conveyance: Assignment
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED MEMORY TECHNOLOGIES LLC
  • Correspondent: Daniel A. Boehnen, McDonnell Boehnen Hulbert & Berghoff LLP, 300 S. Wacker Drive, Chicago, IL 60606. This correspondent is not flagged as recurring in the provided information.
  • Context: Transfer to an asserting entity.

Timeline diagram

timeline
    title Ownership of US 7920018
    2011 : Patent issued
    2020 : Assigned to Panasonic Semiconductor Solutions
    2024 : Nuvoton Technology Corp Japan by name change
         : Assigned to Advanced Memory Technologies LLC
    2024 : Infringement suit filed by AMT
    2025 : IPR filed against AMT

NPE / troll-pattern signals

1. Shell-entity transfer — Present.

   • Advanced Memory Technologies LLC (AMT) is a Delaware limited liability company with its principal place of business at 825 Watters Creek Blvd. Suite 250, Allen, Texas 75013. It has been identified as a non-practicing entity (NPE). AMT sued SK Hynix Inc. for patent infringement in December 2024. Public records do not identify the personnel or management of Advanced Memory Technologies. The assignment from Nuvoton Technology Corporation Japan to Advanced Memory Technologies LLC occurred on 2024-03-25 (executed) / 2024-04-22 (recorded).

2. Known asserter in the chain — Present.

   • Advanced Memory Technologies LLC (AMT) is identified as a non-practicing entity (NPE). They filed a patent infringement complaint against SK Hynix Inc. in the Eastern District of Texas on December 30, 2024, asserting US7920018 along with other patents. Unified Patents also identifies an IPR filed by SK Hynix Inc. against Advanced Memory Technologies LLC for US7920018 (IPR2025-01450). RPX reported on Nuvoton Technology assigning patents to Advanced Memory Technologies LLC, an entity formed in Delaware less than a week prior, in March 2024, noting that public records do not identify its personnel or management.

3. Repeat correspondent across the chain — Not present.

   • The correspondent for the assignment to Advanced Memory Technologies LLC is Daniel A. Boehnen of McDonnell Boehnen Hulbert & Berghoff LLP. There is no indication in the provided text that this correspondent recurs in this chain or is otherwise associated with known NPE assertion lists.

4. Cascading transfers — Present.

   • The patent was reassigned from Panasonic Corp to Panasonic Semiconductor Solutions Co., Ltd. (internal reorganization) on 2020-08-17. Then, a change of name occurred for Panasonic Semiconductor Solutions Co., Ltd. to Nuvoton Technology Corporation Japan, which was executed on 2020-09-02 and recorded on 2024-03-20. Subsequently, the patent was assigned from Nuvoton Technology Corporation Japan to Advanced Memory Technologies LLC on 2024-03-25. The transfers from Panasonic Semiconductor Solutions Co., Ltd. to Nuvoton Technology Corporation Japan and then to Advanced Memory Technologies LLC occurred in close succession (within approximately 4 years for the first, and then within days for the second once the name change was recorded in 2024), especially when considering the lag in recording the name change. The active transfer to AMT was within days of the name change being recorded, indicating a rapid transfer of assets for assertion.

5. Pre-litigation transfer — Present.

   • The assignment to Advanced Memory Technologies LLC was executed on 2024-03-25 and recorded on 2024-04-22. Advanced Memory Technologies LLC filed an infringement suit against SK Hynix Inc. on December 30, 2024. This falls within the 6-month window prior to litigation.

6. Bankruptcy fire-sale — Not present.

   • There is no information in the provided text to suggest a bankruptcy of Panasonic Corp or Nuvoton Technology Corporation Japan.

7. Privateering — Unclear.

   • While Nuvoton Technology Corporation Japan (formerly Panasonic Semiconductor Solutions Co., Ltd., a Panasonic entity) transferred the patent to AMT, there is no explicit evidence in the provided text to suggest that Panasonic or Nuvoton is funding or directing AMT's litigation against their competitors.

8. Defensive aggregator (anti-NPE) — Not present.

   • The chain terminates with Advanced Memory Technologies LLC, which is an NPE, not a defensive aggregator.

Verdict

NPE — high confidence
This verdict is based on several strong signals: Advanced Memory Technologies LLC (AMT) is a known Non-Practicing Entity, the patent was transferred to AMT shortly before infringement litigation was filed, and there were cascading transfers leading up to AMT's acquisition. The entity Advanced Memory Technologies LLC also lacks publicly identified personnel or management and has its principal place of business at a registered-agent type address in Texas. The current legal actions, including an IPR challenge by SK Hynix, further confirm AMT's role as an asserting entity.

USPTO Assignment Center search for US7920018: https://assignmentcenter.uspto.gov/patent/index.html

The most relevant prior art for US patent 7920018, as identified from its own citations, is analyzed below. The priority date for US7920018 is January 17, 2007. Therefore, any patent with a priority date before this is relevant for anticipation under 35 U.S.C. § 102.

Analysis of Cited Prior Art

The US patent 7920018 explicitly mentions several prior art patents in its "BACKGROUND OF THE INVENTION" section as disclosing "a known booster circuit employing a triple-well structure switching element". These, along with other cited references, are detailed below.

1. US6100557A

   • Full Citation: US6100557A, "Triple well charge pump," Macronix International Co., Ltd., published August 8, 2000.
   • Publication/Filing Date: Priority date: October 10, 1996; Publication date: August 8, 2000.
   • Brief Description: This patent describes a triple-well charge pump circuit. According to US7920018, it generally discloses a booster circuit employing a triple-well structure switching element.
   • Potential Anticipation (35 U.S.C. § 102): US6100557A likely anticipates elements of Claims 1 and 12 of US7920018 related to a "booster circuit" and "at least one switching element in either or both of the first well region and the second well region" for transferring charges, particularly in the context of a triple-well structure. Claims 1 and 12 are distinguished by the use of an analog comparison circuit to compare potentials between two boosting cell rows and applying the resultant well bias potential, which is not directly evident from the title or general description of US6100557A.

2. US6121821A

   • Full Citation: US6121821A, "Booster circuit for semiconductor device," Nec Corporation, published September 19, 2000.
   • Publication/Filing Date: Priority date: March 31, 1998; Publication date: September 19, 2000.
   • Brief Description: This patent describes a booster circuit for a semiconductor device. US7920018 states it discloses a booster circuit employing a triple-well structure switching element.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US6100557A, US6121821A likely anticipates the basic concepts of a "booster circuit" and a "switching element" within a triple-well structure as broadly recited in Claims 1 and 12 of US7920018. However, it does not appear to disclose the specific comparison and well bias control across two rows of cells as claimed in US7920018.

3. US7102422B1

   • Full Citation: US7102422B1, "Semiconductor booster circuit having cascaded MOS transistors," Nippon Steel Corporation, published September 5, 2006.
   • Publication/Filing Date: Priority date: April 20, 1994; Publication date: September 5, 2006.
   • Brief Description: This patent describes a semiconductor booster circuit with cascaded MOS transistors. US7920018 indicates it discloses a booster circuit employing a triple-well structure switching element.
   • Potential Anticipation (35 U.S.C. § 102): US7102422B1 likely anticipates the general configuration of a "booster circuit" with "switching elements" and potentially a "triple-well structure" as foundational elements of Claims 1 and 12 of US7920018. The specific inventive aspects of US7920018 regarding analog comparison and shared well regions are not indicated by the title or general context.

4. US6501325B1

   • Full Citation: US6501325B1, "Low voltage supply higher efficiency cross-coupled high voltage charge pumps," Cypress Semiconductor Corp., published December 31, 2002.
   • Publication/Filing Date: Priority date: January 18, 2001; Publication date: December 31, 2002.
   • Brief Description: This patent describes high-efficiency cross-coupled high-voltage charge pumps suitable for low voltage supplies.
   • Potential Anticipation (35 U.S.C. § 102): This patent's focus on high-efficiency charge pumps suggests it deals with similar problems of boosting voltage. While it likely anticipates the general concept of a "booster circuit" and charge transfer, the specific mechanism of using an analog comparison circuit to control well bias potentials between two distinct boosting cell rows, as claimed in US7920018, would need to be thoroughly examined to determine anticipation.

5. US6734717B2

   • Full Citation: US6734717B2, "Charge pump circuit," Hynix Semiconductor Inc., published May 11, 2004.
   • Publication/Filing Date: Priority date: December 29, 2001; Publication date: May 11, 2004.
   • Brief Description: This patent broadly describes a charge pump circuit.
   • Potential Anticipation (35 U.S.C. § 102): As a general "charge pump circuit," it would anticipate the fundamental concept of a "booster circuit" and charge transfer elements. Without further details, it's difficult to assess anticipation of the specific well bias control and dual-row comparison features of US7920018's Claims 1 and 12.

6. US6878981B2

   • Full Citation: US6878981B2, "Triple-well charge pump stage with no threshold voltage back-bias effect," Tower Semiconductor Ltd., published April 12, 2005.
   • Publication/Filing Date: Priority date: March 20, 2003; Publication date: April 12, 2005.
   • Brief Description: This patent describes a triple-well charge pump stage designed to mitigate the threshold voltage back-bias effect. This aligns with a problem US7920018 aims to solve by suppressing the substrate biasing effect.
   • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it specifically addresses the back-bias effect in triple-well charge pumps, a core problem US7920018 seeks to improve upon. It likely anticipates the "triple-well structure," "switching element," and the goal of suppressing the "substrate biasing effect" mentioned in Claims 1 and 12 and their associated advantages. The distinguishing feature for US7920018 would be its specific use of an analog comparison circuit comparing potentials from two rows of cells to generate and apply a well bias potential.

7. US6888400B2

   • Full Citation: US6888400B2, "Charge pump circuit without body effects," Ememory Technology Inc., published May 3, 2005.
   • Publication/Filing Date: Priority date: August 9, 2002; Publication date: May 3, 2005.
   • Brief Description: This patent describes a charge pump circuit designed to operate without body effects, which is another term related to the substrate biasing effect.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US6878981B2, this patent directly addresses the "body effect" (substrate biasing effect) in charge pumps, which is a problem US7920018 also aims to mitigate. It would therefore anticipate elements related to suppressing the substrate biasing effect and the components of a charge pump. The novelty of US7920018 would rest on the specific analog comparison circuit and its application to well bias across multiple boosting cell rows.

8. US6952129B2

   • Full Citation: US6952129B2, "Four-phase dual pumping circuit," Ememory Technology Inc., published October 4, 2005.
   • Publication/Filing Date: Priority date: January 12, 2004; Publication date: October 4, 2005.
   • Brief Description: This patent describes a charge pump circuit utilizing a four-phase dual pumping scheme.
   • Potential Anticipation (35 U.S.C. § 102): This patent describes a specific type of charge pump ("dual pumping circuit") that implies multiple stages or rows. While it might anticipate the concept of multiple boosting cell rows and charge transfer, the "four-phase" clocking is different from the two-phase example primarily discussed in US7920018 (though US7920018 also mentions four-phase). The critical distinction for US7920018's claims would still be the analog comparison circuit's function in generating and applying the well bias potential between rows.

9. US7123077B2

   • Full Citation: US7123077B2, "Four-phase charge pump circuit with reduced body effect," Ememory Technology Inc., published October 17, 2006.
   • Publication/Filing Date: Priority date: August 3, 2004; Publication date: October 17, 2006.
   • Brief Description: This patent describes a four-phase charge pump circuit that explicitly aims to reduce the body effect.
   • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it combines "four-phase charge pump" with "reduced body effect," directly addressing both the pump architecture and the substrate biasing issue that US7920018 seeks to improve. It would anticipate elements related to booster circuits, switching elements, and methods to mitigate body effects. The specific analog comparison circuit approach of US7920018, particularly the comparison between two rows for well bias, would be the differentiating factor.

10. US20070096796A1

    • Full Citation: US20070096796A1, "High voltage charge pump with wide range of supply voltage," Firmansyah Teezar R, published May 3, 2007.
    • Publication/Filing Date: Priority date: August 26, 2005; Publication date: May 3, 2007.
    • Brief Description: This patent application describes a high-voltage charge pump capable of operating over a wide range of supply voltages.
    • Potential Anticipation (35 U.S.C. § 102): This patent generally describes a charge pump for high voltage, which relates to the overall function of US7920018. However, its title doesn't suggest the specific well biasing control or dual-row comparison feature. It would broadly anticipate the "booster circuit" aspect.

11. US7317347B2

    • Full Citation: US7317347B2, "Charge pump circuit with reuse of accumulated electrical charge," Stmicroelectronics S.R.L., published January 8, 2008.
    • Publication/Filing Date: Priority date: November 22, 2004; Publication date: January 8, 2008.
    • Brief Description: This patent describes a charge pump circuit that focuses on the reuse of accumulated electrical charge to improve efficiency.
    • Potential Anticipation (35 U.S.C. § 102): This patent addresses efficiency in charge pumps, which is a goal of US7920018. It might anticipate aspects of charge transfer and improving boost efficiency. However, it does not explicitly disclose the unique well biasing control method of US7920018's Claims 1 and 12.

12. US7532062B2

    • Full Citation: US7532062B2, "Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device," Kabusiki Kaisha Toshiba, published May 12, 2009.
    • Publication/Filing Date: Priority date: November 8, 2005; Publication date: May 12, 2009.
    • Brief Description: This patent describes a semiconductor charge pump that uses MOS transistors as current rectifier devices.
    • Potential Anticipation (35 U.S.C. § 102): This patent addresses the use of MOS transistors for current rectification in charge pumps, which are a form of switching elements in booster circuits. It would therefore anticipate aspects of the "switching element" and "booster circuit" components of US7920018. The specific analog comparison and dual-row well bias control of US7920018's claims would be the distinguishing features.

Overall Most Relevant Prior Art:

The most relevant prior art appears to be US6878981B2 ("Triple-well charge pump stage with no threshold voltage back-bias effect") and US7123077B2 ("Four-phase charge pump circuit with reduced body effect"). These patents directly address the problem of the "substrate biasing effect" or "body effect" in charge pumps employing triple-well structures, which is a primary concern for US7920018. While they disclose booster circuits and methods to mitigate these effects, the unique contribution of US7920018, as recited in Claims 1 and 12, lies in the specific architecture of comparing potentials from two separate boosting cell rows using an analog comparison circuit to generate and apply a well bias potential to the first well region of the switching elements, thereby reducing current consumption and layout area, and improving boost efficiency.

Obviousness Analysis of US Patent 7920018 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that could render claims of US Patent 7920018 obvious to a person having ordinary skill in the art (PHOSITA). The focus is on the motivation to combine these references to arrive at the claimed invention, particularly regarding the control of N-well potentials in triple-well structures for improved booster circuit performance.

Background on Prior Art and Obviousness

The present invention (US7920018) relates to a booster circuit employing switching elements with a triple-well structure. A conventional booster circuit (Figure 25 of US7920018) is described, where the P-well and N-well of each charge transfer transistor are connected to the source to suppress the substrate biasing effect. However, this conventional approach suffers from decreased boost efficiency and increased layout area due to the parasitic capacitance of the N-well being charged and discharged by clock signals, and the necessity of separating N-wells for each transistor. The stated object of US7920018 is to provide a booster circuit that suppresses current consumption and layout area while still mitigating the substrate biasing effect.

The listed prior art includes several patents related to booster circuits and triple-well charge pumps, which were known at the time of the invention:

• US6100557A: Triple well charge pump.
• US6121821A: Booster circuit for semiconductor device.
• US7102422B1: Semiconductor booster circuit having cascaded MOS transistors.
• US6501325B1: Low voltage supply higher efficiency cross-coupled high voltage charge pumps.
• US6734717B2: Charge pump circuit.
• US6888400B2: Charge pump circuit without body effects.
• US6878981B2: Triple-well charge pump stage with no threshold voltage back-bias effect.
• US6952129B2: Four-phase dual pumping circuit.
• US7123077B2: Four-phase charge pump circuit with reduced body effect.
• US20070096796A1: High voltage charge pump with wide range of supply voltage.
• US7317347B2: Charge pump circuit with reuse of accumulated electrical charge.
• US7532062B2: Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device.

Combination 1: US6100557A in view of US6878981B2 and the conventional booster circuit (Figure 25 of US7920018)

Claim Elements Addressed: The primary independent claims (Claims 1 and 12) of US7920018 introduce the use of an analog comparison circuit to control the well bias potential of the first well region (N-well) of switching elements in boosting cells arranged in rows. This control aims to reduce current consumption and layout area while maintaining suppression of the substrate biasing effect.

Prior Art Disclosures:

• US6100557A (Triple well charge pump): This patent discloses a triple-well charge pump, addressing the need for boosting circuits in non-volatile memories. It teaches the use of a triple-well structure to improve charge pump efficiency. While it deals with triple-well structures, it doesn't explicitly detail using an analog comparison circuit to dynamically control the N-well potential based on input/output potentials of different stages in multiple rows for the specific purpose of reducing parasitic capacitance and layout area in the manner claimed by US7920018.
• US6878981B2 (Triple-well charge pump stage with no threshold voltage back-bias effect): This reference also focuses on triple-well charge pumps and aims to eliminate the threshold voltage back-bias effect, thereby improving efficiency. It emphasizes connecting the N-well to the source of the switching element, similar to the conventional circuit described in US7920018.
• Conventional Booster Circuit (Figure 25 of US7920018): This figure illustrates a typical triple-well booster circuit where the P-well and N-well of each charge transfer transistor are connected to the source to suppress the substrate biasing effect. However, the applicant of US7920018 identifies a drawback of this conventional approach as the charging/discharging of the N-well's parasitic capacitance, leading to decreased boost efficiency and increased layout area.

Motivation for Combination:
A PHOSITA, aware of the issues with conventional triple-well booster circuits (as described in the background of US7920018 and exemplified by the conventional circuit in Figure 25, which is consistent with the general principles of US6100557A and US6878981B2), would be motivated to find ways to improve efficiency and reduce layout area. The problem explicitly stated in US7920018 is the current consumption and layout area increase due to the parasitic capacitance of the N-well being charged and discharged by clock signals in a conventional triple-well structure where the N-well is connected to the source.

Given the goal of improving boost efficiency and reducing current consumption and layout area, a PHOSITA would seek methods to minimize the voltage swing of the N-well or to share N-well regions. Analog comparison circuits are well-known components for comparing voltage levels and generating control signals. The idea of using an analog comparison circuit to fix or control the N-well potential to either the input or output potential of a boosting cell stage, as proposed in US7920018, directly addresses the problem of N-well parasitic capacitance charging and discharging. By selecting the higher or lower of potentials from corresponding stages in parallel boosting cell rows, the N-well potential could be dynamically adjusted to minimize the voltage difference between the N-well and the substrate, thereby reducing the amount of charge that needs to be moved into and out of the N-well.

Specifically, US6100557A discloses the triple-well structure. US6878981B2 further details how to manage body bias in such structures by connecting the N-well to the source. The problem identified in US7920018 with this approach is the N-well's parasitic capacitance. A PHOSITA, seeking to overcome this problem, would look for ways to stabilize or control the N-well potential more effectively than simply connecting it to the source. An analog comparison circuit, capable of sensing potentials and outputting a specific bias, would be a logical tool to achieve this. The motivation would be to maintain the benefits of suppressing the substrate biasing effect (as taught by US6878981B2 and the conventional circuit) while simultaneously mitigating the disadvantages of N-well parasitic capacitance by actively controlling its potential based on the dynamic voltages within the boosting cell stages, especially in a multi-stage, multi-row configuration. The concept of comparing potentials across different rows and stages to derive an optimal well bias is an engineering choice to optimize the known triple-well structure for efficiency and area.

Therefore, combining the teaching of triple-well charge pumps from US6100557A (or US6878981B2) with the understanding of the N-well parasitic capacitance problem (as explained in US7920018's background) would lead a PHOSITA to employ an analog comparison circuit to provide a more controlled N-well bias, aiming to reduce current consumption and layout area.

Combination 2: US6888400B2 in view of US6121821A and US7123077B2

Claim Elements Addressed: This combination addresses the general concept of reducing body effects in charge pump circuits and extending it to a multi-row configuration with N-well potential control via an analog comparison circuit.

Prior Art Disclosures:

• US6888400B2 (Charge pump circuit without body effects): This patent explicitly aims to provide a charge pump circuit that is free from body effects, using specific transistor arrangements to achieve this. It addresses the fundamental problem of body biasing, which US7920018 also seeks to mitigate.
• US6121821A (Booster circuit for semiconductor device): This reference describes a booster circuit generally, which could include multiple stages or be part of a larger system. While it may not specifically detail triple-well N-well control via analog comparison, it represents the broader field of booster circuit design.
• US7123077B2 (Four-phase charge pump circuit with reduced body effect): This patent, like US6888400B2, focuses on reducing body effects in charge pump circuits, specifically in a four-phase configuration. The explicit mention of "reduced body effect" signifies the ongoing effort in the art to overcome this challenge.

Motivation for Combination:
A PHOSITA would be well aware of the limitations imposed by body effects on the performance of charge pump circuits, as evidenced by references like US6888400B2 and US7123077B2, which directly address this issue. The goal of US7920018 to suppress the substrate biasing effect in triple-well structures aligns directly with the objectives of these prior art documents.

Given the existing knowledge of reducing body effects (US6888400B2, US7123077B2) and the general architecture of booster circuits (US6121821A), a PHOSITA would be motivated to apply solutions for body effect reduction to more complex booster circuit designs, such as those with multiple stages and parallel rows. The specific challenge addressed by US7920018 is applying body effect reduction techniques in a way that also reduces current consumption and layout area, particularly when N-wells are involved in triple-well devices.

The analog comparison circuit described in US7920018 offers a means to dynamically control the N-well potential, which is a sophisticated approach to mitigating body effects and parasitic capacitance issues simultaneously. If prior art already teaches reducing body effects and utilizing triple-well structures, then the next logical step for a PHOSITA facing the problems of current consumption and layout area (as described in US7920018) would be to implement a more active and optimized control scheme for the well potentials. An analog comparison circuit is a standard building block for voltage regulation and comparison, making its application to sense and control N-well potentials a design choice driven by known problems and available tools to achieve improved efficiency and smaller footprint.

For instance, US6888400B2 describes a charge pump without body effects. If a PHOSITA were to implement this in a multi-stage, multi-row booster circuit (as generally understood from the field of US6121821A), and encountered the N-well parasitic capacitance issue described in US7920018, they would seek methods to further optimize. Dynamically choosing the higher or lower potential of adjacent stages/rows via an analog comparator to bias the N-well would be an obvious design choice to minimize voltage swings across the N-well junction and reduce the associated charging/discharging current and thus current consumption, while also enabling sharing of N-well regions to reduce layout area.

Conclusion on Obviousness

The core inventive step of US7920018 lies in using an analog comparison circuit to dynamically control the N-well potential of switching elements in a triple-well structure within a multi-row booster circuit, specifically to reduce parasitic capacitance effects, current consumption, and layout area.

While individual elements like triple-well structures, body effect reduction techniques, and analog comparison circuits were known in the prior art, the specific combination and the explicit motivation to solve the N-well parasitic capacitance and layout area problem in multi-row booster circuits using an analog comparison circuit for dynamic N-well biasing could be argued as non-obvious.

However, a PHOSITA would have been motivated to combine these known elements to address the acknowledged problems in existing booster circuit designs. The desire to improve efficiency (reduce current consumption) and reduce physical footprint (layout area) are common driving forces in semiconductor circuit design. Given the recognition of N-well parasitic capacitance as a source of inefficiency and increased area in conventional triple-well booster circuits, and the availability of analog comparison circuits for voltage control, a PHOSITA would likely consider solutions that involve actively managing well potentials. The selection of the higher or lower potential of adjacent stages/rows to bias the N-well of switching elements would represent an engineering optimization based on known circuit behaviors and components, aimed at directly mitigating the identified problems.

Therefore, while the specific implementation detailed in US7920018 offers advantages, the underlying principle of using an analog comparison circuit to dynamically control N-well potentials in triple-well devices within a multi-stage, multi-row booster circuit to improve efficiency and reduce area could be considered obvious to a PHOSITA. The combination of prior art focusing on triple-well structures (US6100557A, US6878981B2), body effect reduction (US6888400B2, US7123077B2), and general booster circuit design (US6121821A) would provide sufficient motivation and means for a PHOSITA to arrive at the claimed invention, particularly given the explicit problem statement provided in US7920018 itself regarding the shortcomings of prior art solutions.