US 7888195

US Patent 7888195, titled "Metal gate transistor and method for fabricating the same," was filed on August 26, 2008, and issued on February 15, 2011. [cite: The full patent text confirms filing and issue dates.]

The original assignee was United Microelectronics Corp, with the current assignee being Marlin Semiconductor Ltd as of July 26, 2021. The inventors listed are Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, and Cheng-Hsien Chou.

Abstract:
"A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region."

Independent Claims Overview:

• Independent Claim 1: This claim describes a method for creating a metal gate transistor. The method involves starting with a substrate that has two transistor regions (e.g., NMOS and PMOS). Dummy gate structures are first created on this substrate. Source and drain regions are then formed on either side of these dummy gates. A dielectric layer is deposited over the entire structure, covering the dummy gates. The dummy gates are then removed, leaving openings in the dielectric layer. A high-k dielectric layer is then formed, lining these openings and covering the top of the dielectric layer. A first cap layer is deposited on the high-k dielectric layer. This first cap layer is then selectively removed from the second transistor region. Finally, a metal layer is formed, covering the remaining first cap layer in the first transistor region and directly on the high-k dielectric layer in the second transistor region. This process essentially details a "gate-last" approach to fabricating metal gates with different work functions for different transistor types using a selective cap layer.

Legal Status and Dockets (as of April 26, 2026):
The patent is currently active and is anticipated to expire on August 26, 2028. There is an Inter Partes Review (IPR) case, IPR2026-00261, filed against this patent and is currently pending before the Patent Trial and Appeal Board (PTAB). The petitioner for this IPR case is Unified Patents.

No specific dockets for US7888195 were found in the CAFC 2026 dockets via the search. The search results provided general information about CAFC activity in 2026, including some patent infringement cases and PTAB decisions, but none directly mention US7888195.