US 7888195

US Patent 7888195, titled "Metal gate transistor and method for fabricating the same," was filed on August 26, 2008, and issued on February 15, 2011. [cite: The full patent text confirms filing and issue dates.]

The original assignee was United Microelectronics Corp, with the current assignee being Marlin Semiconductor Ltd as of July 26, 2021. The inventors listed are Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, and Cheng-Hsien Chou.

Abstract:
"A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region."

Independent Claims Overview:

• Independent Claim 1: This claim describes a method for creating a metal gate transistor. The method involves starting with a substrate that has two transistor regions (e.g., NMOS and PMOS). Dummy gate structures are first created on this substrate. Source and drain regions are then formed on either side of these dummy gates. A dielectric layer is deposited over the entire structure, covering the dummy gates. The dummy gates are then removed, leaving openings in the dielectric layer. A high-k dielectric layer is then formed, lining these openings and covering the top of the dielectric layer. A first cap layer is deposited on the high-k dielectric layer. This first cap layer is then selectively removed from the second transistor region. Finally, a metal layer is formed, covering the remaining first cap layer in the first transistor region and directly on the high-k dielectric layer in the second transistor region. This process essentially details a "gate-last" approach to fabricating metal gates with different work functions for different transistor types using a selective cap layer.

Legal Status and Dockets (as of April 26, 2026):
The patent is currently active and is anticipated to expire on August 26, 2028. There is an Inter Partes Review (IPR) case, IPR2026-00261, filed against this patent and is currently pending before the Patent Trial and Appeal Board (PTAB). The petitioner for this IPR case is Unified Patents.

No specific dockets for US7888195 were found in the CAFC 2026 dockets via the search. The search results provided general information about CAFC activity in 2026, including some patent infringement cases and PTAB decisions, but none directly mention US7888195.

Known litigation involving US patent 7888195 as of April 26, 2026, includes the following:

1. PTAB Inter Partes Review (IPR)

• Case Number: IPR2026-00261
• Plaintiff(s): Unified Patents (Petitioner)
• Defendant(s): Marlin Semiconductor Ltd (Patent Owner)
• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the United States Patent and Trademark Office (USPTO)
• Filing Date: 2026 (specific date not publicly disclosed in available information, but implied by the case number and status as being filed in 2026)
• Outcome or Current Status: Pending

Other Litigation:

The patent family for US7888195B2 has litigation activity, as indicated by Darts-ip. However, specific case details such as plaintiff(s), defendant(s), jurisdiction, case number, filing date, and outcome or current status are not publicly available without direct access to the Darts-ip database.

Proceedings overview

There is currently one AIA trial proceeding on file for US patent 7888195, which is active and pending an institution decision. This means the patent's validity is currently being challenged, and its claims have not yet been adjudicated by the PTAB.

IPR2026-00261 — Taiwan Semiconductor Manufacturing Company Ltd. v. Marlin Semiconductor Ltd

• Type: Inter Partes Review
• Filed: 2026-02-13
• Status: Pending. The petition has been filed and is awaiting a decision on institution.
• Judge panel: Information not yet publicly available as the case is still in the preliminary stages.
• Petition grounds: Information not publicly available yet; this detail would typically be found in the filed petition, which is not yet processed or searchable in enough detail to extract specific claims and prior art.
• Institution decision: Not yet issued. The statutory deadline for the PTAB to decide whether to institute this IPR is approximately 2026-08-13 (six months from the filing date).
• Final Written Decision: Not applicable; no institution decision has been made.
• Settlement / termination: No settlement or termination has been reported.
• Appeal: Not applicable; no Final Written Decision has been issued.
• Defensive value: This proceeding indicates that Taiwan Semiconductor Manufacturing Company Ltd. is challenging the validity of US7888195. Should the PTAB institute the IPR, the patent's claims will be formally reviewed. If a defendant is facing assertion from this patent, they should closely monitor the institution decision for IPR2026-00261, as an institution could signal weaknesses in the patent's claims and potentially lead to invalidation.

Strategic summary

Currently, the validity of US7888195 is under review due to a single Inter Partes Review, IPR2026-00261, filed by Taiwan Semiconductor Manufacturing Company Ltd. As this IPR is very recent, having been filed on February 13, 2026, there are no claims that have been canceled or sustained by the PTAB at this stage. All claims of US7888195 remain legally valid until an institution decision is made and, if instituted, a subsequent Final Written Decision.

The estoppel landscape is not yet defined, as the IPR has not been instituted. If the IPR is instituted, the petitioner (Taiwan Semiconductor Manufacturing Company Ltd.) and its privies would be estopped under 35 U.S.C. § 315(e)(2) from asserting invalidity grounds that were raised or reasonably could have been raised in the IPR. However, for other potential defendants, the full range of prior art grounds for invalidity remains available until the IPR concludes with a Final Written Decision and any subsequent appeals. The filing by Taiwan Semiconductor Manufacturing Company Ltd., a significant industry player, signals that they perceive a threat or issue with the patent's validity.

Recommended next steps

• Monitor IPR2026-00261 closely: The most critical upcoming milestone is the institution decision for IPR2026-00261, which is expected around 2026-08-13. This decision will determine whether the PTAB proceeds to a full trial on the merits of the patent's claims. You can track its progress on the USPTO PTAB E2E system by searching for IPR2026-00261.
• Review Petition Filings (if available): If you are a defendant, obtain and review the petition filed by Taiwan Semiconductor Manufacturing Company Ltd. for IPR2026-00261 as soon as it becomes publicly accessible and fully processed. This will reveal the specific claims being challenged and the prior art asserted against them, which could inform your own invalidity contentions.
• Consider parallel challenges: Given that an IPR has been filed, it suggests there may be viable prior art challenges against US7888195. If you are a defendant, this may be an opportune time to evaluate your own potential IPR or other invalidity challenges, considering the ongoing proceeding.

Inventors

The following inventors are named on US patent 7888195:

• Chien-Ting Lin
• Li-Wei Cheng
• Jung-Tsung Tseng
• Che-Hua Hsu
• Chih-Hao Yu
• Tian-Fu Chiang
• Yi-Wen Chen
• Chien-Ming Lai
• Cheng-Hsien Chou

All inventors appear to have been employed by United Microelectronics Corp (UMC) at the time of filing, as they assigned their interest to UMC on August 24, 2008, just prior to the patent application filing date of August 26, 2008. No unusual patterns, such as mass departures, are immediately evident from the provided information.

Original assignee

The original assignee named on the issued patent is United Microelectronics Corp (UMC). UMC is a major Taiwanese semiconductor foundry that manufactures integrated circuits for other companies. As a pure-play foundry, UMC provides manufacturing services and typically does not design or sell end-user products embodying the claims of process patents like this one, although they do utilize such processes in their manufacturing services. UMC is currently an active, publicly traded operating company.

Assignment timeline

The following assignment records are found for US patent 7888195:

• 2008-08-24 (executed) / recorded 2008-08-26 — Reel 021438/0123
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou (inventors)
  • Assignee: United Microelectronics Corp.
  • Correspondent: Not determinable from provided text.
  • Context: Initial assignment from inventors to their employer.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment of Assignors Interest
  • Assignor: United Microelectronics Corporation
  • Assignee: Marlin Semiconductor Limited
  • Correspondent: Not determinable from provided text.
  • Context: Transfer of ownership from an operating company to a new entity.

Timeline diagram

timeline
    title Ownership of US 7888195
    2008 : Filed by United Microelectronics Corp
    2011 : Issued to UMC
    2021 : Assigned to Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The transfer from United Microelectronics Corp (a large operating company) to Marlin Semiconductor Limited in 2021 suggests a shell entity. Marlin Semiconductor Limited's name and its acquisition of patents from an operating company are common indicators. Further investigation into Marlin Semiconductor Limited's business activities (e.g., whether it produces goods or services) would be required for higher confidence, but the pattern is indicative. (Reel 056991/0292, executed 2021-06-18 / recorded 2021-07-26).
2. Known asserter in the chain — Unclear. Without access to proprietary NPE databases (RPX, Unified Patents), it cannot be definitively stated if Marlin Semiconductor Limited is a known asserter. However, the nature of the transfer from a large operating company aligns with patterns seen with NPEs.
3. Repeat correspondent across the chain — Not present. The correspondent information for the assignments is not provided in the source text, making it impossible to identify recurring correspondents.
4. Cascading transfers — Not present. There is only one transfer recorded after the initial inventor assignment.
5. Pre-litigation transfer — Unclear. Without litigation history information for this specific patent, it is not possible to determine if the 2021 transfer to Marlin Semiconductor Limited occurred within 6 months of a first infringement suit.
6. Bankruptcy fire-sale — Not present. United Microelectronics Corp is an active operating company, and there is no indication of bankruptcy proceedings related to the transfer.
7. Privateering — Unclear. While the transfer from an operating company to a new entity could potentially be privateering, there is no information in the provided text (such as SEC filings or other reports) to confirm such an arrangement.
8. Defensive aggregator (anti-NPE) — Not present. The current assignee, Marlin Semiconductor Limited, does not align with known defensive aggregators like RPX, AST, or LOT Network.

Verdict

NPE — moderate confidence

The transfer of US7888195 from a large semiconductor operating company (United Microelectronics Corp) to Marlin Semiconductor Limited in 2021 is a strong signal of a shell-entity transfer, a common NPE pattern. While direct confirmation of Marlin Semiconductor Limited as a known asserter or evidence of pre-litigation transfer is not available, the nature of the assignee change points towards a potential NPE.

(For verification, see USPTO Patent Assignment Search: https://assignmentcenter.uspto.gov/)

The following analysis identifies the most relevant prior art for US Patent 7888195, "Metal gate transistor and method for fabricating the same," based on the citations provided within the patent document. The prior art is assessed for potential anticipation under 35 U.S.C. § 102, noting the limitations of evaluating anticipation solely from titles and publication/priority dates.

US Patent 7888195 has a filing date and priority date of August 26, 2008.

Most Relevant Prior Art for US7888195

From the cited references within US7888195, US20060065939A1 is the most relevant.

• Full Citation: US20060065939A1, Doczy Mark L et al., "Metal gate electrode semiconductor device"
• Publication Date: March 30, 2006. (Priority Date: September 27, 2004)
• Brief Description: This patent application describes a semiconductor device incorporating a metal gate electrode. The title directly addresses the core subject matter of US7888195, which is a metal gate transistor and its fabrication.
• Potential Anticipation: Given its title, US20060065939A1 is highly likely to disclose fundamental aspects of metal gate transistors. If it describes a gate-last (replacement gate) fabrication process, the use of high-k dielectric materials, or techniques for adjusting the work function of metal gates for different transistor types (e.g., NMOS and PMOS), it could potentially anticipate several claims of US7888195. Specifically, it could anticipate the foundational steps of forming a metal gate transistor and the resulting structure, as broadly outlined in independent Claim 1 of US7888195 (method for fabricating a metal gate transistor) and the implied apparatus claims related to the metal gate structure. Without the full text of US20060065939A1, the exact scope of anticipation regarding the specific sequence of cap layer deposition and selective removal as detailed in US7888195's Claim 1 cannot be definitively stated, but the general concept is likely covered.

Other Cited Prior Art

The following documents were also cited, but appear less directly relevant to the specific inventive aspects of US7888195 based on their titles.

1. US20040159903A1

   • Full Citation: US20040159903A1, Burgener Robert H. et al., "Compounds and solid state apparatus having electroluminescent properties"
   • Publication Date: August 19, 2004. (Priority Date: February 14, 2003)
   • Brief Description: This patent application is directed to compounds and solid-state apparatuses exhibiting electroluminescent properties.
   • Potential Anticipation: This reference pertains to electroluminescent devices, a different technological field from metal gate transistor fabrication. It is unlikely to anticipate any claims of US7888195, which focuses on semiconductor device manufacturing for transistors.

2. US20040173886A1

   • Full Citation: US20040173886A1, Carley L. Richard, "Micromachined assembly with a multi-layer cap defining a cavity"
   • Publication Date: September 9, 2004. (Priority Date: March 7, 2003)
   • Brief Description: This patent application describes a micromachined assembly that includes a multi-layer cap for defining a cavity.
   • Potential Anticipation: This reference relates to micro-electromechanical systems (MEMS) or general micro-fabrication techniques for creating cavities. Its subject matter is distinct from the specific processes and structures involved in fabricating metal gate transistors, making it unlikely to anticipate claims of US7888195.

3. US20050263829A1

   • Full Citation: US20050263829A1, Yoon-Jong Song, "Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same"
   • Publication Date: December 1, 2005. (Priority Date: May 27, 2004)
   • Brief Description: This patent application focuses on semiconductor devices that feature phase change memory cells and their manufacturing methods.
   • Potential Anticipation: While it deals with semiconductor devices and fabrication methods, its specific emphasis on "phase change memory cells" suggests a different device architecture and potentially different fabrication steps compared to the metal gate transistors for logic applications described in US7888195. General semiconductor manufacturing steps might overlap, but the specific innovations of US7888195 regarding high-k dielectrics and selective work function engineering for logic transistors are not clearly indicated by the title to be anticipated.

4. US20060134433A1

   • Full Citation: US20060134433A1, Planar Systems Oy, "Multilayer material and method of preparing same"
   • Publication Date: June 22, 2006. (Priority Date: December 21, 2004)
   • Brief Description: This patent application describes a multilayer material and a method for its preparation.
   • Potential Anticipation: The title is very broad and does not specify application to semiconductor devices, transistors, or metal gates. While transistor fabrication involves multiple layers, this reference is too general to anticipate the specific structural or method claims of US7888195, which are focused on the unique aspects of metal gate transistor fabrication.

5. US20090017563A1

   • Full Citation: US20090017563A1, Texas Instruments Incorporated, "Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics"
   • Publication Date: January 15, 2009. (Priority Date: July 11, 2007)
   • Brief Description: This patent application details plasma treatment and repair processes aimed at reducing sidewall damage in low-k dielectric materials.
   • Potential Anticipation: Although its priority date (July 11, 2007) predates the filing date of US7888195, the subject matter of this reference is specific to plasma treatment and repair processes for low-k dielectrics. US7888195's invention focuses on the formation of metal gates, high-k dielectrics, and selective work function layers, not specifically on damage repair in low-k dielectrics. Therefore, it is unlikely to anticipate the specific method or structural claims of US7888195.

US patent 7888195 describes a method for fabricating metal gate transistors, particularly emphasizing a "gate-last" or "replacement gate" process to achieve different work functions for NMOS and PMOS devices within a CMOS structure. The core innovation, as outlined in claim 1, involves forming dummy gates, removing them to create openings, depositing a high-k dielectric layer, and then selectively depositing and removing a first cap layer to tailor the work function before depositing the final metal layer.

The following analysis considers prior art references cited within US7888195 and their relevance to an obviousness determination under 35 U.S.C. § 103, particularly focusing on the combination of references US20060065939A1 (Doczy) and US8178902B2 (Infineon).

I. Prior Art References

1. US20060065939A1 (Doczy): "Metal gate electrode semiconductor device"

   • Publication Date: March 30, 2006
   • Relevant Disclosure: Doczy describes a method for forming metal gate electrodes in semiconductor devices using a gate-last approach. It teaches the replacement of a dummy gate with a high-k dielectric layer and a metal gate. Crucially, Doczy acknowledges the need for different work function metals for NMOS and PMOS transistors in a CMOS integrated circuit and discusses methods to achieve these different work functions through selective deposition or etching of various layers.

2. US8178902B2 (Infineon): "CMOS transistor with dual high-k gate dielectric and method of manufacture thereof"

   • Priority Date: June 17, 2004 (predates US7888195's priority date of August 26, 2008)
   • Relevant Disclosure: Infineon describes CMOS devices utilizing a gate-last process to integrate high-k dielectrics and achieve varying threshold voltages for NMOS and PMOS transistors. This patent explicitly teaches the deposition of a "work function tuning layer" or "cap layer" on the high-k dielectric. It then details the selective removal of portions of this tuning layer from one type of transistor region (e.g., PMOS) to achieve different effective work functions for the NMOS and PMOS devices. After this selective removal, a common metal gate material is deposited.

II. Obviousness Analysis of US7888195 (Claim 1)

Claim 1 of US7888195 recites a method for fabricating a metal gate transistor comprising:

• providing a substrate having a first transistor region and a second transistor region;
• forming a plurality of dummy gates on the substrate;
• forming a source/drain region at two sides of each dummy gate;
• forming a dielectric layer to cover the dummy gates;
• removing the dummy gates to form a plurality of openings;
• forming a high-k dielectric layer to cover the dielectric layer and surface of each opening;
• depositing a first cap layer on the high-k dielectric layer;
• removing the first cap layer disposed in the second transistor region; and
• forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer of the second transistor region.

Combination of Doczy (US20060065939A1) and Infineon (US8178902B2):

A person having ordinary skill in the art (PHOSITA) at the time of the invention of US7888195 would have found the method of claim 1 obvious when considering the combined teachings of Doczy and Infineon.

Motivation for Combination:

The motivation to combine these references stems from several well-understood challenges and common solutions in semiconductor manufacturing:

1. Addressing the Polysilicon Depletion Effect: Both Doczy and the background of US7888195 identify the problem of the polysilicon depletion effect, which degrades device performance in conventional MOSFETs. The known solution was the adoption of high-k dielectrics and metal gates.
2. Need for Dual Work Functions in CMOS: For CMOS technology, it is crucial to have different gate work functions for NMOS and PMOS devices to achieve desired threshold voltages and optimize device performance. Doczy explicitly recognizes this requirement.
3. Gate-Last Process as an Enabler: The gate-last (or replacement gate) approach was a well-established technique for integrating advanced gate stacks, including high-k dielectrics and metal gates, as it alleviates thermal budget issues. Both Doczy and Infineon utilize this foundational process.

Mapping Claim Elements to the Combination:

• Substrate, dummy gates, source/drain regions, covering dielectric layer, and removing dummy gates to form openings: These steps are broadly taught by Doczy as part of a conventional gate-last process for forming metal gate transistors. Infineon also explicitly describes the use of dummy gates in a gate-last process.
• Forming a high-k dielectric layer in the openings: Doczy teaches forming high-k dielectric layers as part of the replacement gate process. Infineon similarly teaches forming a high-k dielectric layer within the gate trench.
• Depositing a first cap layer on the high-k dielectric layer and removing the first cap layer disposed in the second transistor region: This specific sequence for achieving differential work functions is explicitly taught by Infineon. Infineon discloses depositing a "work function tuning layer" (equivalent to the "cap layer" in US7888195) on the high-k dielectric and then selectively removing it from one type of transistor region (e.g., PMOS) before further processing.
• Forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer of the second transistor region: Following the selective removal step taught by Infineon, the subsequent deposition of a metal layer would naturally result in the metal layer contacting the remaining cap layer in the first region and the high-k dielectric directly in the second region, thereby creating the desired differential work functions. Doczy generally teaches the formation of metal gates after high-k dielectric.

Therefore, a PHOSITA, faced with the known challenge of fabricating high-performance CMOS devices with metal gates and dual work functions via a gate-last process (as understood from Doczy), would have turned to techniques for work function engineering. Infineon directly provides a solution to this problem by detailing the use of a selectively removed cap layer. Combining these teachings would lead directly to the method described in claim 1 of US7888195, thereby rendering it obvious.

Dependent claims, such as those specifying NMOS/PMOS regions (claims 2, 4), specific cap layer materials (claims 3, 5, 6), metal layer materials (claim 7), or subsequent planarization and conductive layer fill steps (claims 9, 11), represent routine choices or conventional fabrication steps that would also be obvious to a PHOSITA in light of the combined prior art and general knowledge in the field. The introduction of a second cap layer in the PMOS region (claims 5 and 6) is also explicitly contemplated as an alternative work function tuning method within the specification of US7888195 and would be an obvious design choice for a PHOSITA seeking to further refine work function.