US 7007259

Here's a concise summary of US Patent 7007259:

US Patent Number: US7007259B2

Title: Method for providing clock-net aware dummy metal using dummy regions

Inventors: Vikram Shrowty; Santhanakrishnan Raman

Current Assignee: Bell Semiconductor LLC (as of December 17, 2017)

Original Assignee: LSI Logic Corp

Filing Date: July 31, 2003

Issue Date: February 28, 2006

Abstract:
A method and system for inserting dummy metal into a circuit design is disclosed, specifically for designs including a plurality of objects and clock nets. The invention involves identifying free spaces on each layer of the chip as "dummy regions" suitable for dummy metal insertion. These dummy regions are then prioritized so that those located adjacent to clock nets are filled with dummy metal last, aiming to minimize timing impact on the clock nets. In a preferred embodiment, further prioritization ensures that dummy regions adjacent to wider clock nets are filled after those adjacent to narrower clock nets.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method for Inserting Dummy Metal): This claim describes a method for placing inactive metal (dummy metal) into an integrated circuit design. The method involves two primary steps:

  1. Finding empty areas on each layer of the chip, which are designated as "dummy regions."
  2. Deciding the order in which these dummy regions will be filled. Crucially, the dummy regions that are next to "clock nets" (wires that carry timing signals) are filled last. This strategy is used to reduce any negative effects the dummy metal might have on the timing of the clock signals.

• Claim 18 (Computer-Readable Medium): This claim covers a computer program (stored on a computer-readable medium) that, when executed, performs the same two main steps described in Claim 1. That is, it identifies dummy regions and then prioritizes them so that dummy metal is inserted into clock-net adjacent regions last, thereby minimizing timing impact.

• Claim 35 (Method for Inserting Dummy Metal with Timing Factors): This claim outlines a more detailed method for inserting dummy metal:

  1. Identifying free spaces on each layer as dummy regions.
  2. Determining which of these dummy regions are located next to clock nets.
  3. Assigning a "timing factor" to each dummy region. This factor is based on the width of the clock net wire it is adjacent to (wider wires are generally more critical for timing).
  4. Sorting all the dummy regions according to these timing factors.
  5. Inserting dummy metal into the sorted regions. The insertion is done in an order where regions next to progressively wider clock nets are filled last, again to minimize any negative timing impact on the clock nets.

Litigation Information:
The patent "Family has litigation," with a "US case filed in Court of Appeals for the Federal Circuit" identified by case number 24-1057. While this patent has been noted as "Expired - Lifetime" as of April 16, 2024, the listed CAFC case indicates that litigation involving this patent family existed. A search for "CAFC 2026 dockets" provided a schedule of cases for May 2026, but case number 24-1057 was not explicitly listed among those scheduled for that month, so its specific status within 2026 dockets beyond its initial filing is not definitively confirmed by the provided search results.