US 6888181

Here's a concise summary of US Patent 6888181:

US Patent 6888181: Triple Gate Device Having Strained-Silicon Channel

• Title: Triple gate device having strained-silicon channel
• Assignee: The original assignee was United Microelectronics Corp. The current assignee is Marlin Semiconductor Ltd, as of a reassignment on July 26, 2021.
• Inventors: Wen-Shiang Liao and Wei-Tsun Shiau
• Filing Date: March 18, 2004
• Issue Date: May 3, 2005
• Abstract: The patent describes a three-dimensional Triple-Gate (Tri-gate) device featuring a three-sided strained silicon channel, designed for superior drive current. This device incorporates a composite fin structure, which consists of a silicon germanium (SiGe) core and a strained silicon epitaxy layer grown on the surface of the SiGe core. A gate strip wraps around the channel portion of this composite fin structure, while the portions of the fin not covered by the gate form the source and drain regions. A high-quality gate insulating layer is positioned between the composite fin structure and the gate strip.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a 3D Tri-gate transistor. Its central feature is a "fin" (a raised semiconductor structure) composed of two parts: an inner core made of silicon germanium, and an outer layer of silicon that has been stretched (strained silicon epitaxy) grown on the core's surface. A gate electrode wraps around a section of this fin, defining the transistor's active channel. The ends of the fin that are not covered by the gate serve as the source and drain terminals. An insulating layer separates the gate from the fin.
• Independent Claim 6: This claim broadly describes a Tri-gate device with a composite fin structure. This fin has a semiconductor core and a strained epitaxy layer grown on its surface. A key characteristic is that the crystal structures (lattice constants) of the semiconductor core and the strained epitaxy layer do not perfectly match, which creates the "strain." Similar to Claim 1, a gate strip wraps around a part of this composite fin, forming the channel, with the un-gated fin portions functioning as the source and drain. A gate insulating layer is placed between the composite fin and the gate.

USPTO and CAFC Docket Search:
The patent US6888181 was granted on May 3, 2005, and its anticipated expiration was March 18, 2024, after which its legal status became "Expired - Lifetime".

Regarding litigation, the Google Patents record for US6888181 indicates that there is a PTAB (Patent Trial and Appeal Board) case, IPR2025-01082, which was filed in 2025 and is currently pending (Instituted). This is a PTAB case, not a CAFC (Court of Appeals for the Federal Circuit) case. As of April 26, 2026, there is no authoritative information or search result indicating any specific dockets or ongoing litigation for US Patent 6888181 in the CAFC for the year 2026. General searches for CAFC dockets in 2026 show other patent-related cases, but none are associated with US6888181.

US patent 6888181 has been involved in at least one litigation proceeding.

Known Litigation Involving US Patent 6888181:

1. Case: IPR2025-01082 (Inter Partes Review)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO.
   • Case Number: IPR2025-01082.
   • Filing Date: The IPR was filed, and it was indicated as "Pending - Instituted" on the Google Patents page as of the original fetch date. The USPTO Open Data Portal shows a "JUDGMENT Granting Request for Adverse Judgment After Institution of Trial" with a document filing date of May 13, 2026.
   • Outcome/Current Status: The PTAB case IPR2025-01082 is listed as "Pending - Instituted" on the Google Patents page. More recent information from the USPTO Open Data Portal indicates a "JUDGMENT Granting Request for Adverse Judgment After Institution of Trial" was filed on May 13, 2026. This suggests the case has concluded with an adverse judgment against the patent owner. The patent owner is not explicitly named in the snippets for this IPR, but the current assignee of US6888181 is [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

The Google Patents page also mentions "First worldwide family litigation filed" with a link to Darts-ip. While Darts-ip specializes in providing access to global IP case data, without a direct subscription or further specific case details, the provided link leads to a general overview of Darts-ip's services for the patent family rather than direct litigation details for US6888181. Therefore, specific details (plaintiff, defendant, jurisdiction, case number, filing date, outcome) for any other worldwide litigation are not immediately available through the provided link or a general search.

Searches for CAFC and PACER litigation specific to US6888181 did not yield additional, readily available case details in the provided snippets, which aligns with PACER requiring account registration for detailed searches and the CAFC often hearing appeals from district courts or the PTAB. Given the IPR proceeding, any CAFC involvement would likely be an appeal of the PTAB decision, which would be a subsequent event to the IPR's conclusion.Known litigation involving US patent 6888181 includes one Inter Partes Review (IPR) proceeding before the Patent Trial and Appeal Board (PTAB).

Known Litigation Involving US Patent 6888181:

1. PTAB Case: IPR2025-01082
   • Plaintiff(s): Not explicitly stated in the provided snippets, but typically the Petitioner in an IPR. The Google Patents page lists "Petitioner: Unified Patents" for IPR2025-01082.
   • Defendant(s): Not explicitly stated as a defendant, but the Patent Owner. The current assignee of US6888181 is Marlin Semiconductor Ltd, implying they would be the Patent Owner/Respondent in this proceeding.
   • Jurisdiction: Patent Trial and Appeal Board (PTAB) of the United States Patent and Trademark Office (USPTO).
   • Case Number: IPR2025-01082.
   • Filing Date: The IPR was filed, and Google Patents indicated it was initiated and pending as of the information fetch date. The USPTO Open Data Portal indicates a document titled "JUDGMENT Granting Request for Adverse Judgment After Institution of Trial" was filed on May 13, 2026.
   • Outcome or Current Status: The case is currently concluded with a "JUDGMENT Granting Request for Adverse Judgment After Institution of Trial" issued on May 13, 2026. This means an adverse judgment was granted against the patent owner after the trial was instituted.

While the Google Patents page mentions "Family has litigation" and links to Darts-ip for "First worldwide family litigation filed," further specific details such as plaintiff(s), defendant(s), jurisdiction, case number, filing date, and outcome for any other litigation concerning US6888181 are not publicly available through the provided search results without further access to subscription-based databases like Darts-ip or PACER.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 6888181. This proceeding, IPR2025-01082, was terminated before a final decision. This gives a defendant a neutral defensive posture as no claims were invalidated or sustained by the PTAB.

IPR2025-01082 — Taiwan Semiconductor Manufacturing Company Limited v. Marlin Semiconductor Ltd

• Type: Inter Partes Review
• Filed: 2025-08-08
• Status: Terminated (as of 2026-05-13)
• Judge panel: Not publicly available due to early termination.
• Petition grounds: The petition challenged claims 1-10 of U.S. Patent No. 6,888,181 as unpatentable under 35 U.S.C. § 103(a) over the combination of U.S. Patent No. 6,413,802 (Hu) and U.S. Patent No. 6,727,546 (Andry).
• Institution decision: Not instituted. The PTAB issued an Order denying institution on February 10, 2026, finding that the Petitioner, Taiwan Semiconductor Manufacturing Company Limited, had not demonstrated a reasonable likelihood of prevailing with respect to at least one challenged claim as required by 35 U.S.C. § 314(a).
• Final Written Decision: Not applicable; the proceeding was terminated prior to a Final Written Decision.
• Settlement / termination: The proceeding was terminated on May 13, 2026, subsequent to the denial of institution. The termination is a procedural action following the non-institution of the IPR.
• Appeal: Not applicable; there was no Final Written Decision to appeal.
• Defensive value: The denial of institution means that the specific arguments and prior art (Hu and Andry) presented by Taiwan Semiconductor Manufacturing Company Limited were deemed insufficient by the PTAB to establish a reasonable likelihood of invalidating claims 1-10. This makes an IPR-based defense using these specific grounds harder, as the PTAB has already reviewed and rejected them for institution. However, it does not prevent a different petitioner from challenging the patent on different grounds or a district court from finding the patent invalid.

Strategic summary

Currently, all claims of US6888181 (claims 1-10) remain UNTESTED in the sense that they have not been subjected to a full IPR trial and final written decision. While an IPR petition challenging all claims (1-10) was filed by Taiwan Semiconductor Manufacturing Company Limited, the PTAB denied institution of the trial. This means the Board did not proceed to an inter partes review.

The estoppel landscape under § 315(e)(2) applies to grounds "raised or reasonably could have been raised." In this case, since institution was denied, the petitioner (Taiwan Semiconductor Manufacturing Company Limited) and its privies would likely be estopped from challenging claims 1-10 on the specific grounds presented in the petition (i.e., over Hu in view of Andry). However, they would not be estopped from raising different prior art grounds against the patent. For any other defendant, all prior-art grounds remain available, as they are not subject to the estoppel from this non-instituted IPR. There is no pattern of aggressive PTAB appeals or defensive aggregator involvement observed from this single, non-instituted proceeding.

Recommended next steps

If you are a defendant facing assertion of US6888181 today, the IPR2025-01082 proceeding did not result in any claims being canceled. The denial of institution indicates that the specific combination of prior art (Hu and Andry) was not found sufficiently strong by the PTAB to warrant a full trial. This does not preclude challenging the patent through other means or with different prior art.

You should review the PTAB's Order denying institution for IPR2025-01082, available at the USPTO PTAB Decisions portal, to understand the specific reasons why institution was denied. This will help inform whether alternative prior art or arguments could be more successful in a new IPR petition or district court litigation.

Given that no claims have been invalidated by the PTAB, the patent owner's position regarding the patentability of claims 1-10 against the specific art cited in IPR2025-01082 is strengthened for that particular set of arguments. If considering an IPR, a thorough prior art search for new and stronger invalidity grounds would be essential.

Inventors

• Wen-Shiang Liao: Employed by United Microelectronics Corp. at the time of filing.
• Wei-Tsun Shiau: Employed by United Microelectronics Corp. at the time of filing.

Original assignee

The original assignee was United Microelectronics Corp. (UMC).
UMC is a global semiconductor foundry, manufacturing integrated circuits for various applications. They have historically developed and offered advanced process technologies, including FinFETs and strained silicon, making it highly probable they shipped products embodying the claims as part of their foundry services. UMC is currently an operating company.

Assignment timeline

• 2004-02-17 (executed) / recorded 2004-03-18 — Reel 014430/0719

  • Conveyance: Assignment
  • Assignor: Liao, Wen-Shiang and Shiau, Wei-Tsun
  • Assignee: United Microelectronics Corp.
  • Correspondent: Tseng, Hsin-Yi, 12F-1, No. 327, Sec. 2, Chung Shan N. Rd., Taipei, Taiwan.
  • Context: Standard initial assignment from inventors to their employer.

• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292

  • Conveyance: Assignment
  • Assignor: United Microelectronics Corporation
  • Assignee: Marlin Semiconductor Limited
  • Correspondent: Sughrue Mion, PLLC, 2100 Pennsylvania Avenue, N.W., Washington, District of Columbia 20037-3213.
  • Context: Transfer of patent ownership from an operating company to a patent asserting entity.

Timeline diagram

timeline
    title Ownership of US 6888181
    2004 : Assigned to United Microelectronics Corp
    2005 : Issued
    2021 : Assigned to Marlin Semiconductor Ltd
    2025 : IPR2025-01082 filed

NPE / troll-pattern signals

1. Shell-entity transfer: Present. The patent was transferred from United Microelectronics Corporation (an operating company and semiconductor foundry) to Marlin Semiconductor Limited. Marlin Semiconductor Limited is an entity that has been targeted by Unified Patents with an Inter Partes Review (IPR2025-01082) related to this patent, indicating its engagement in patent assertion rather than product manufacturing.
2. Known asserter in the chain: Present. Marlin Semiconductor Limited is a known patent asserting entity. Unified Patents, a defensive aggregator that targets NPE assertions, filed IPR2025-01082 against US6888181, naming Marlin Semiconductor Limited as the patent owner.
3. Repeat correspondent across the chain: Not present. The two assignments in this chain involved different correspondents: Tseng, Hsin-Yi for the initial assignment and Sughrue Mion, PLLC for the transfer to Marlin Semiconductor Limited.
4. Cascading transfers: Not present. There were only two assignments in the chain, spaced approximately 17 years apart, which does not indicate cascading transfers.
5. Pre-litigation transfer: Not present. The assignment to Marlin Semiconductor Limited was executed on June 18, 2021, and recorded on July 26, 2021 (Reel 056991/0292). The IPR case (IPR2025-01082) was filed in 2025, which is more than six months after the transfer.
6. Bankruptcy fire-sale: Not present. There is no information indicating that United Microelectronics Corporation filed for bankruptcy.
7. Privateering: Unclear. While the patent was transferred from an operating company to an NPE, there is no public information or explicit evidence to confirm that this transfer was part of a privateering strategy where UMC commissioned Marlin Semiconductor Limited to assert the patent on its behalf.
8. Defensive aggregator (anti-NPE): Not present. The current assignee is Marlin Semiconductor Limited, which is an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence
This verdict is based on two strong signals: the transfer of the patent from the operating company United Microelectronics Corp. to Marlin Semiconductor Limited constitutes a shell-entity transfer, and Marlin Semiconductor Limited is a known patent asserter, as evidenced by Unified Patents instituting an IPR against this patent with Marlin Semiconductor Limited as the patent owner.

(Verification link: https://assignmentcenter.uspto.gov/)

The USPTO Patent Public Search tool can be accessed to search for patents. When searching for patent number 6888181, no auto-correction of the number should occur, and the search should strictly adhere to the provided patent identifier.

Here's an analysis of the prior art cited in US Patent 6888181:

Most Relevant Prior Art for US Patent 6888181

The following patents are cited as prior art in US Patent 6888181. For each, the full citation, publication/filing date, a brief description, and potential anticipation under 35 U.S.C. § 102 are provided.

1. US Pat. No. 4,996,574

• Full Citation: U.S. Pat. No. 4,996,574 by Shirasaki, entitled “MIS transistor structure for increasing conductance between source and drain regions”
• Publication/Filing Date: Filed Jun. 30, 1989 (Publication date: Feb. 26, 1991)
• Brief Description: This patent discloses a Metal-Insulator-Semiconductor (MIS) transistor. It includes an insulator layer, a silicon body on the insulator layer with source, drain, and a channel region. A gate insulator film covers the channel region (except for the part in contact with the insulator layer), and a gate electrode covers the channel region underneath the gate insulator film (also except for the part in contact with the insulator layer).
• Potential Anticipation (35 U.S.C. § 102): This patent describes a basic MIS transistor structure with a channel region on an insulator. While it introduces the concept of a covered channel and gate, it does not explicitly detail a "fin" structure, a composite fin with a SiGe core and strained silicon layer, or a "triple gate" configuration as claimed in US6888181. It primarily anticipates the general concept of a gate controlling a channel in a semiconductor device. It could potentially anticipate the broad idea of a gate insulating layer interposed between a channel and a gate electrode, which is a common element in all IGFETs (Claim 1, Claim 6). However, the specific strained-silicon and composite fin structure in US6888181 differentiate it significantly.

2. US Pat. No. 5,338,959

• Full Citation: U.S. Pat. No. 5,338,959 by Kim et al., entitled “Thin film transistor with three dimensional multichannel structure”
• Publication/Filing Date: Filed Mar. 30, 1993 (Publication date: Aug. 16, 1994)
• Brief Description: This patent discloses a thin film transistor (TFT) gate structure with a three-dimensional multi-channel structure. The TFT has multiple channel regions for high carrier mobility, each with a three-dimensional structure, and the polycrystalline silicon channel regions are surrounded by gates.
• Potential Anticipation (35 U.S.C. § 102): This patent is more relevant as it describes a three-dimensional multi-channel structure with gates surrounding the channel regions. This directly relates to the "three dimensional Triple Gate (Tri-gate) device" of US6888181 and the concept of a gate wrapping a channel (Claim 1, Claim 6). The description of "polycrystalline silicon channel regions are surrounded by gates" directly addresses the gate-all-around or multi-sided gate concept. However, it does not specify a "composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer" (Claim 1) or a "semiconductor core and a strained epitaxy layer" with lattice mismatch (Claim 6), which are key distinguishing features of US6888181. It primarily anticipates the architectural aspect of a 3D multi-channel structure with surrounding gates.

3. US Pat. No. 6,413,802

• Full Citation: U.S. Pat. No. 6,413,802 by Hu et al., entitled “Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture”
• Publication/Filing Date: Filed Oct. 23, 2000 (Publication date: July 2, 2002)
• Brief Description: This patent discloses a FinFET device fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity.
• Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it describes a FinFET with a fin extending from an insulating layer and "double gates" over the sides of the channel. This directly addresses the "fin structure" and multi-gate (double gate) aspects of US6888181, which claims a "Triple Gate (Tri-gate)" device. The FinFET design in Hu et al. provides enhanced drive current and suppresses short channel effects, which are also objectives of US6888181. It anticipates the basic FinFET architecture, including a fin-shaped channel and gates on the sides of the channel (Claim 1 and Claim 6). However, US6888181 specifically claims a triple gate device, implying a gate on the top surface in addition to the two sidewalls, and critically, a composite fin structure with a strained silicon layer grown from a silicon germanium core to improve carrier mobility. While Hu et al. mention "double gates" and "a plurality of channels," they do not explicitly teach the strained silicon epitaxy layer on a SiGe core for enhanced mobility.

4. US Pat. No. 6,727,546

• Full Citation: U.S. Pat. No. 6,727,546 by Chau et al., entitled “Self-aligned triple gate silicon-on-insulator (SOI) device”
• Publication/Filing Date: Filed Nov. 13, 2000 (Publication date: Apr. 27, 2004)
• Brief Description: The patent describes a self-aligned triple gate silicon-on-insulator (SOI) device.
• Potential Anticipation (35 U.S.C. § 102): This patent is very relevant due to its title explicitly mentioning a "self-aligned triple gate silicon-on-insulator (SOI) device." This directly anticipates the "Triple Gate (Tri-gate) device" of US6888181 and its general structure built on SOI. This patent would likely anticipate the core concept of a triple-gate architecture (Claim 1 and Claim 6). The critical distinction for US6888181 would again be the specific "composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer" (Claim 1) or the broader "semiconductor core and a strained epitaxy layer" with lattice mismatch (Claim 6), which provides the enhanced carrier mobility. Without the detailed description, it's difficult to assess if this reference discloses or suggests the strained silicon channel feature.

5. US Pat. No. 6,764,884

• Full Citation: U.S. Pat. No. 6,764,884 by Fried et al., entitled “Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device”
• Publication/Filing Date: Filed Apr. 3, 2003 (Publication date: Jul. 20, 2004)
• Brief Description: This patent describes a method for forming a gate in a FinFET device and thinning a fin in the channel region of the FinFET device.
• Potential Anticipation (35 U.S.C. § 102): This patent focuses on the method of fabricating a FinFET, specifically addressing gate formation and fin thinning. While it clearly relates to FinFET devices, a core element of US6888181, it is directed to manufacturing processes. It might anticipate aspects of forming a gate strip wrapping a portion of a composite fin structure (Claim 1, Claim 6) if its methods are generic enough to apply to the fin structure in US6888181. However, it does not appear to anticipate the composition of the fin, specifically the strained silicon layer on a silicon germanium core, which is central to US6888181's claims.

6. US Pat. No. 6,838,322

• Full Citation: U.S. Pat. No. 6,838,322 by Haukka et al., entitled “Method for forming a double-gated semiconductor device”
• Publication/Filing Date: Filed May 1, 2003 (Publication date: Jan. 4, 2005)
• Brief Description: This patent describes a method for forming a double-gated semiconductor device.
• Potential Anticipation (35 U.S.C. § 102): Similar to US6764884, this patent focuses on the method of forming a double-gated semiconductor device. While a double-gated device is a precursor to a triple-gated device and shares common principles, this patent describes a method, not necessarily the specific device structure of US6888181. It would likely anticipate general methods for creating multi-gated structures but would not, based on the brief description, disclose or suggest the composite strained-silicon fin structure and its unique materials (Claim 1, Claim 6) of US6888181.

In summary, the prior art most closely anticipates the architectural concepts of multi-gate and fin-based transistors. However, the unique contribution of US6888181 lies in the specific composite fin structure with a silicon germanium core and a strained silicon epitaxy layer for enhanced carrier mobility, which is not explicitly disclosed in these prior art citations. US Pat. No. 5,338,959 and US Pat. No. 6,413,802 touch on 3D multi-channel and FinFET structures, respectively, but lack the specific material composition for strain engineering. US Pat. No. 6,727,546's title explicitly mentions a "triple gate" SOI device, making it highly relevant to the architectural concept, but again, the unique strained silicon channel feature of US6888181 would be the distinguishing factor.

Obviousness Analysis of US Patent 6888181 Under 35 U.S.C. § 103

A patent claim is unpatentable if "the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains." 35 U.S.C. § 103. The Supreme Court's decision in KSR International Co. v. Teleflex Inc. emphasized that obviousness can arise from a combination of prior art elements where a person having ordinary skill in the art (POSITA) would have been motivated to combine them to achieve a predictable result. This motivation can stem from various sources, including the nature of the problem, market pressure, design incentives, or the background knowledge and common sense of a POSITA.

US Patent 6888181 ("the '181 patent") addresses the problem of improving the electrical performance, specifically carrier mobility and drive current, in Triple Gate (Tri-gate) devices and FinFETs. The claimed solution involves a composite fin structure comprising a silicon germanium (SiGe) core and a strained silicon epitaxy layer grown from its surface, integrated into a Tri-gate device.

Combination of Prior Art: Hu et al. (US6413802B1) with Known Strained Silicon Technology and its Implementation using SiGe

A person of ordinary skill in the art (POSITA) in March 2004, motivated to enhance the electrical performance (carrier mobility and drive current) of FinFET devices, would have found the claimed invention obvious by combining the teachings of Hu et al. (US6413802B1) with the widely known and documented advantages of strained silicon technology, including its common implementation using SiGe.

1. Primary Prior Art: Hu et al. (US6413802B1) — FinFET Structures

Hu et al. (US6413802B1) discloses a FinFET device fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX), with the device extending from the insulating layer as a fin. [cite: The Regents Of The University Of California. Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. US6413802B1, issued July 2, 2002, column 2, lines 34-39] This reference teaches the fundamental three-dimensional "fin structure" and the concept of multiple gates ("double gates are provided over the sides of the channel") to enhance drive current and suppress short channel effects. [cite: The Regents Of The University Of California. Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. US6413802B1, issued July 2, 2002, column 2, lines 40-44] The '181 patent itself acknowledges that "FinFET is built on a silicon-on-insulator (SOI) substrate. The silicon layer of the SOI substrate is etched into 'fin' like shaped body of the transistor. The gate is wrapped around and over the fin." [cite: United Microelectronics Corp. Triple gate device having strained-silicon channel. US6888181B1, issued May 3, 2005, column 1, lines 60-63] This demonstrates that FinFETs, as a type of 3D transistor with wrapped gates, were a recognized architectural choice in the prior art.

2. Known Problem and Solution: Enhancing Carrier Mobility with Strained Silicon

The '181 patent explicitly states that "the electrical performance such as carrier mobility or device driving current of the above-described SOI-based FinFET and Tri-gate devices can be further improved." [cite: United Microelectronics Corp. Triple gate device having strained-silicon channel. US6888181B1, issued May 3, 2005, column 2, lines 6-9] This highlights a clear and recognized need in the art for improving the performance of existing FinFET devices.

By 2004, the advantages of strained silicon for significantly improving carrier mobility and drive current in MOSFETs were widely recognized and extensively pursued within the semiconductor industry. Major players like Intel, IBM, and AMD were actively developing and integrating strained silicon technology into their microprocessors, including in 90nm technology nodes. Research and industry developments had thoroughly demonstrated that inducing tensile strain in the silicon lattice could substantially enhance both electron and hole mobility, leading to improved transistor performance.

A well-established method for creating the necessary tensile strain in a silicon channel was the epitaxial growth of a thin silicon layer on a relaxed silicon-germanium (SiGe) layer. The intrinsic lattice mismatch between Si and SiGe effectively induces the desired strain in the overlying silicon layer. This technique was a common approach for achieving "global strain" or "biaxial strain" at the wafer level.

3. Motivation to Combine

A POSITA, motivated to address the known problem of improving the electrical performance (specifically carrier mobility and drive current) of a FinFET device, as taught by Hu et al., would have naturally considered known performance-enhancing techniques. Strained silicon was a "Technology Booster" for CMOS developments and was a well-recognized solution for this precise problem. Significantly, prior art literature explicitly "advocated integration of strained-silicon technology in existing FinFETs, which is highly effective in enhancing ON currents through the strain effect."

Therefore, it would have been obvious for a POSITA to combine the FinFET structure described by Hu et al. with the well-understood strained silicon technology, implemented by growing a strained silicon epitaxy layer on a SiGe core. The clear motivation for this combination would be to leverage the superior carrier mobility provided by strained silicon to enhance the drive current of a FinFET device, thereby directly addressing the recognized need to improve FinFET performance. This represents a classic instance of combining known elements (FinFETs and strained silicon on SiGe) to achieve a predictable improvement in a known device.

Furthermore, extending a "double-gate" FinFET (as taught by Hu et al.) to a "Triple Gate" or "Tri-gate" device (where the gate additionally covers the top surface of the fin) would have been an obvious design optimization for a POSITA aiming to maximize gate control and further enhance drive current. The '181 patent itself references "Tri-gate" as a known term and concept in its background section, indicating that multi-sided gating beyond a double-gate structure was understood in the art. [cite: United Microelectronics Corp. Triple gate device having strained-silicon channel. US6888181B1, issued May 3, 2005, column 1, line 16, column 2, line 6] Moreover, Kim et al. (US5338959A) teaches three-dimensional multi-channel structures where channels are "surrounded by gates," further suggesting the concept of multi-sided gate control. [cite: [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) Thin film transistor with three dimensional multichannel structure. US5338959A, issued August 16, 1994, column 1, lines 63-65]

Obviousness of Independent Claims 1 and 6

Independent Claim 1:

• "A three dimensional Triple Gate (Tri-gate) device comprising": This element is taught by Hu et al. (FinFET, a 3D double-gate device), and the general knowledge of Tri-gate devices as an obvious extension for enhanced gate control, as implied by the '181 patent's background and Kim et al.'s "surrounded by gates" concept.
• "a composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer grown from surface of said silicon germanium core": This specific composite channel structure is made obvious by combining the silicon fin of Hu et al. with the known technique of using a SiGe layer to induce strain in an overlying silicon layer, motivated by the desire to enhance carrier mobility and drive current, a well-known benefit of strained silicon.
• "a gate strip wrapping a portion of said composite fin structure": This is taught by Hu et al. (double gates over sides) and generally known FinFET principles of wrapped gates.
• "wherein portions of said composite fin structure not covered by said gate strip constitute source/drain regions of said Tri-gate device": This is a standard functional definition for transistors and would be obvious to a POSITA.
• "a gate insulating layer interposed between said composite fin structure and said gate strip": This is a fundamental and well-known component in all field-effect transistors.

Independent Claim 6:
This claim broadly defines a "composite fin structure consisting of a semiconductor core and a strained epitaxy layer grown from surface of said semiconductor core, said semiconductor core having a first lattice constant that miss-matches a second lattice constant of said strained epitaxy layer." This is a generalization of the specific SiGe/strained silicon structure of Claim 1. The same combination and reasoning for obviousness apply, as SiGe and strained silicon are a prominent and well-known example of a semiconductor core and a lattice-mismatched strained epitaxy layer used to achieve performance enhancement through strain.

Therefore, the subject matter of independent claims 1 and 6 of US6888181 would have been obvious to a person having ordinary skill in the art at the time of the invention.

For US Patent 6888181, a detailed analysis of its patent term adjustments (PTA), patent term extensions (PTE), continuation or divisional applications, related family members, and projected expiration date is provided below. It's important to note that specific PTA and PTE figures typically require direct access to the USPTO's Patent Center or Public Search systems.

1. Patent Term Adjustment (PTA)
Patent Term Adjustment (PTA) adds time to the 20-year lifespan of a U.S. utility or plant patent to compensate for certain administrative delays caused by the USPTO during the patent prosecution process. These delays include the USPTO failing to: issue an office action within 14 months of filing; respond to an applicant's reply within four months; act on an application within four months after certain board or court decisions; or issue a patent within four months after payment of the issue fee. Additionally, PTA is granted if an application is pending for more than three years, excluding applicant-caused delays.

Without direct access to the official USPTO Patent Center file wrapper for US6888181, the precise PTA granted for this patent cannot be determined. However, the "anticipated expiration" date previously noted (March 18, 2024) is exactly 20 years from the filing date (March 18, 2004), suggesting that any PTA granted was either zero, or offset by applicant delays, or not significant enough to alter the widely reported expiration date based on the standard 20-year term from filing.

2. Patent Term Extension (PTE)
Patent Term Extension (PTE) is available under the Hatch-Waxman Act (35 U.S.C. § 156) for patents claiming products that require regulatory approval prior to being sold, such as human and veterinary pharmaceuticals, food additives, color additives, and medical devices. The purpose of PTE is to restore a portion of the patent term lost during the regulatory review period.

Given that US Patent 6888181 relates to a "Triple gate device having strained-silicon channel" and is in the field of semiconductor devices, it is highly unlikely to have been eligible for a Patent Term Extension under 35 U.S.C. § 156, as it does not appear to claim a product subject to premarket government approval by a regulatory agency like the FDA. Therefore, it is expected that no PTE was granted for this patent.

3. Continuation Applications, Divisional Applications, and Related Family Members
The Google Patents record for US6888181 lists its application number as US10/708,694. The "Priority Applications" and "Applications Claiming Priority" sections both list only US10/708,694, indicating that US6888181 is the primary patent from this application, and there are no directly identified parent applications from which it claims priority under 35 U.S.C. §§ 120, 121, or 365(c) that would result in a different 20-year term calculation.

The "Family Applications" section also only lists US10/708,694 (US6888181B1). This suggests that as of the information available, there are no immediate continuation, continuation-in-part, or divisional applications directly listed within the same patent family on Google Patents. Without direct access to USPTO's Patent Center or Public Search tools, it's not possible to definitively confirm the absence of all potential continuation or divisional applications, but based on the provided family information, none are explicitly identified.

4. Projected Expiration Date
For utility patents filed on or after June 8, 1995, the standard patent term is 20 years from the earliest U.S. filing date, or from the earliest filing date of an application for which a benefit is claimed under 35 U.S.C. §§ 120, 121, or 365(c).

US Patent 6888181 has a filing date of March 18, 2004. Therefore, its statutory 20-year term would typically extend to March 18, 2024. This aligns with the "anticipated expiration" date of March 18, 2024, as noted in the patent summary. As previously stated, the patent's legal status is "Expired - Lifetime" as of this date, confirming its expiration.