US 11538763

US Patent 11,538,763: Chip Package

Title: Chip package

Assignee: Myw Semitech LLC

Inventors: Ping-Jung Yang

Filing Date: July 11, 2021 (for application US17/372,459, which resulted in this patent)

Issue Date: December 27, 2022

Abstract:
A display device is described, featuring a display panel substrate and an overlying glass substrate. The display panel substrate includes multiple contact pads and a display area defined by edges and boundaries. The key feature is that the distances between the display area's edges and the panel's boundaries are less than 100 micrometers. The glass substrate incorporates multiple metal conductors passing through it, with metal bumps positioned between the glass and display panel substrates. These metal conductors connect to the display panel's contact pads via the metal bumps.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Display Device): This claim describes a display device comprising two main parts: a display panel substrate and a glass substrate.

  • The display panel substrate has contact pads and a display area. The display area is defined by four edges. The entire display panel also has four boundaries. A key feature is that the shortest distances between each of the display area's edges and the corresponding parallel boundary of the display panel are all very small—less than 100 micrometers. This implies a very narrow border or bezel around the display area.
  • The glass substrate is positioned over the display panel substrate. It contains multiple metal conductors that pass completely through the glass. Between the glass substrate and the display panel substrate are multiple metal bumps. These metal conductors are electrically connected to the contact pads on the display panel substrate via these metal bumps.

• Independent Claim 10 (Chip Package): This claim details a chip package built around a "first substrate" which is essentially a glass interposer.

  • The first substrate consists of a glass layer with multiple metal plugs running from its top surface to its bottom surface. Both the top and bottom surfaces of these metal plugs are level (coplanar) with the respective top and bottom surfaces of the glass layer.
  • A first dielectric layer is on the top surface of this first substrate and covers the top of the metal plugs, but it has openings that expose these metal plugs.
  • A first metal layer is formed over the first dielectric layer and fills these openings, contacting the exposed metal plugs.
  • A second metal layer is then formed on top of the first metal layer.
  • A second dielectric layer covers the first dielectric layer and the second metal layer, and it has openings that expose parts of the second metal layer.
  • A third metal layer is formed on the second dielectric layer and fills its openings, contacting the exposed second metal layer.
  • A fourth metal layer is formed on top of the third metal layer.
  • Finally, at least one chip is placed on this fourth metal layer.

• Independent Claim 11 (Chip Package with Specific Chip Connection): This claim is very similar to Claim 10, describing the same layered structure of the chip package, but adds more specific details about how the chip is connected.

  • It includes all the features of Claim 10 regarding the first substrate, dielectric layers, and metal layers (first, second, third, and fourth).
  • The key difference is that the at least one chip formed on the fourth metal layer is specified to include multiple metal pads and multiple metal bumps formed on these pads. These metal bumps are then specifically connected to the fourth metal layer. This describes a flip-chip type of connection.

Litigation Status:
As of the current date, US patent 11,538,763 is involved in litigation. A PTAB (Patent Trial and Appeal Board) case, IPR2026-00066, has been filed and is currently pending. Additionally, a US case has been filed in the Delaware District Court.

Known litigation involving US patent 11538763 includes:

1. Inter Partes Review (IPR) Case

   • Case Number: IPR2026-00066
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Plaintiff(s)/Petitioner(s): Unified Patents PTAB Data
   • Defendant(s)/Patent Owner(s): Not specified in the provided information.
   • Filing Date: Not explicitly provided in the patent text or search results.
   • Outcome or Current Status: Pending

2. US District Court Case

   • Case Number: 1:25-cv-00504
   • Jurisdiction: Delaware District Court
   • Plaintiff(s): Not specified in the provided information.
   • Defendant(s): Not specified in the provided information.
   • Filing Date: Not explicitly provided in the patent text or search results.
   • Outcome or Current Status: Active litigation.

Additionally, the patent record indicates "First worldwide family litigation filed" with a link to Darts-ip. However, specific details such as jurisdiction, case number, filing date, plaintiffs, defendants, or status for this "worldwide family litigation" are not available in the provided patent text or search results beyond the general mention.

Proceedings overview

One AIA trial proceeding has been filed against US patent 11538763. This Inter Partes Review (IPR) is currently in the "Trial Instituted" phase, meaning the Patent Trial and Appeal Board (PTAB) has found a reasonable likelihood that at least one challenged claim is unpatentable. For a defendant facing assertion of this patent, this indicates that the patent's validity is currently being challenged and no claims have been definitively upheld or invalidated by the PTAB yet.

IPR2026-00066 — Taiwan Semiconductor Manufacturing Company Ltd. et al. v. Myw Semitech LLC

• Type: Inter Partes Review
• Filed: 2025-11-21
• Status: Trial Instituted (The PTAB has determined that the petitioner has a reasonable likelihood of prevailing with respect to at least one challenged claim and has authorized the trial to proceed).
• Judge panel: Undisclosed publicly at this time based on available information.
• Petition grounds: The specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) are not publicly detailed in the provided information or readily available from general searches at this "Trial Instituted" stage without access to the full petition and institution decision documents.
• Institution decision: Instituted. The exact date of institution and the panel's reasoning are not explicitly provided in the initial data, but the status "Trial Instituted" confirms this outcome. The Unified Patents PTAB data indicates the case was filed on 2025-11-21 and last modified on 2026-05-22 with a status of "Trial Instituted". This implies the institution decision was issued around the modification date.
• Final Written Decision (if issued): Not yet issued. The proceeding is in the trial phase.
• Settlement / termination: No settlement or termination has been publicly reported.
• Appeal: Not applicable, as no Final Written Decision has been issued.
• Defensive value: As the IPR has been instituted, it indicates that the PTAB found the challenge to at least one claim sufficiently strong to proceed to trial. This means the validity of US11538763 is actively under scrutiny. Any infringement theory based on claims under challenge in this IPR faces significant risk if those claims are ultimately found unpatentable.

Strategic summary

Currently, all claims of US11538763 remain untested by a Final Written Decision, as the single identified IPR (IPR2026-00066) is in the "Trial Instituted" phase. This means no claims have been canceled or sustained by the PTAB yet.

Regarding the estoppel landscape, since IPR2026-00066 has been instituted, Taiwan Semiconductor Manufacturing Company Ltd. et al. (and their privies) will be estopped under § 315(e)(2) from asserting in any other proceeding before the USPTO, the International Trade Commission, or any district court of the United States, that a claim is invalid on any ground that the petitioner raised or reasonably could have raised during the IPR. For a defendant not privy to this IPR, most prior-art grounds would theoretically still be available for a new challenge, though the institution of this IPR suggests that strong prior art has already been identified and is being litigated.

No clear pattern signals are available as only one IPR proceeding is currently on file for this patent. The involvement of Unified Patents as a source for litigation data may suggest a defensive aggregation strategy by the petitioner, but without more context or additional filings, this is speculative.

Recommended next steps

If you are a defendant facing assertion of US11538763, closely monitor IPR2026-00066. The patent's validity is currently being challenged, which could significantly impact any litigation. The PTAB has a statutory deadline to issue a Final Written Decision within one year of institution. Given the filing date of 2025-11-21 and a "last modified" date of 2026-05-22 for "Trial Instituted", the Final Written Decision would likely be due around May 2027. Accessing the publicly available petition and institution decision for IPR2026-00066 on the USPTO PTAB E2E system would provide critical details on the specific claims challenged and the prior art relied upon.The search results provide some general context about recent changes to PTAB proceedings and IPR institution rates under Director John Squires, but they do not provide specific details for IPR2026-00066 such as the institution decision date, claims challenged, or judge panel. The information from the initial prompt states "last modified 2026-05-22 — status: Trial Instituted", which implies the institution decision was made around this time. Without direct access to the PTAB docket for this specific case, I cannot provide these granular details.

Therefore, I need to state clearly what information is not available.

Revised plan:

1. Proceedings overview: Keep as is, noting the "Trial Instituted" status.
2. For IPR2026-00066:
   • Type, Filed, Status, Petitioner, Patent Owner: Use the provided data.
   • Judge panel: State that it's undisclosed publicly at this time based on available information.
   • Petition grounds: State that specific claims challenged, prior art, and statutory bases are not publicly detailed without access to the full petition and institution decision documents.
   • Institution decision: State that it was instituted, and while the exact date isn't known, it was around the "last modified" date (2026-05-22). Explain what "Trial Instituted" means.
   • Final Written Decision (FWD), Settlement / termination, Appeal: State not applicable yet.
   • Defensive value: Reiterate its implications.
3. Strategic summary:
   • Claims: Reiterate that all claims are currently untested by a FWD.
   • Estoppel: Explain estoppel for the petitioner once a FWD is issued.
   • Pattern signals: Note that with only one IPR, patterns are limited. Mention the source of litigation data (Unified Patents) as a potential signal.
4. Recommended next steps:
   • Emphasize monitoring the active proceeding.
   • Note the statutory 1-year deadline for FWD.
   • Recommend accessing the petition/institution decision for details.

I will use the "last modified" date (2026-05-22) from the provided structured data as an approximate date for the institution decision, as the status changed to "Trial Instituted" by then.

Final check of constraints:

• Don't fabricate: I will clearly state when information is not available.
• Quote claim numbers exactly: N/A as claims are not yet detailed.
• Date format YYYY-MM-DD: Will use this.
• Link to USPTO PTAB E2E or CourtListener: I will mention these as sources for the user to look up, but since I don't have direct links to a specific FWD or CAFC opinion for this IPR, I won't provide a direct link for it.
• Build on previously generated sections: Yes.

One more quick search to see if any specific institution date or claims for IPR2026-00066 are available through a more direct PTAB search query, though the general searches didn't yield them.

Search Query:
6. "IPR2026-00066 USPTO PTAB"## Proceedings overview

One AIA trial proceeding has been filed against US patent 11538763. This Inter Partes Review (IPR) is currently in the "Trial Instituted" phase, meaning the Patent Trial and Appeal Board (PTAB) has found a reasonable likelihood that at least one challenged claim is unpatentable. For a defendant facing assertion of this patent, this indicates that the patent's validity is currently being challenged and no claims have been definitively upheld or invalidated by the PTAB yet.

IPR2026-00066 — Taiwan Semiconductor Manufacturing Company Ltd. et al. v. Myw Semitech LLC

• Type: Inter Partes Review
• Filed: 2025-11-21
• Status: Trial Instituted (The PTAB has determined that the petitioner has a reasonable likelihood of prevailing with respect to at least one challenged claim and has authorized the trial to proceed. The case was last modified on 2026-05-22, indicating the institution decision occurred around this time.)
• Judge panel: The specific judge panel for this IPR is not publicly disclosed at this time based on available information.
• Petition grounds: The specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) are not publicly detailed in the provided information or readily available from general searches at this "Trial Instituted" stage without access to the full petition and institution decision documents.
• Institution decision: Instituted. While the exact date of institution is not explicitly stated in the provided data, the status update to "Trial Instituted" as of 2026-05-22 confirms this outcome. The institution means the PTAB found the petition to demonstrate a reasonable likelihood that at least one challenged claim of US11538763 is unpatentable.
• Final Written Decision (if issued): Not yet issued. The proceeding is currently in the trial phase.
• Settlement / termination: No settlement or termination has been publicly reported for this proceeding.
• Appeal: Not applicable, as no Final Written Decision has been issued.
• Defensive value: The institution of this IPR signifies that the PTAB found the challenge to at least one claim of US11538763 sufficiently strong to warrant a full trial. This means the validity of the patent is actively under scrutiny. Any infringement theory based on claims currently challenged in IPR2026-00066 faces significant risk if those claims are ultimately found unpatentable by the PTAB.

Strategic summary

All claims of US11538763 are currently untested by a Final Written Decision, as the sole identified IPR (IPR2026-00066) is in the "Trial Instituted" phase. Therefore, no claims have been definitively canceled or sustained by the PTAB at this juncture.

Regarding the estoppel landscape, once a Final Written Decision is issued in IPR2026-00066, the petitioner, Taiwan Semiconductor Manufacturing Company Ltd. et al., and any parties in privy with them, will be estopped under 35 U.S.C. § 315(e)(2) from asserting in any other proceeding before the USPTO, the International Trade Commission, or any district court of the United States, that a claim is invalid on any ground that the petitioner raised or reasonably could have raised during the IPR. For a defendant not privy to this IPR, most prior-art grounds would theoretically still be available for a new challenge, though the institution of this IPR suggests that strong prior art has already been identified and is being litigated.

With only one IPR proceeding currently on file for this patent, there are limited pattern signals to discern. The petitioner's identity and the public record from Unified Patents indicate that a defensive aggregator or a large operating company is involved in challenging the patent.

Recommended next steps

If you are a defendant facing assertion of US11538763, it is crucial to closely monitor IPR2026-00066. The patent's validity is actively being challenged, which could significantly impact any ongoing or future litigation. The PTAB has a statutory deadline to issue a Final Written Decision within one year of institution. Given that the IPR was last modified with a "Trial Instituted" status on 2026-05-22, the Final Written Decision is expected around May 2027.

It is highly recommended to obtain and review the publicly available petition and institution decision documents for IPR2026-00066 from the USPTO PTAB E2E system. These documents will provide precise details on the specific claims challenged and the prior art relied upon, which are essential for evaluating the strength of the patent and informing your defensive strategy.

Inventors

• Ping-Jung Yang (Employer at time of filing: Individual/Independent Inventor. The patent lists "Original Assignee: Individual" and "Application filed by Individual" on 2021-07-11.)

Original assignee

The original assignee named on the application was an "Individual" (Ping-Jung Yang). This individual inventor does not ship products embodying the claims. The first assignment transferred the patent to MYW Semitech LLC. Based on available information, MYW Semitech LLC is a non-practicing entity (NPE) that engages in patent litigation and does not ship products embodying the claims. Its primary line of business appears to be patent assertion. MYW Semitech LLC is currently an active entity and is involved in litigation.

Assignment timeline

• 2022-12-27 (executed) / recorded 2022-12-27 — Reel 071665/157

  • Conveyance: Assignment of Assignors Interest
  • Assignor: YANG, PING-JUNG
  • Assignee: MYW SEMITECH LLC
  • Correspondent: ROBERT J. YARBROUGH, ESQ., YARBROUGH LAW LLC, 1400 BROADWAY, NEW YORK, NEW YORK 10018, UNITED STATES. This correspondent recurs in this chain.
  • Context: Transfer from individual inventor to an asserting entity upon patent grant.

• 2023-03-20 (executed) / recorded 2023-03-20 — Reel 071665/154

  • Conveyance: Patent Security Agreement
  • Assignor: MYW SEMITECH LLC
  • Assignee: PICCADILLY PATENT FUNDING LLC, AS SECURITY HOLDER
  • Correspondent: ROBERT J. YARBROUGH, ESQ., YARBROUGH LAW LLC, 1400 BROADWAY, NEW YORK, NEW YORK 10018, UNITED STATES. This correspondent recurs in this chain.
  • Context: Securitization of the patent by the assignee.

Timeline diagram

timeline
    title Ownership of US 11538763
    2012 : Priority date
    2021 : Application filed by Individual
    2022 : Patent granted
         : Assigned to MYW Semitech LLC
    2023 : Security agreement with Piccadilly Patent Funding LLC
    2025 : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was assigned from an individual inventor to MYW SEMITECH LLC on the day the patent was granted (2022-12-27, Reel 071665/157). MYW Semitech LLC is identified as a patent owner involved in litigation and there is no evidence that it produces products embodying the claims.

2. Known asserter in the chain — present. MYW SEMITECH LLC is listed by Unified Patents as an entity involved in patent litigation.

3. Repeat correspondent across the chain — present. ROBERT J. YARBROUGH, ESQ. of YARBROUGH LAW LLC is listed as the correspondent for both the assignment from Ping-Jung Yang to MYW Semitech LLC (Reel 071665/157, recorded 2022-12-27) and the Patent Security Agreement between MYW Semitech LLC and Piccadilly Patent Funding LLC (Reel 071665/154, recorded 2023-03-20).

4. Cascading transfers — present. The initial assignment to MYW SEMITECH LLC occurred on 2022-12-27 (Reel 071665/157), followed by a Patent Security Agreement with Piccadilly Patent Funding LLC on 2023-03-20 (Reel 071665/154). This rapid sequence of financial transactions within approximately three months of acquiring the patent by an identified NPE indicates an assertion strategy.

5. Pre-litigation transfer — not present. The earliest recorded litigation for this patent family (Delaware District Court case 1:25-cv-00504) was filed on April 24, 2025. The assignments occurred in December 2022 and March 2023, which is more than six months prior to the first reported litigation.

6. Bankruptcy fire-sale — not present. There is no indication that the original inventor or MYW Semitech LLC filed for bankruptcy proceedings that led to the patent transfer.

7. Privateering — not present. The initial transfer was from an individual inventor, not an operating company.

8. Defensive aggregator (anti-NPE) — not present. The current assignee, MYW Semitech LLC, and the security holder, Piccadilly Patent Funding LLC, are not defensive aggregators.

Verdict

NPE — high confidence. This verdict is supported by multiple strong signals: the transfer from an individual inventor directly to MYW Semitech LLC on the day of patent grant (Reel 071665/157, 2022-12-27), MYW Semitech LLC's status as a known patent asserter, the recurrence of the same correspondent attorney across the assignment chain (ROBERT J. YARBROUGH, ESQ., YARBROUGH LAW LLC), and the cascading financial activity (security agreement) shortly after the initial assignment to the NPE.

For verification, see USPTO Patent Assignment Search: https://assignmentcenter.uspto.gov/patent/[11538763](/patent/11538763)

The full patent text for US11538763B2, "Chip package," primarily details its own patent family lineage in the "Description" section, rather than listing external prior art references in a dedicated "References Cited" section. Therefore, the "patent citations" identified within the provided authoritative text are the patent's own direct ancestors.

The earliest priority date for US11538763B2 is September 26, 2012, based on U.S. provisional patent application No. 61/705,649.

It is important to note that an applicant's own earlier-filed, co-pending, and published application or granted patent is generally not considered "prior art" under 35 U.S.C. § 102 against claims in a later-filed continuation application if those claims are fully supported by the disclosure of the earlier application and are entitled to the earlier application's priority date. Therefore, the patents listed below, being direct ancestors in the same patent family, would typically not anticipate the claims of US11538763B2 for subject matter sharing the common priority date. However, if US11538763B2 were to introduce new subject matter not disclosed in the earlier patents, and those earlier patents were published before the effective filing date of the new matter, then the earlier patents could potentially anticipate only those specific new claims.

Given the instructions, the following are the patent citations found within the provided text of US11538763B2:

Most Relevant Patent Citations for US11538763B2

1. U.S. Pat. No. 10,622,310

• Full Citation: U.S. Pat. No. 10,622,310.
• Publication/Filing Date: Granted from application Ser. No. 15/261,956, which was filed on September 11, 2016. The grant date for US10622310 was April 7, 2020.
• Brief Description: US10622310 is a direct ancestor in the patent family of US11538763B2. It generally describes a chip package or display device, likely involving a glass substrate with through-glass vias (metal conductors) and methods for manufacturing such structures. As a parent patent, its disclosure is expected to encompass the core subject matter of US11538763B2.
• Potential Anticipation under 35 U.S.C. § 102: Due to its status as a parent patent to US11538763B2, and both sharing the earliest common priority date of September 26, 2012, US10622310 would typically not anticipate any claims of US11538763B2 that are fully supported by the earlier disclosures. The claims of US11538763B2 are generally entitled to the same priority date as the subject matter disclosed in US10622310. Without a detailed, claim-by-claim comparison of the disclosures for any potentially new matter introduced in US11538763B2 that might not be entitled to the earliest priority date, it is highly probable that US10622310 does not anticipate the claims of US11538763B2.

2. U.S. Pat. No. 9,615,453

• Full Citation: U.S. Pat. No. 9,615,453.
• Publication/Filing Date: Granted from application Ser. No. 14/036,256, which was filed on September 25, 2013. The grant date for US9615453 was April 4, 2017.
• Brief Description: US9615453 is also an ancestor in the patent family of US11538763B2, being a continuation-in-part (CIP) of application Ser. No. 14/036,256, which ultimately claims the earliest priority date of September 26, 2012, shared with US11538763B2. This patent likely describes a method and structure for manufacturing a glass substrate and integrating one or more chips onto it, consistent with the broader technical field of US11538763B2.
• Potential Anticipation under 35 U.S.C. § 102: As a direct ancestor sharing the earliest common priority date (September 26, 2012) with US11538763B2, US9615453 would typically not anticipate any claims of US11538763B2 that are fully supported by its own disclosure and entitled to this common priority date. Similar to US10622310, a detailed analysis would be required to determine if any specific claims of US11538763B2 are directed to new subject matter not present in US9615453's disclosure and not entitled to the earlier priority date. Absent such an analysis, it is most probable that US9615453 does not anticipate the claims of US11538763B2.

Obviousness Analysis of US Patent 11,538,763 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the independent claims of US Patent 11,538,763 (hereinafter "the '763 patent") obvious to a person having ordinary skill in the art (PHOSITA) as of its priority date of September 26, 2012. The analysis relies on the prior art explicitly referenced and discussed within the '763 patent itself, particularly US Pat. No. 9,615,453 (hereinafter "'453 patent") and general knowledge in the semiconductor packaging and display industries as described in the background section of the '763 patent.

Due to the limitations of the provided tools, the full text of US Pat. No. 9,615,453 was not directly retrieved. However, based on the '763 patent stating that it is a continuation-in-part of the application that led to the '453 patent, and the '763 patent's detailed discussion of "Through Glass Vias (TGV's)" in the context of glass interposers, it is reasonably assumed that the '453 patent teaches the fundamental concept of a glass substrate incorporating through-glass metal conductors (metal plugs) for chip packaging or interposer applications. This assumption aligns with the background section of the '763 patent, which describes the use of "glass as an interposer to bridge between one or more IC chips and a printed circuit board" and notes the "difficulty in forming Through Glass Vias (TGV's)," indicating that this technology was a focus of the patent family.

Analysis of Independent Claim 1 (Display Device)

Claim 1 of the '763 patent describes a display device comprising:

• A display panel substrate with multiple contact pads and a display area defined by edges and boundaries, where the least distances between the display area's edges and the panel's boundaries are smaller than 100 micrometers.
• A glass substrate over the display panel substrate.
• Multiple metal conductors passing through the glass substrate.
• Multiple metal bumps between the glass substrate and the display panel substrate, connecting the metal conductors to the contact pads.

Combination of Prior Art:

1. US Pat. No. 9,615,453 (assumed): Teaches a glass interposer with through-glass metal conductors (or "metal plugs") used in chip packaging.
2. General knowledge in the display industry: A PHOSITA in the display field would be well aware of the continuous market demand and technical drive to reduce the "bezel" or border size around display areas for aesthetic and functional reasons, leading to a desire for "first, second, third and fourth least distances are smaller than 100 micrometers." The background of the '763 patent itself acknowledges the trend for microelectronic devices to be "minimized and thinned."

Motivation for Combination:
A PHOSITA would be motivated to combine the teachings of the '453 patent (glass interposer with TGVs) with the known desire for narrow-bezel displays. The glass substrate, being transparent, is a natural candidate for an overlying layer in a display device. Integrating the metal conductors (TGVs) within this glass substrate, as taught by the '453 patent, provides a compact and efficient means of routing electrical signals from the display panel's contact pads to external connections or other chips. This high-density routing capability enabled by TGVs would directly facilitate the reduction of the border area around the display, allowing for the "least distances" to be "smaller than 100 micrometers." The use of metal bumps for electrical connection between the glass substrate and the display panel substrate is a known and established technique in microelectronics, such as Chip-on-Glass (COG) bonding or flip-chip technology, which is explicitly mentioned as known in the background of the '763 patent. Therefore, utilizing a glass substrate with integrated through-glass conductors to enable a narrow-bezel display device would be an obvious design choice for a PHOSITA.

Analysis of Independent Claim 10 (Chip Package)

Claim 10 of the '763 patent describes a chip package comprising:

• A first substrate having a glass layer with multiple metal plugs extending through it, with their top and bottom surfaces coplanar with the respective glass layer surfaces.
• A first dielectric layer on the top surface of the first substrate, with openings exposing the metal plugs.
• A first metal layer on the first dielectric layer and in the openings, contacting the metal plugs.
• A second metal layer on the first metal layer.
• A second dielectric layer covering the first dielectric layer and the second metal layer, with openings exposing the second metal layer.
• A third metal layer on the second dielectric layer and in the openings, contacting the second metal layer.
• A fourth metal layer on the third metal layer.
• At least one chip on the fourth metal layer.

Combination of Prior Art:

1. US Pat. No. 9,615,453 (assumed): Teaches a glass substrate with through-glass metal plugs (TGVs) that are coplanar with the substrate surfaces. This forms the "first substrate" base of Claim 10.
2. Background of the '763 patent and general knowledge in semiconductor packaging: The '763 patent's background discusses the increasing importance of metal connections, parasitic capacitance and resistance, and attempts to use "low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines." This highlights the known challenges and solutions related to interconnect performance. Multi-layer redistribution layers (RDLs), consisting of alternating dielectric and metal layers, are a well-established technique in advanced semiconductor packaging to provide signal routing, power delivery, and fan-out capabilities between chips and packages. The materials described for the dielectric layers (e.g., silicon oxide, polyimide) and metal layers (e.g., titanium, copper, nickel, gold) in the '763 patent are standard RDL materials and processes (e.g., PVD, PECVD, sputtering, electroplating) are well-known fabrication methods.

Motivation for Combination:
A PHOSITA would be motivated to combine the glass interposer with TGVs (from the '453 patent) with standard RDL technology. The '763 patent's background explicitly recognizes the problems of parasitic effects in metal interconnections and the need for low resistance metals and low dielectric materials. Building multi-layer RDLs, as described in Claim 10 (first dielectric/metal, second dielectric/metal, etc.), on the glass interposer with TGVs is a direct and obvious solution to address these performance issues and provide the necessary routing complexity for connecting chips. The TGVs in the glass substrate provide vertical interconnects, while the RDLs on the surface provide horizontal routing and fan-out, enabling sophisticated chip packages. Placing a chip on the topmost metal layer (fourth metal layer) is the logical endpoint of such an RDL structure.

Analysis of Independent Claim 11 (Chip Package with Specific Chip Connection)

Claim 11 of the '763 patent describes a chip package comprising:

• All features of Claim 10.
• The at least one chip on the fourth metal layer comprises multiple metal pads and multiple metal bumps formed on the metal pads, wherein the metal bumps are connected to the fourth metal layer.

Combination of Prior Art:

1. All elements of Claim 10 (as rendered obvious above).
2. Background of the '763 patent and general knowledge in semiconductor packaging: The '763 patent's background extensively describes "Flip-chip Packages," stating that "Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads of chip and interconnects the bumps directly to the package media" to achieve "highest density of interconnection to the device and a very low inductance interconnection."

Motivation for Combination:
Given the chip package structure of Claim 10 (a glass interposer with multi-layer RDLs), a PHOSITA would be strongly motivated to connect chips to this structure using flip-chip technology. The '763 patent's background explicitly endorses flip-chip for its high interconnection density and low inductance, which are critical for meeting the "increased demands for high performance" in ICs. Therefore, adapting the well-known flip-chip bonding technique—which involves forming metal pads and metal bumps on the chip and connecting these bumps to the corresponding pads/layers (like the fourth metal layer in Claim 11) on the package medium (the glass interposer with RDLs)—is a straightforward and obvious choice for a PHOSITA seeking to achieve the known benefits of flip-chip packaging within the described structure.

Here's a detailed breakdown for US Patent 11,538,763:

Patent Term Adjustment (PTA)

Specific Patent Term Adjustment (PTA) data for US11538763 is not directly available from the provided patent text or the general search results. The United States Patent and Trademark Office (USPTO) grants PTA to compensate patent holders for certain administrative delays during the patent examination process, such as the USPTO failing to issue a first office action within 14 months of filing, or failing to issue a patent within three years of the application filing date. The total PTA is an addition to the standard 20-year lifespan of a utility or plant patent. Without accessing the patent's file wrapper in the USPTO's Patent Center or Public PAIR system, the exact calculation and final PTA awarded for this specific patent cannot be determined.

Patent Term Extension (PTE)

Based on the nature of US11538763, which is titled "Chip package," it is highly unlikely to be eligible for Patent Term Extension (PTE). PTE is a statutory mechanism primarily intended for patents claiming products (such as human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products) that require premarket government approval from a regulatory agency like the FDA. PTE compensates for the patent term lost during this regulatory review process. As a chip package does not fall into these categories, it would not typically qualify for PTE.

Continuation Applications

US Patent 11,538,763 is part of a series of continuation applications. Its application, Ser. No. 17/372,459, is a continuation of the following:

• Application Ser. No. 16/752,650, filed January 26, 2020.
• Application Ser. No. 15/261,956, filed September 11, 2016 (which issued as U.S. Pat. No. 10,622,310).

Application Ser. No. 15/261,956 is itself a continuation-in-part of application Ser. No. 14/036,256, filed September 25, 2013 (which issued as U.S. Pat. No. 9,615,453).

Divisional Applications

The provided patent text and general search results do not explicitly mention any divisional applications associated with US Patent 11,538,763.

Related Family Members

The patent family for US11538763 includes the following applications and granted patents, tracing back to the earliest priority date:

• U.S. Provisional Patent Application No. 61/705,649: Filed September 26, 2012 (earliest priority date).
• U.S. Provisional Patent Application No. 62/219,249: Filed September 16, 2015.
• U.S. Patent Application Ser. No. 14/036,256: Filed September 25, 2013 (issued as U.S. Pat. No. 9,615,453).
• U.S. Patent No. 9,615,453: Granted April 4, 2017.
• U.S. Patent Application Ser. No. 15/261,956: Filed September 11, 2016 (issued as U.S. Pat. No. 10,622,310).
• U.S. Patent No. 10,622,310: Granted April 7, 2020.
• U.S. Patent Application Ser. No. 16/752,650: Filed January 26, 2020.
• U.S. Patent Application Ser. No. 17/372,459: Filed July 11, 2021 (which issued as US Patent 11,538,763).
• U.S. Patent No. 11,538,763: Granted December 27, 2022.
• US20210335714A1: Published October 28, 2021 (this is the publication of application US17/372,459).
• US17/985,827: Priority claimed November 12, 2022 (issued as US11894306B2).
• US18/524,118: Priority claimed November 30, 2023 (issued as US12062618B2).
• US18/778,983: Priority claimed July 21, 2024 (published as US20240379566A1).
• US19/001,689: Priority claimed December 26, 2024 (published as US20250132260A1).

Projected Expiration Date

The anticipated expiration date for US Patent 11,538,763 is September 25, 2033. This date is based on the 20-year term from the earliest priority date (September 26, 2012), adjusted for any Patent Term Adjustment (PTA) or Patent Term Extension (PTE), if applicable. However, as noted above, specific PTA/PTE figures are not publicly detailed here.