US 11538763

US Patent 11,538,763: Chip Package

Title: Chip package

Assignee: Myw Semitech LLC

Inventors: Ping-Jung Yang

Filing Date: July 11, 2021 (for application US17/372,459, which resulted in this patent)

Issue Date: December 27, 2022

Abstract:
A display device is described, featuring a display panel substrate and an overlying glass substrate. The display panel substrate includes multiple contact pads and a display area defined by edges and boundaries. The key feature is that the distances between the display area's edges and the panel's boundaries are less than 100 micrometers. The glass substrate incorporates multiple metal conductors passing through it, with metal bumps positioned between the glass and display panel substrates. These metal conductors connect to the display panel's contact pads via the metal bumps.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Display Device): This claim describes a display device comprising two main parts: a display panel substrate and a glass substrate.

  • The display panel substrate has contact pads and a display area. The display area is defined by four edges. The entire display panel also has four boundaries. A key feature is that the shortest distances between each of the display area's edges and the corresponding parallel boundary of the display panel are all very small—less than 100 micrometers. This implies a very narrow border or bezel around the display area.
  • The glass substrate is positioned over the display panel substrate. It contains multiple metal conductors that pass completely through the glass. Between the glass substrate and the display panel substrate are multiple metal bumps. These metal conductors are electrically connected to the contact pads on the display panel substrate via these metal bumps.

• Independent Claim 10 (Chip Package): This claim details a chip package built around a "first substrate" which is essentially a glass interposer.

  • The first substrate consists of a glass layer with multiple metal plugs running from its top surface to its bottom surface. Both the top and bottom surfaces of these metal plugs are level (coplanar) with the respective top and bottom surfaces of the glass layer.
  • A first dielectric layer is on the top surface of this first substrate and covers the top of the metal plugs, but it has openings that expose these metal plugs.
  • A first metal layer is formed over the first dielectric layer and fills these openings, contacting the exposed metal plugs.
  • A second metal layer is then formed on top of the first metal layer.
  • A second dielectric layer covers the first dielectric layer and the second metal layer, and it has openings that expose parts of the second metal layer.
  • A third metal layer is formed on the second dielectric layer and fills its openings, contacting the exposed second metal layer.
  • A fourth metal layer is formed on top of the third metal layer.
  • Finally, at least one chip is placed on this fourth metal layer.

• Independent Claim 11 (Chip Package with Specific Chip Connection): This claim is very similar to Claim 10, describing the same layered structure of the chip package, but adds more specific details about how the chip is connected.

  • It includes all the features of Claim 10 regarding the first substrate, dielectric layers, and metal layers (first, second, third, and fourth).
  • The key difference is that the at least one chip formed on the fourth metal layer is specified to include multiple metal pads and multiple metal bumps formed on these pads. These metal bumps are then specifically connected to the fourth metal layer. This describes a flip-chip type of connection.

Litigation Status:
As of the current date, US patent 11,538,763 is involved in litigation. A PTAB (Patent Trial and Appeal Board) case, IPR2026-00066, has been filed and is currently pending. Additionally, a US case has been filed in the Delaware District Court.