US 11032111

The USPTO and CAFC search results did not contradict the information already extracted from the provided patent text about US11032111. The CAFC search for "CAFC dockets 2026 patent 11032111" did not return any specific cases related to patent 11032111 in the Federal Circuit's 2026 schedule. The Google Patents information did mention PTAB cases and US District Court cases for 2025, but not specifically CAFC dockets for 2026. Therefore, I will state that no CAFC 2026 dockets were found for this specific patent.

I have all the necessary information to provide the concise summary.

Concise Summary of US Patent 11032111

Title: Serdes pre-equalizer having adaptable preset coefficient registers

Assignee: Credo Technology Group Ltd

Inventors: Junqing Sun, Haoli Qian

Filing Date: August 27, 2019

Issue Date: June 8, 2021

Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a method for a SerDes (serializer-deserializer) communication system. The method involves a transceiver choosing one of several available registers. Each register holds a set of initial settings (coefficient values) for a pre-equalizer, and each set is designed for a different type of communication channel. During a "training phase," these initial settings are adjusted or "updated." Finally, the transceiver uses these updated pre-equalizer settings to send out a data stream.
• Independent Claim 8: This claim describes a hardware system, specifically a chip-to-module communication link. It includes a connector that links a transceiver on a "port" (like on a network switch) to a transceiver inside a "pluggable module" (like an SFP+ module). The pluggable module's transceiver has one or more transmit filters, which prepare (pre-equalize) the data streams before they are sent to the port transceiver. It also has a controller with multiple registers, each storing different initial coefficient values. The controller uses one of these registers to set the initial coefficient values for the transmit filters.

CAFC 2026 Dockets: No specific cases related to patent 11032111 were found in the CAFC 2026 dockets.Concise Summary of US Patent 11032111

Title: Serdes pre-equalizer having adaptable preset coefficient registers

Assignee: Credo Technology Group Ltd

Inventors: Junqing Sun, Haoli Qian

Filing Date: August 27, 2019

Issue Date: June 8, 2021

Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a method for a SerDes (serializer-deserializer) communication system. The method involves a transceiver choosing one of multiple pre-defined registers. Each of these registers holds a different set of initial coefficient values for a pre-equalizer, with each set corresponding to a different expected communication channel condition. During a "training phase," these initial pre-equalizer coefficient values are adjusted. The transceiver then uses these updated coefficient values to transmit a data stream.
• Independent Claim 8: This claim describes a hardware system, specifically a chip-to-module communication link. It includes a port connector that connects a port transceiver (e.g., on a host device) to a pluggable module transceiver. The pluggable module transceiver contains one or more transmit filters, which are used to pre-equalize the serial data streams being sent to the port transceiver. The module also has a controller equipped with multiple registers, where each register stores a set of initial coefficient values. The controller selects and uses one of these registers to configure the initial coefficient values for its transmit filters.

CAFC 2026 Dockets: No specific cases related to patent 11032111 were found in the CAFC 2026 dockets.

The US patent 11032111 is currently involved in several litigation cases.

Here is a summary of the known litigation:

• PTAB case IPR2025-01220

  • Petitioner: Unified Patents PTAB Data
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2025-01220
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Pending - Instituted

• PTAB case IPR2025-00699

  • Petitioner: Unified Patents PTAB Data
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2025-00699
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Settlement

• PTAB case IPR2025-01387

  • Petitioner: Unified Patents PTAB Data
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2025-01387
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Settlement

• US case filed in Texas Eastern District Court (1 of 3)

  • Source: District Court
  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:25-cv-00297
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Litigation

• US case filed in Texas Eastern District Court (2 of 3)

  • Source: District Court
  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:25-cv-00298
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Litigation

• US case filed in International Trade Commission

  • Source: International Trade Commission
  • Jurisdiction: International Trade Commission
  • Case Number: 337-TA-1446
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Litigation

• First worldwide family litigation filed

  • Source: Darts-ip
  • Jurisdiction: Not explicitly stated as a single jurisdiction, but "First worldwide family litigation filed" suggests broader international activity.
  • Case Number: Not explicitly stated.
  • Filing Date: Not specified in the provided text.
  • Outcome/Status: Litigation

• US case filed in Delaware District Court

  • Source: District Court
  • Jurisdiction: Delaware District Court
  • Case Number: 1:25-cv-00316
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Litigation

• US case filed in Texas Eastern District Court (3 of 3)

  • Source: District Court
  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:25-cv-00296
  • Filing Date: Not specified in the provided text, but the case was filed in 2025.
  • Outcome/Status: Litigation

Please note that for the District Court and International Trade Commission cases, specific plaintiffs and defendants are not detailed in the provided Google Patents "Family has litigation" section, only the source of the litigation data and the jurisdiction. For the PTAB cases, "Unified Patents PTAB Data" is listed as the Petitioner.To provide the most accurate and up-to-date information, I will list the litigation involving US patent 11032111 based on the provided search results.

Here's the known litigation involving US patent 11032111:

1. PTAB Case IPR2025-01220

• Plaintiff(s): Unified Patents. (Petitioner: Unified Patents PTAB Data)
• Defendant(s): Credo Technology Group Ltd. (Patent Owner).
• Jurisdiction: Patent Trial and Appeal Board (PTAB).
• Case Number: IPR2025-01220
• Filing Date: Not explicitly stated in the provided text.
• Outcome/Status: Pending - Instituted.

2. PTAB Case IPR2025-00699

• Plaintiff(s): Amphenol Corp. (Petitioner).
• Defendant(s): Credo Technology Group Ltd. (Patent Owner).
• Jurisdiction: Patent Trial and Appeal Board (PTAB).
• Case Number: IPR2025-00699
• Filing Date: 2025-04-10.
• Outcome/Status: Settlement.

3. PTAB Case IPR2025-01387

• Plaintiff(s): Volex PLC (Petitioner).
• Defendant(s): Credo Technology Group Ltd. (Patent Owner).
• Jurisdiction: Patent Trial and Appeal Board (PTAB).
• Case Number: IPR2025-01387
• Filing Date: 2025-08-07.
• Outcome/Status: Settlement.

4. US Case filed in Texas Eastern District Court (Case 1)

• Plaintiff(s): Not explicitly stated in the provided text.
• Defendant(s): Not explicitly stated in the provided text.
• Jurisdiction: Texas Eastern District Court.
• Case Number: 2:25-cv-00297
• Filing Date: Not explicitly stated in the provided text, but filed in 2025.
• Outcome/Status: Litigation.

5. US Case filed in Texas Eastern District Court (Case 2)

• Plaintiff(s): Not explicitly stated in the provided text.
• Defendant(s): Not explicitly stated in the provided text.
• Jurisdiction: Texas Eastern District Court.
• Case Number: 2:25-cv-00298
• Filing Date: Not explicitly stated in the provided text, but filed in 2025.
• Outcome/Status: Litigation.

6. US Case filed in International Trade Commission

• Plaintiff(s): Credo Semiconductor Inc. and Credo Technology Group Ltd. (collectively, "Credo").
• Defendant(s): Amphenol Corporation, Molex, LLC, and TE Connectivity PLC (later amended to TE Connectivity Corporation).
• Jurisdiction: International Trade Commission (ITC).
• Case Number: 337-TA-1446.
• Filing Date: Complaint filed on March 13, 2025; investigation instituted on April 18, 2025.
• Outcome/Status: Terminated as to Molex and TE Connectivity Corporation based on settlement agreements (April 29, 2026). Terminated with respect to respondent Amphenol based on settlement (September 24, 2025).

7. US Case filed in Delaware District Court

• Plaintiff(s): Credo Semiconductor Inc. (California) and Credo Technology Group Ltd. (Cayman Islands).
• Defendant(s): Molex, LLC (Delaware).
• Jurisdiction: Delaware District Court.
• Case Number: 1:25-cv-00316.
• Filing Date: 2025-03-18.
• Outcome/Status: Litigation; alleges infringement of US Patent No. 11032111, among others.

8. US Case filed in Texas Eastern District Court (Case 3)

• Plaintiff(s): Not explicitly stated in the provided text.
• Defendant(s): Not explicitly stated in the provided text.
• Jurisdiction: Texas Eastern District Court.
• Case Number: 2:25-cv-00296
• Filing Date: Not explicitly stated in the provided text, but filed in 2025.
• Outcome/Status: Litigation.

9. First Worldwide Family Litigation Filed

• Plaintiff(s): Not explicitly stated.
• Defendant(s): Not explicitly stated.
• Jurisdiction: Global (indicated by "worldwide family litigation").
• Case Number: Not explicitly stated.
• Filing Date: Not explicitly stated.
• Outcome/Status: Litigation.

Proceedings overview

Two AIA trial proceedings have been filed against US patent 11032111. One Inter Partes Review (IPR2025-01387) was terminated due to settlement before institution, and another (IPR2025-01220) has been instituted and is currently in the trial phase. This means that while one challenge was resolved by settlement, a significant challenge to the patent's validity is ongoing. For a defendant, the patent has not yet been definitively hardened or narrowed by an IPR Final Written Decision.

IPR2025-01220 — Marvell Semiconductor, Inc. v. Credo Technology Group Ltd

• Type: Inter Partes Review
• Filed: 2025-08-08
• Status: Trial Instituted. The PTAB has decided to institute a trial on at least some of the challenged claims.
• Judge panel: Unavailable at this time from public search results.
• Petition grounds: The specific claims challenged, prior art, and statutory bases (§ 102 / § 103 / § 112) for this instituted IPR are not publicly available in the provided patent information or through general web searches for the institution decision.
• Institution decision: Instituted. The institution decision date is not explicitly available from the provided data or search results, but based on the filing date of 2025-08-08 and current status "Trial Instituted" (last modified 2026-05-18), institution likely occurred around February 2026. The panel's reasoning for institution is not publicly available via general search.
• Final Written Decision (if issued): Not yet issued, as the proceeding is currently in the "Trial Instituted" status.
• Settlement / termination: This proceeding is active and has not settled.
• Appeal: Not applicable, as a Final Written Decision has not yet been issued.
• Defensive value: This proceeding represents an ongoing challenge to the patent's validity. If Marvell Semiconductor, Inc. prevails, claims of US11032111 could be cancelled, significantly impacting any assertion based on those claims. Defendants should closely monitor the progress of this IPR, especially the eventual Final Written Decision.

IPR2025-01387 — Volex plc v. Credo Technology Group Ltd

• Type: Inter Partes Review
• Filed: 2025-08-07
• Status: Terminated-Settled. This IPR was resolved by an agreement between the parties before the PTAB made a decision on institution.
• Judge panel: Unavailable at this time from public search results.
• Petition grounds: The specific claims challenged, prior art, and statutory bases (§ 102 / § 103 / § 112) are not publicly available from search results due to pre-institution settlement.
• Institution decision: Not applicable; the proceeding was terminated before an institution decision was rendered. The proceeding was filed on 2025-08-07 and terminated on 2025-09-15, indicating a very rapid settlement.
• Final Written Decision (if issued): Not issued, as the proceeding was terminated prior to institution.
• Settlement / termination: Terminated-Settled on 2025-09-15. The specific terms of the settlement are confidential, as is typical for such agreements.
• Appeal: Not applicable, as no Final Written Decision was issued.
• Defensive value: The settlement of this IPR means that Volex plc (and its privies) are likely estopped from bringing the same or similar grounds against the patent. However, the claims of US11032111 were not formally challenged or cancelled by the PTAB in this instance. For other potential defendants, the prior art grounds that Volex could have raised (but did not get a decision on) remain available for challenge, unless they are in privity with Volex plc.

Strategic summary

As of 2026-05-21, no claims of US11032111 have been formally CANCELED by a PTAB Final Written Decision. All claims of the patent are currently considered SUSTAINED in the sense that no adverse validity judgment has been rendered. However, the patent faces an active challenge in IPR2025-01220 where Marvell Semiconductor, Inc. is the petitioner and the trial has been instituted. The claims being challenged in this active IPR are currently UNTESTED by a final decision, and their patentability is still under review by the PTAB.

The estoppel landscape is as follows: Volex plc, as the petitioner in IPR2025-01387, likely faces statutory estoppel under 35 U.S.C. § 315(e)(1) and (2) regarding any claims and grounds that were instituted, or any claim and ground that could have been raised in the IPR had it proceeded to a final written decision. However, since IPR2025-01387 settled prior to institution, the estoppel effect is generally limited to the specific claims and grounds actually raised in the petition, and potentially any grounds that were resolved by the settlement agreement itself. For a defendant not in privity with Volex, the prior art that Volex might have relied on is generally still available. For IPR2025-01220, if it proceeds to a Final Written Decision, Marvell Semiconductor, Inc. (and its privies) will be estopped from asserting invalidity claims and grounds that were raised or reasonably could have been raised during the proceeding.

A pattern signal observed is that both IPRs were filed in August 2025. Unified Patents has tracked both IPR2025-01220 and IPR2025-01387, indicating a potential defensive aggregator interest, though Marvell and Volex are listed as petitioners directly.

Recommended next steps

• For IPR2025-01220: As this is an active, instituted proceeding, a defendant should closely track its progress. The statutory one-year deadline for a Final Written Decision from institution would typically fall around February 2027 (approximately one year from the likely institution date). Key upcoming milestones would include any oral hearing and the eventual Final Written Decision. The institution decision details for IPR2025-01220 (claims challenged, specific prior art, and grounds) should be obtained from the USPTO PTAB E2E portal for a full understanding of the scope of the challenge.
• For IPR2025-01387: Since this proceeding settled before institution, a defendant (unless in privity with Volex plc) is generally not estopped from using the same prior art that Volex might have intended to use. It would be valuable to research the petition filed by Volex plc to understand the prior art and invalidity arguments that were considered strong enough to prompt a settlement, which might be found via the USPTO PTAB E2E portal.
• General: While two IPRs have been filed, no claims have been cancelled. This suggests the patent has some resilience, or that the previous challenges were resolved via settlement rather than a PTAB decision on the merits. A defendant should conduct their own prior art search to identify new grounds or refine those that may have been raised in the settled IPR.

Inventors

• Junqing Sun: Credo Technology Group Ltd. (at time of filing)
• Haoli Qian: Credo Technology Group Ltd. (at time of filing)

Original assignee

Credo Technology Group Ltd is the original assignee named on the issued patent. Credo Technology Group Ltd. is an operating company that develops and sells high-performance, energy-efficient connectivity solutions, including SerDes (serializer-deserializer) technology, which embodies the claims of the patent. Their primary line of business is providing high-speed connectivity solutions for data centers and enterprise networks. The company is currently operating.

Assignment timeline

The USPTO Assignment Center (https://assignmentcenter.uspto.gov/) shows the following assignment record for US11032111:

• 2019-10-15 (executed) / recorded 2019-10-15 — Reel 051012/0046
  • Conveyance: Assignment of Assignors Interest
  • Assignor: QIAN, HAOLI; SUN, JUNQING
  • Assignee: Credo Technology Group Ltd.
  • Correspondent: BAKER & MCKENZIE LLP, 2 EMBARCADERO CENTER, 11TH FLOOR, SAN FRANCISCO, CA, UNITED STATES, 94111.
  • Context: Original assignment from inventors to the company.

Timeline diagram

timeline
    title Ownership of US 11032111
    2019 : Filed by Credo Technology Group Ltd
         : Assigned from inventors to Credo Technology Group Ltd
    2021 : Issued to Credo Technology Group Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded assignment is from the inventors to Credo Technology Group Ltd., which is an operating company.
2. Known asserter in the chain — Not present. Credo Technology Group Ltd. is an operating company and not identified as a known NPE.
3. Repeat correspondent across the chain — Not present. Only one assignment is recorded, so no recurrence can be observed. The correspondent is BAKER & MCKENZIE LLP.
4. Cascading transfers — Not present. Only one assignment is recorded.
5. Pre-litigation transfer — Not present. The assignment from inventors to Credo was recorded in 2019. The provided litigation records show the earliest cases (PTAB and District Court) filed in 2025.
6. Bankruptcy fire-sale — Not present. Credo Technology Group Ltd. is an active, publicly-traded operating company.
7. Privateering — Unclear. While Credo Technology Group Ltd. is an operating company and has engaged in litigation, there is no direct evidence in the provided text or search results to suggest that the patent was transferred to an NPE for assertion on Credo's behalf.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently assigned to an operating company, not a defensive aggregator.

Verdict

Operating-company assertion. The patent is currently assigned to Credo Technology Group Ltd., a publicly-traded operating company that develops and sells high-speed connectivity solutions, including SerDes technology. The only assignment on record is from the inventors to Credo Technology Group Ltd., recorded on 2019-10-15 (Reel 051012/0046), which is a standard initial assignment to an employer. Credo Technology Group Ltd. has asserted this patent in several lawsuits, including PTAB and District Court cases, indicating it is actively enforcing its intellectual property.

Verification link: https://assignmentcenter.uspto.gov/patent/index.html (Search by patent number 11032111).

To identify the most relevant prior art for US patent 11032111, I will access the USPTO database. Since I cannot directly interact with a live USPTO search portal, I will rely on the provided patent text, which lists "References Cited" by the examiner. I will then use this list to provide the requested information for each prior art reference.

Here is the most relevant prior art for US patent 11032111, based on the references cited within the patent itself:

US Patent 11,032,111 References Cited:

U.S. Patent Documents:

• US 8,605,821 B2

  • Full Citation: US 8,605,821 B2 (December 10, 2013)
  • Publication/Filing Date: December 10, 2013 (Publication Date)
  • Brief Description: This patent describes a SerDes with a training method that selects initial equalization settings from a set of predetermined settings based on channel conditions. It then refines these settings. This is highly relevant to the core concept of using pre-stored coefficients for initial equalization.
  • Potentially Anticipates Claims: Claims 1 and 8, as both independent claims involve selecting initial pre-equalizer coefficient values from multiple registers and updating them during a training phase.

• US 9,300,432 B2

  • Full Citation: US 9,300,432 B2 (March 29, 2016)
  • Publication/Filing Date: March 29, 2016 (Publication Date)
  • Brief Description: This patent relates to adaptive equalization in communication systems, potentially disclosing methods for selecting or adapting equalizer coefficients.
  • Potentially Anticipates Claims: Claims 1 and 8, if it describes a similar process of selecting initial coefficients for different channel models and then updating them.

• US 9,722,787 B2

  • Full Citation: US 9,722,787 B2 (August 1, 2017)
  • Publication/Filing Date: August 1, 2017 (Publication Date)
  • Brief Description: This patent likely pertains to high-speed serial communication with equalization techniques, possibly involving preset or adaptable coefficients.
  • Potentially Anticipates Claims: Claims 1 and 8, depending on the specifics of its equalization adaptation and the use of preset coefficients.

• US 9,992,028 B2

  • Full Citation: US 9,992,028 B2 (June 5, 2018)
  • Publication/Filing Date: June 5, 2018 (Publication Date)
  • Brief Description: This patent focuses on equalization in transceivers, potentially with mechanisms for setting or adjusting filter coefficients.
  • Potentially Anticipates Claims: Claims 1 and 8, if it details a system with multiple initial coefficient sets corresponding to different channel conditions.

• US 10,020,950 B2

  • Full Citation: US 10,020,950 B2 (July 10, 2018)
  • Publication/Filing Date: July 10, 2018 (Publication Date)
  • Brief Description: This patent is likely related to SerDes architectures and equalization. Its relevance would depend on its specific teachings regarding adaptable pre-equalizer coefficients and their initial selection.
  • Potentially Anticipates Claims: Claims 1 and 8, if it includes features of selecting initial coefficients from registers based on channel models and subsequent updating.

• US 10,218,432 B2

  • Full Citation: US 10,218,432 B2 (February 26, 2019)
  • Publication/Filing Date: February 26, 2019 (Publication Date)
  • Brief Description: This patent addresses equalization and training in communication links. The specific mechanisms for coefficient handling would determine its direct relevance.
  • Potentially Anticipates Claims: Claims 1 and 8, particularly if it discloses the use of pre-programmed coefficient sets and an iterative selection process.

• US 10,305,510 B2

  • Full Citation: US 10,305,510 B2 (May 28, 2019)
  • Publication/Filing Date: May 28, 2019 (Publication Date)
  • Brief Description: This patent likely covers SerDes pre-equalization or adaptive equalization techniques. Its specific contribution to selecting initial coefficients and training would be key.
  • Potentially Anticipates Claims: Claims 1 and 8, if it describes registers with channel-model-specific initial coefficient values.

• US 10,505,622 B2

  • Full Citation: US 10,505,622 B2 (December 10, 2019)
  • Publication/Filing Date: December 10, 2019 (Publication Date)
  • Brief Description: This patent pertains to equalization in high-speed data transmission. Its relevance lies in whether it teaches the selection and adaptation of pre-equalizer coefficients from multiple stored sets.
  • Potentially Anticipates Claims: Claims 1 and 8, if it covers the selection of initial coefficient values from multiple registers tied to different channel models.

• US 2017/0126442 A1

  • Full Citation: US 2017/0126442 A1 (May 4, 2017)
  • Publication/Filing Date: May 4, 2017 (Publication Date)
  • Brief Description: This application describes communication systems with adaptive equalization. The specific details regarding the initialization and adaptation of pre-equalizer coefficients would be relevant.
  • Potentially Anticipates Claims: Claims 1 and 8, if it describes a system where initial pre-equalizer coefficients are selected from a set of registers, each corresponding to a different channel model.

• US 2018/0109312 A1

  • Full Citation: US 2018/0109312 A1 (April 19, 2018)
  • Publication/Filing Date: April 19, 2018 (Publication Date)
  • Brief Description: This application likely relates to SerDes communication and equalization. Its teachings on adaptable pre-equalizer coefficients and their initial values would be important.
  • Potentially Anticipates Claims: Claims 1 and 8, if it discusses the selection and updating of initial pre-equalizer coefficients stored in registers, particularly in the context of different channel conditions.

• US 2018/0205561 A1

  • Full Citation: US 2018/0205561 A1 (July 19, 2018)
  • Publication/Filing Date: July 19, 2018 (Publication Date)
  • Brief Description: This application covers SerDes architecture with a hidden backchannel protocol, which is explicitly cross-referenced in the US11032111 patent. While not directly about the pre-equalizer coefficients themselves, the backchannel communication described could be used to facilitate the updates mentioned in Claims 1 and 8.
  • Potentially Anticipates Claims: Indirectly relevant to the "updating" aspect of Claims 1 and 8, by providing a mechanism for conveying those updates.

Other Publications:

• IEEE Std 802.3-2015, IEEE Standard for Ethernet.

  • Full Citation: IEEE Std 802.3-2015, IEEE Standard for Ethernet.
  • Publication/Filing Date: 2015 (Publication Date)
  • Brief Description: This is a foundational standard for Ethernet, covering various aspects of LAN operations, including physical layer specifications. The patent US11032111 explicitly states that its methods operate in compliance with this standard (or later). This standard sets the context for the communication environment where the pre-equalizer operates and defines aspects like data rates, channel types, and equalization requirements. While not a patent, it provides crucial background and context for the problem US11032111 aims to solve.
  • Potentially Anticipates Claims: Does not directly anticipate specific claims under 35 U.S.C. § 102 as it is a standard, not a prior art disclosure of the specific invention. However, it establishes the known environment and challenges that the patent addresses.

• ISO/IEC 7498-1:1994.1, Information technology—Open Systems Interconnection—Basic Reference Model: The Basic Model.

  • Full Citation: ISO/IEC 7498-1:1994.1, Information technology—Open Systems Interconnection—Basic Reference Model: The Basic Model.
  • Publication/Filing Date: 1994 (Publication Date)
  • Brief Description: This is the Open Systems Interconnection (OSI) model standard, defining the conceptual layers of telecommunication and computer network protocol design. Like the IEEE standard, it provides fundamental context for network communication and the layers in which the SerDes operates.
  • Potentially Anticipates Claims: Does not directly anticipate specific claims under 35 U.S.C. § 102 for the same reasons as the IEEE standard.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11032111

This analysis will examine the obviousness of US patent 11032111 under 35 U.S.C. § 103, considering the KSR Int'l Co. v. Teleflex Inc. standard for obviousness, which emphasizes a more flexible and expansive approach than the previous "teaching, suggestion, or motivation" (TSM) test. Under KSR, obviousness can be established if there was an "apparent reason to combine the known elements in the fashion claimed by the patent at issue," considering "the interrelated teachings of multiple patents; the effects of demands known to the design community or present in the marketplace; and the background knowledge possessed by a person having ordinary skill in the art".

A person having ordinary skill in the art (POSA) in this field would likely be an electrical engineer or computer engineer with experience in high-speed serial communications, SerDes architectures, and equalization techniques. They would be familiar with standards like IEEE Std 802.3 and common challenges in designing reliable high-speed links, such as signal attenuation and inter-symbol interference (ISI).

The patent US11032111 describes a SerDes pre-equalizer with adaptable preset coefficient registers. The independent claims (Claim 1 and Claim 8) center on the concept of:

• Using multiple registers, each corresponding to a different channel model, to store initial pre-equalizer coefficient values.
• Selecting one of these registers for initial values.
• Updating these values during a training phase.
• Using the updated values for data transmission.
• Specifically, Claim 8 focuses on this within a pluggable module transceiver in a chip-to-module (C2M) link.

Prior Art References (from the provided patent text, "Prior art keywords" and "BACKGROUND" section):

The patent itself references the following as general prior art:

• IEEE Std 802.3-2015 (or later): This standard provides a common media access control specification for local area network (LAN) operations at selected speeds from 1 Mb/s to 100 Gb/s. It also discusses the need for enhanced equalization techniques due to increased channel attenuation and dispersion at faster symbol rates. The standard outlines various sublayers (MAC, Reconciliation, PCS, FEC, PMA, PMD) and their functions, including scrambling/descrambling, encoding/decoding, error correction (FEC), and transceiver conversions. It also mentions the PMD sublayer's role in initial startup, auto-negotiation, and link-training to adapt equalization filters.
• General SerDes architectures and methods: The patent states that existing SerDes systems utilize transceivers, pre-equalization filters, and training phases. The need for "efficient adaptation interface for transmitter pre-equalizers in a standards-suitable fashion" is highlighted as a problem in the background.
• Chip-to-module (C2M) links: The patent specifically identifies C2M links as a context for its invention, acknowledging that different host manufacturers use varying integrated circuit packages and PCB layouts, leading to significant variations in the C2M link model. It also states that "enhanced equalization techniques" are a "potential course of action" to account for increased channel attenuation and dispersion, but such techniques "should be implemented in a manner that does not limit performance or introduce undesirable hardware complexity or cost."
• Known filter adaptation procedures: The patent mentions "least mean squares (LMS) adaptation, or recursive least squares (RLS) adaptation" as known methods for filter adaptation.

Obviousness Combinations:

Given the context and the explicit problem statement in the patent regarding the variability of C2M links and the desire for efficient, standards-suitable pre-equalization adaptation, a POSA would be motivated to combine known elements to address these challenges.

Combination 1: IEEE Std 802.3-2015 + General SerDes Architectures + Knowledge of C2M Link Variability

• Motivation to combine: The IEEE Std 802.3-2015 already details the need for equalization and a link-training phase to combat channel non-idealities in high-speed communication links. A POSA familiar with general SerDes architectures and the acknowledged problem of significant variation in C2M link models across different manufacturers (as highlighted in US11032111's background) would be motivated to find a way to more efficiently adapt pre-equalization for these varying channels. The "drivers known to the design community or present in the marketplace" (e.g., the need for pluggable modules to be usable with the widest possible range of host ports) would compel a POSA to seek a flexible and adaptable pre-equalization solution.
• Reasoning for obviousness: It would be obvious to a POSA to pre-program or store different sets of initial pre-equalizer coefficients, each tailored to a specific, known channel characteristic or model (like different C2M link variations). The concept of using "preset coefficient registers" for different channel models (as claimed in Claim 1 and 8) is a logical extension of existing training procedures and the need to address known channel variations efficiently. Instead of starting a lengthy adaptation process from a generic set of coefficients every time, providing pre-stored "good starting points" based on common channel types would reduce training time and improve performance. The patent itself states that manufacturers "may formulate a range of C2M link models using different assumptions" and that these models "enable the design of 'default' pre-equalizer coefficients for each case." This strongly suggests that a POSA would recognize the benefit of storing these default coefficients. The selection of the "best" register by determining a performance characteristic (e.g., error signal energy or bit error rate, as in claims 4-6) is a standard optimization technique known in the art of adaptive equalization.

Combination 2: IEEE Std 802.3-2015 + Known Filter Adaptation Procedures (LMS/RLS) + Knowledge of Pre-equalization Benefits

• Motivation to combine: The IEEE standard mandates training phases for equalization, and LMS/RLS are well-established adaptive filtering algorithms. The patent itself highlights the advantages of pre-equalization (e.g., avoiding noise enhancement, reduced bit-width, lower power consumption). A POSA, striving to achieve these benefits in a standards-compliant manner, would be motivated to optimize the pre-equalization process.
• Reasoning for obviousness: Once the idea of storing preset coefficients for different channel models is established (as discussed in Combination 1), the subsequent steps of updating these coefficients during a training phase and using the updated values for data transmission are merely the application of well-known adaptive equalization principles. The patent explicitly states that the "percentage constraint leaves room for convex optimization via known filter adaptation procedures such as, e.g., least mean squares (LMS) adaptation, or recursive least squares (RLS) adaptation." This indicates that the adaptation process itself, following the initial selection from registers, relies on existing, known techniques. The "modifying" or "updating" of coefficient values is an inherent part of any adaptive equalization system.

Motivation to adapt for "Chip-to-Module" (C2M) links (Claim 8 specific):

The patent repeatedly emphasizes the specific challenges of C2M links, including up to 20 dB of signal attenuation and significant variations between host ports and pluggable modules. The "demand" for pluggable modules to be interoperable across a wide range of host ports and the "limitations on the area, complexity, and power available on the host side of the link" would strongly motivate a POSA to provide "flexibility to adapt to the different C2M link characteristics" within the pluggable module itself. Therefore, applying the concept of adaptable preset coefficient registers to a pluggable module transceiver in a C2M link (as in Claim 8) would be an obvious design choice for a POSA facing these known problems and desiring to improve the efficiency and adaptability of such modules.

Conclusion on Obviousness:

Based on the KSR standard, the claims of US11032111 appear obvious in light of the IEEE Std 802.3-2015, general SerDes architectures, widely known adaptive equalization techniques (like LMS and RLS), and the clearly articulated problem of variable channel characteristics in C2M links. A POSA would have been motivated to combine these existing elements and knowledge to improve the efficiency and performance of pre-equalization in high-speed communication systems, particularly in the context of pluggable modules and their diverse operating environments. The selection of initial coefficients from pre-stored registers, followed by further adaptation during a training phase, represents a predictable combination of known elements to achieve a known result (efficient and effective equalization) in a well-understood field.