US 11032111

The USPTO and CAFC search results did not contradict the information already extracted from the provided patent text about US11032111. The CAFC search for "CAFC dockets 2026 patent 11032111" did not return any specific cases related to patent 11032111 in the Federal Circuit's 2026 schedule. The Google Patents information did mention PTAB cases and US District Court cases for 2025, but not specifically CAFC dockets for 2026. Therefore, I will state that no CAFC 2026 dockets were found for this specific patent.

I have all the necessary information to provide the concise summary.

Concise Summary of US Patent 11032111

Title: Serdes pre-equalizer having adaptable preset coefficient registers

Assignee: Credo Technology Group Ltd

Inventors: Junqing Sun, Haoli Qian

Filing Date: August 27, 2019

Issue Date: June 8, 2021

Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a method for a SerDes (serializer-deserializer) communication system. The method involves a transceiver choosing one of several available registers. Each register holds a set of initial settings (coefficient values) for a pre-equalizer, and each set is designed for a different type of communication channel. During a "training phase," these initial settings are adjusted or "updated." Finally, the transceiver uses these updated pre-equalizer settings to send out a data stream.
• Independent Claim 8: This claim describes a hardware system, specifically a chip-to-module communication link. It includes a connector that links a transceiver on a "port" (like on a network switch) to a transceiver inside a "pluggable module" (like an SFP+ module). The pluggable module's transceiver has one or more transmit filters, which prepare (pre-equalize) the data streams before they are sent to the port transceiver. It also has a controller with multiple registers, each storing different initial coefficient values. The controller uses one of these registers to set the initial coefficient values for the transmit filters.

CAFC 2026 Dockets: No specific cases related to patent 11032111 were found in the CAFC 2026 dockets.Concise Summary of US Patent 11032111

Title: Serdes pre-equalizer having adaptable preset coefficient registers

Assignee: Credo Technology Group Ltd

Inventors: Junqing Sun, Haoli Qian

Filing Date: August 27, 2019

Issue Date: June 8, 2021

Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a method for a SerDes (serializer-deserializer) communication system. The method involves a transceiver choosing one of multiple pre-defined registers. Each of these registers holds a different set of initial coefficient values for a pre-equalizer, with each set corresponding to a different expected communication channel condition. During a "training phase," these initial pre-equalizer coefficient values are adjusted. The transceiver then uses these updated coefficient values to transmit a data stream.
• Independent Claim 8: This claim describes a hardware system, specifically a chip-to-module communication link. It includes a port connector that connects a port transceiver (e.g., on a host device) to a pluggable module transceiver. The pluggable module transceiver contains one or more transmit filters, which are used to pre-equalize the serial data streams being sent to the port transceiver. The module also has a controller equipped with multiple registers, where each register stores a set of initial coefficient values. The controller selects and uses one of these registers to configure the initial coefficient values for its transmit filters.

CAFC 2026 Dockets: No specific cases related to patent 11032111 were found in the CAFC 2026 dockets.