US 10868031

I'll verify against USPTO/CAFC sources before summarizing.

Now let me check the USPTO/PTAB and CAFC litigation posture, and pull the actual US claim set.

Let me pull the actual granted US claim set for the '031 patent.

US 10,868,031 B2 — Verification Summary

Source caveat up front: I retrieved the Google Patents full text (https://patents.google.com/patent/US10868031/en), the USPTO/PTAB record for IPR2024-00790, and the AU family member (AU2018433803B2, which reproduces a claim set for this family). I could not retrieve the verbatim granted US claim text in this session — it is not present in the Google Patents text I was given, which truncates before the claims. The independent-claim descriptions below are reconstructed from (a) the '031 specification/BRIEF SUMMARY, (b) the corresponding AU granted claims in the same family, and (c) the PTAB record. Treat exact US wording as unverified.

Also note a date inconsistency: the prompt says today is 2026-04-26, but my retrieval is dated 2026-09-25 and includes events through September 2026. I report the later events and flag them as such.

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1. Bibliographic data (from the '031 front page data)

Abstract (verbatim): "Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces."

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2. Plain-language overview of the independent claims

Independent claim 1 — device claim. A 3D memory (NAND) device comprising:

• a substrate;
• a multiple-stack staircase structure — i.e., two or more stacked staircase structures, each made of conductor layers (word lines) with each conductor layer sandwiched between two insulating layers;
• a filling structure (dielectric fill, e.g., silicon oxide, "retro-stepped") surrounding the multiple-stack staircase structure;
• a semiconductor channel running through the multiple-stack staircase structure, where the channel's sidewall surfaces are "unaligned" (disjointed) — the patent defines this as the consequence of building the channel by aligning/adjoining separately-etched sub-channel holes in successive dielectric stacks, so the hole diameter is inconsistent at the junctions of high-aspect-ratio etches; and
• a supporting pillar running through at least one of the staircase structure and the filling structure, where the pillar's sidewall surfaces are "aligned" (non-disjointed) — i.e., the pillar hole was not formed by adjoining per-stack sub-pillar holes, but etched through the already-assembled multiple-stack structure in one go.

In the AU family member the granted claim 1 carries an additional "wherein the semiconductor channel is formed by…" clause reciting: forming a first sub-channel hole in a first dielectric stack → filling it with a sacrificial filling material → forming a second dielectric stack directly on the first → forming a second sub-channel hole that aligns with the sacrificial fill and adjoins the first hole to form a channel hole into the substrate → removing the sacrificial fill → filling the channel hole with a second material. That "product-by-process" language appears to be a post-filing amendment in the AU case; I cannot confirm whether the granted US claim 1 contains it, and the PTAB record (below) treated US claim 1 as the sole independent claim among the challenged claims.

Independent method claim (claim 6 in the AU set). A method of forming a memory device, comprising: forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure, each stack being a plurality of dielectric pairs (sacrificial layer / insulating layer) arranged perpendicular to the substrate; forming a filling structure surrounding the multiple-stack staircase structure; forming a semiconductor channel through the multiple-stack staircase structure having unaligned sidewall surfaces; and forming a supporting pillar through the staircase structure and/or the filling structure having aligned sidewall surfaces. Pillar formation is expressly recited as: photoresist over the filling structure/staircase structure → pattern an opening at the pillar location → use it as an etch mask to etch a pillar hole whose bottom contacts the substrate → fill the pillar hole with a first material.

Underlying inventive point of both independents: instead of patterning each dielectric stack's staircases, pillar holes, and channel holes separately with separate photomasks (prior practice), the multiple dielectric stacks are etched together in a single staircase-forming patterning process, and the pillar hole is etched through the finished multi-stack structure rather than by adjoining sub-pillar holes. The pillar may be filled with the same channel-forming layers (charge-trap film, semiconductor channel film, dielectric core) deposited simultaneously with the channels (dummy filling layers), or with different material (silicon oxide liner plus a support metal such as Cu, Co, Ni or Al). The specification also discloses a "double-channel" variant, in which the channel is split by a doped-semiconductor connection layer between two adjacent staircase structures (two sub-channels joined by that layer).

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3. Scope note on the claim set

The US patent appears to contain at least claims 1–5 (the set challenged at the PTAB, per the Patent Owner Response: "The only independent claim of the Challenged Claims, claim 1"). Reporter summaries indicate the US patent also includes method claims and, per the specification, a double-channel (connection-layer) aspect. The exact count and wording of US independent claims is not verified here; the AU sibling has 9 claims with device claims 1–5 and method claims 6–9.

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4. PTAB and court posture (this is where the '031 patent's current status actually turns)

• IPR2024-00790, Micron Technology, Inc. v. Yangtze Memory Technologies Co., Ltd. over US 10,868,031 B2. Petition filed ~2024-04-18; instituted 2024-10-28; Final Written Decision 2025-10-23. Outcome: claims 1–3 held unpatentable (the panel found Micron's Kim-based showing sufficient), while claims 4–5 were upheld — i.e., partial invalidation, not full cancellation. See https://ai-lab.exparte.com/case/ptab/IPR2024-00790/micron-technology-inc-v-yangtze-memory-technologies-co-ltd and the reporting at https://news.qq.com/rain/a/20251025A049MK00.
  • Note: Google Patents labels this PTAB entry "Unified Patents PTAB Data." That is the data vendor attribution on the family page; the named petitioner in IPR2024-00790 is Micron Technology, Inc.
  • Director Review denied 2026-03-17 (Paper 38), covering IPR2024-00790 together with parallel IPRs IPR2024-00792 (US 11,468,957) and IPR2024-00794 (US 10,950,623).
• Federal Circuit 2026 dockets. The Google Patents family page lists CAFC cases 26-1336 and 26-1161 against this family (https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/26-1336 and .../case/26-1161). Separately, reporting confirms a Federal Circuit appeal Yangtze Memory Technologies Co. v. Micron Technology, Inc. docketed 2026-06-15, which concerns Director Squires' January 2026 decision vacating institution of YMTC's IPRs (IPR2025-00098/00099) against Micron's patents over YMTC's failure to name all real parties in interest (35 U.S.C. §312(a)(2)). I cannot confirm whether 26-1161 / 26-1336 are the appeal of the '031 FWD or the RPI/sovereign-eligibility appeal — those are distinct matters and I flag this as unresolved rather than asserting a mapping.
• District court: YMTC's original US complaint against Micron was filed in the Northern District of California, Case No. 3:23-cv-05792 (Google Patents also lists the same case number under the Eastern District of California, consistent with transfer/redocketing). The '031 patent is one of the patents YMTC asserted there (listed among eight asserted patents, incl. US 10,950,623; 10,861,872; 10,937,806; 10,658,378; 11,468,957; 11,501,822; 11,600,342).
• Germany (context, not this US patent): on 2026-09-18 the Munich I Regional Court granted YMTC injunctions against Micron on two German utility models (DE 20 2020 006 166 U1 – "staircase structure"; DE 20 2021 004 551 U1 – word-line contact barrier). Three other Munich actions, including one on a "multi-stack 3D memory device," were stayed. Those are German utility models, not the '031 US patent, so do not read them as a finding on US 10,868,031.

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5. Statements I cannot make with confidence

1. The verbatim text and count of the granted US claims (I could not retrieve them; the AU sibling claim set and the PTAB record are the basis for §2/§3).
2. Whether the granted US claim 1 includes the AU's "wherein the semiconductor channel is formed by…" process limitation.
3. The precise mapping of CAFC 26-1336 / 26-1161 to the '031 IPR appeal rather than to the YMTC-v.-Micron RPI Director Review appeal.
4. Whether the '031 patent's claims 4–5 (the surviving claims) have since been subject to a further challenge or amendment; no such record surfaced in this search.
5. Google Patents shows "Status: Active" with a 2038-07-27 anticipated expiration, but the PTAB FWD extinguished claims 1–3; "Active" therefore does not mean the originally granted claim scope remains intact.

I'll research litigation involving US patent 10868031. Let me search multiple sources.

The Google Patents page lists specific litigation links. Let me investigate each case number and the PTAB proceeding.

Let me verify the PTAB outcome, the CAFC appeals, and the E.D. Cal. case.

Litigation Involving U.S. Patent No. 10,868,031

Short answer: Yes — this patent is in active litigation. U.S. 10,868,031 ("Multiple-stack three-dimensional memory device and fabrication method thereof," Yangtze Memory Technologies Co., Ltd.) is one of the patents asserted in the global YMTC v. Micron dispute, and it has also been the subject of an instituted AIA trial at the PTAB. Below are the proceedings I could verify, with the specific record identifiers found.

⚠️ Data-integrity note: the patent page I was given (fetched 2026-09-25) is dated later than the "current date" in your instruction (April 26, 2026). Some search results reference events dated September 2026. I have flagged where that matters rather than silently reconciling it.

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1. District Court — YMTC v. Micron (the principal case)

This patent's role in the case: YMTC's Patent L.R. 3‑1 disclosure of asserted claims and infringement contentions expressly asserts claims 1‑2 and 4 of U.S. Patent No. 10,868,031. The accused products are Micron's 96‑layer, 128‑layer, 176‑layer and 232‑layer 3D NAND products (chips and products incorporating them).

Sources:

• https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556878](/patent/1556878)/download-documents (Micron's motion to stay; Dkt. reference to 3:23-cv-05792-RFL)
• https://www.docketalarm.com/cases/PTAB/IPR2024-00788/... (YMTC's 3‑1 contentions, listing "Claims 1-2 and 4 of U.S. Patent No. 10,868,031")
• https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1557307](/patent/1557307)/download-documents (order on motion to dismiss counterclaims, 23-cv-05792-RFL)

Docket-number discrepancy (not auto-corrected): The Google Patents litigation feed for US10868031 lists two California district court entries — "California Northern District Court, case 5:23-cv-05792" and "California Eastern District Court, case 3:23-cv-05792." The actual operative docket number appearing throughout the parties' papers is 3:23-cv-05792-RFL (N.D. Cal.). I could not verify any separate, live E.D. Cal. action on this patent; the E.D. Cal. entry appears to be a mislabeled duplicate of the N.D. Cal. suit, but I am reporting the identifier literally as it appears rather than "fixing" it.

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2. Related/consolidated district court case

This second suit asserted eleven additional patents (3D NAND and DDR5 products). Based on the record I retrieved, U.S. 10,868,031 was asserted in the first complaint, not the second — the second complaint's patents include the '254 patent (IPR2025-00119). Source: https://ptacts.uspto.gov/ptacts/public-informations/petitions/1556878/download-documents (updated mandatory notice in IPR2025-00119).

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3. PTAB — AIA trial on this patent

Sources:

• https://ai-lab.exparte.com/case/ptab/IPR2024-00790/micron-technology-inc-v-yangtze-memory-technologies-co-ltd (filed 04/18/24; institution 10/28/24; FWD 10/23/25; outcome "Unpatentable")
• https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2024-00790/... (Paper 38, Order Denying Director Review, Mar. 17, 2026)
• https://www.docketalarm.com/cases/PTAB/IPR2024-00792/... (Director Review order covering IPR2024-00790 / -00792 / -00794)

Context: Micron filed IPRs on all eight patents in YMTC's first complaint by May 2024; the PTAB instituted on seven of eight. Across both U.S. suits Micron filed roughly 26 IPR/PGR petitions, a campaign repeatedly litigated in the district court stay briefing.

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4. Federal Circuit appeals

The Google Patents litigation feed for this patent lists two CAFC appeals with this patent's family:

• Court of Appeals for the Federal Circuit, case 26-1336 — https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/26-1336
• Court of Appeals for the Federal Circuit, case 26-1161 — https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/26-1161

Confidence: low on details. I could not retrieve the docket sheets for these two appeals; the search tool returned no matching results before I exhausted my search budget. Given the docket numbers (FY2026) and the October 23, 2025 FWD date, the most likely explanation is that these are appeals arising from the PTAB final written decisions in the Micron v. YMTC IPR wave — most plausibly YMTC's appeal of the adverse FWDs (including IPR2024-00790) and/or appeals of related decisions. I am not asserting the appellant, the appealed-from decision, or the outcome, because I did not verify them. These should be confirmed on PACER/CM-ECF or the Federal Circuit's docket.

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5. Other proceedings the patent page references (family-level, not patent-level)

• Unified Patents PTAB data and Darts‑ip "first worldwide family litigation" (family 64789406) are cited on the patent page as generic family-litigation sources: https://patents.darts-ip.com/?family=64789406
• The global dispute also includes German (Munich I Regional Court) and UPC/UK proceedings. None of the German rulings reported to date involve US 10,868,031 — the Munich September 2026 injunctions concern German utility models DE202020006166U1 (case 7 O 12615/25) and DE202021004551U1 (case 7 O 12614/25), with three further Munich cases (DE202018007011U1, DE202022003278U1, EP3931868) adjourned. Those are not the U.S. patent at issue here, so I have excluded them from the case list and mention them only to avoid confusion.

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⚠️ Near-match to disregard (different patent number)

A search result surfaced Bayer Pharma AG et al. v. Aurobindo Pharma Limited et al., D. Del. 1:25-cv-00631, filed May 21, 2025, which reports "Patent/Trademark Number(s) 10,828,310 B2." Read literally, that is 10,828,310 — a different patent from 10,868,031, and a different technology (pharmaceuticals). It is not litigation involving US 10,868,031 and should not be listed. (Source: https://dockets.justia.com/docket/delaware/dedce/1:2025cv00631/89217)

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Summary of known litigation for US 10,868,031

What I could not confirm: filing dates, appellant identity, and outcomes of CAFC 26-1161 and 26-1336; the existence and content of a genuine E.D. Cal. action; and whether any settlement or license has resolved the dispute. Treat items 4–6 as leads to verify against PACER/CM-ECF and the Federal Circuit docket rather than as established facts.

I'll start by reconciling the structured "PTAB proceedings on file" block (which says none) against the litigation data visible on the patent's own Google Patents page, which lists IPR2024-00790 with a Final Written Decision. Let me search.

Significant discrepancy found: the structured block says no proceedings, but the patent's own record shows IPR2024-00790 with a Final Written Decision. Let me drill into claim-level outcomes, the FWD, and the Federal Circuit appeals.

⚠️ Data-integrity flag — read this first. The structured "PTAB proceedings on file" block in this prompt states the USPTO ODP API returns no AIA trial proceedings for US 10,868,031. That is wrong / stale. The patent's own Google Patents record lists a PTAB case with a Final Written Decision, and web sources confirm a full IPR through FWD, Director Review, and Federal Circuit appeal. I am therefore reporting one AIA trial proceeding, sourced and dated, rather than the default "none." I did not invent any number: IPR2024-00790 appears in both the authoritative patent text block and multiple independent sources.

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Proceedings overview

There is 1 AIA trial proceeding on file for US 10,868,031 — IPR2024-00790 (Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.), which went to a Final Written Decision on 2025-10-23 holding claims 1–3 unpatentable while sustaining claims 4–5; it is now in the appellate phase (Federal Circuit 26-1161 / 26-1336) after a limited remand and a denied Director Review request, giving a defendant a narrowed but not dead patent: the broadest, sole independent claim (claim 1) is invalidated on paper, but the two surviving dependent claims 4–5 carry the same core "filling structure surrounding the multiple-stack staircase structure" limitation that defeated Micron's primary (Tessariol) art theory.

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IPR2024-00790 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review (35 U.S.C. §§ 311–319). The patent text block described it as "PTAB case IPR2024-00790 filed (Final Written Decision)." Note: the "Unified Patents" strings on that block are the data vendor (Unified Patents Litigation Data / PTAB Data), not a party — the petitioner of record is Micron Technology, Inc., not a defensive aggregator.
• Filed: 2024-04-18 (filing date per PTAB dockets; patent's priority date 2018-07-27)
• Status: "Final Written Decision" (verbatim) — outcome coded "Unpatentable" in third-party PTAB summaries. Plain English: trial closed, FWD issued 2025-10-23, claims 1–3 held unpatentable, claims 4–5 upheld, now on appeal at the Federal Circuit. The Board-level proceeding is terminated as of 2025-10-23 (docket "Close" 2025-10-23); the appellate phase is live.
• Judge panel: Administrative Patent Judges Jo-Anne M. Kokoski, Kimberly McGraw, and Michael T. Cygan (oral-hearing record and docket data; a fourth name, Kalyan K. Deshpande, appears in some judge-list aggregations — treat the three-judge panel above as the operative FWD panel and verify against the FWD cover page). Tech Center 2800, Art Unit 2812.
• Petition grounds: § 103 obviousness challenge to the challenged claims of the '031. The Chinese industry report on the decision identifies Micron's asserted art as including "Tessariol" (primary) and Kim, where Kim is Samsung's US 10,381,369. The '031 issued with six claims; claim 1 is the sole independent claim, with claims 2–6 depending from it. The challenged set appears to be claims 1–5 (Patent Owner's Response refers to "the only independent claim of the Challenged Claims, claim 1"). I could not independently verify the complete, verbatim ground-by-ground mapping or whether claim 6 was challenged — verify against the FWD PDF before relying on claim 6's status.
• Institution decision: Instituted 2024-10-28 (per PTAB docket data). I could not retrieve the Board's verbatim institution reasoning; the record shows institution on all challenged claims (post-SAS practice), with the Board preliminarily finding the Kim-based showing adequate for at least claim 1 and adopting Petitioner's POSITA definition — "a person with a bachelor of science degree in electrical engineering or a similar discipline, along with 2-3 years of professional experience... working with memory devices," a definition Patent Owner did not contest for purposes of the proceeding.
• Final Written Decision (2025-10-23): Claim-level verdict:
  • Claims 1, 2, 3 — held unpatentable (obvious). Per the reporting on the decision, only the Kim reference (Samsung US 10,381,369) was found to disclose the subject matter of claims 1–3; the Tessariol-based theory did not carry the day.
  • Claims 4, 5 — sustained (patentable). The panel maintained the validity of claims 4–5.
  • Bottom line quoted from the reporting: PTAB "宣布长江存储该专利权利要求1-3不具备创造性，但是维持了该专利权利要求4-5的效力" — i.e., claims 1–3 unpatentable for lack of inventive step; claims 4–5 sustained.
  • I do not have the FWD's verbatim claim-by-claim table or its exact reasoning sentences and will not fabricate them. The single most important durable finding is that the "filling structure surrounding the multiple-stack staircase structure" limitation — the limitation on which the patent was allowed over Chae during prosecution and on which Patent Owner built its Response — was not overcome by Micron's primary art for claims 4–5.
• Settlement / termination: No settlement. The proceeding ran to a contested FWD and then to appeal; no termination-on-settlement papers appear in the docket record.
• Appeal: Yes — extensive post-FWD activity, all confirming this is not final:
  • 2025-11-05 — Patent Owner's Notice of Appeal (Paper 30).
  • 2025-12-26 — Petitioner's Protective Notice of Cross-Appeal (Paper 35).
  • 2026-01-12 — Federal Circuit limited remand (Paper 36).
  • 2026-03-17 — Order Denying Director Review of the FWD, signed by Under Secretary/Director John A. Squires, addressing IPR2024-00790 (Patent 10,868,031 B2) together with IPR2024-00792 (Patent 11,468,957 B2) and IPR2024-00794 (Patent 10,950,623 B2) — the requests for Director Review were denied (Paper 38).
  • Federal Circuit dockets: the patent record lists two CAFC cases — 26-1336 and 26-1161. Most plausibly these are the Patent Owner's appeal and Micron's cross-appeal (the notice sequence above fits), but I cannot confirm which docket number maps to which party without pulling the CAFC dockets; verify at CourtListener (https://www.courtlistener.com/?q=%2226-1336%22 and https://www.courtlistener.com/?q=%2226-1161%22) or the PTAB E2E docket at https://e2e.uspto.gov/. No CAFC opinion or disposition has issued as of today.
• Defensive value: Split result — procedurally useful, substantively incomplete. Claim 1 — the only independent claim, and the claim most demand letters default to — has been held unpatentable, so any infringement theory built purely on claim 1 is now fighting a live FWD finding of unpatentability (though not yet a certificate of cancellation, because the appeal is pending). But claims 4–5 survived, and they are dependent claims that inherit all of claim 1's limitations plus the pillar/channel-fill differentiation that Micron's art failed to reach. A defendant cannot treat this patent as neutered; it must attack claims 4–5 with new art.

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Strategic summary

Claim status on 10,868,031 today:

The practical consequence: the patent has been narrowed but hardened at the dependent-claim level. The surviving claims 4–5 are the operative assertion targets for anyone facing this patent going forward, and the validity fight over those claims has already been won once by the Patent Owner — against Micron's best primary reference. Note the important caveat: because cancellation of claims 1–3 requires the appeal to conclude and a certificate to issue, a defendant served today should not assume claims 1–3 are formally gone.

Estoppel landscape. Under § 315(e)(2), Micron and its privies are estopped, on the FWD's issuance, from raising in the district court any ground they raised or reasonably could have raised in the IPR — i.e., the Kim- and Tessariol-based § 103 combinations, except that IPR estoppel generally does not reach device/system art and other non-printed-publication invalidity theories (see the estoppel discussion in the parallel YMTC/Micron briefing). Other defendants are not estopped. A non-Micron defendant (e.g., another NAND supplier) remains free to file its own IPR against claims 1–6 — including against claims 4–5 with art Micron never deployed — and to raise any printed publication, product, or system art that Micron did not. The most attractive IPR target is the surviving dependent claims 4–5, on the pillar-fill ("insulating material and a pillar-support material surrounded by the insulating material" vs. channel-fill) limitation that defeated Micron.

Pattern signals. This is not a one-off: it is a large two-way campaign. Micron filed roughly 26 IPR/PGR petitions against YMTC's portfolio (including IPR2024-00788/00789/00790/00791/00792/00794/00909/00911 and later IPR2025-xxxx series). YMTC, in turn, is an aggressive IPR petitioner itself, asserting Micron's own patents (e.g., IPR2025-00499 against Micron's US 8,803,214), which has produced a return-mail/RPI fight over YMTC's governmental character. The underlying district court case is Yangtze Memory Technologies Co., Ltd. v. Micron Technology, Inc., No. 3:23-cv-05792-RFL (N.D. Cal., filed 2023-11-09) — the '031 was among the original asserted patents — and the litigation has been stayed pending the IPR/PGR wave. There is no defensive aggregator in the chain here; the "Unified Patents" references are data-vendor attributions only. Patent Owner is represented at the PTAB by Munger, Tolles & Olson; Micron by Orrick.

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Recommended next steps

1. Pull the FWD immediately (IPR2024-00790, Paper dated 2025-10-23) via PTAB E2E (https://e2e.uspto.gov/) or the public PTAB decisions site, and confirm verbatim: the exact challenged-claim set (1–5 vs. 1–6), the ground-by-ground table, and the exact claim language held unpatentable. The single highest-value drafting input for a new petition is the FWD's treatment of claims 4–5. Link the FWD to your file and quote the disposition in any response to a demand letter.
2. If you are a defendant, state in your invalidity contentions that claims 1–3 stand adjudicated unpatentable (citing the FWD), and note that any infringement theory resting on claim 1 is now exposed; then focus your own art on claims 4–5, using references Micron did not assert.
3. Do not rely on the claim-cancellation. Claims 1–3 are not canceled until the appeal concludes and a certificate issues. Track CAFC 26-1161 and 26-1336 at CourtListener and the Federal Circuit's docket; both a Patent Owner appeal and a Petitioner protective cross-appeal are on file, and a limited remand already occurred on 2026-01-12 with Director Review denied on 2026-03-17. Until an affirmance issues, treat claims 1–3 as "adjudicated unpatentable, subject to appeal."
4. No PTAB trial-stage deadlines remain in IPR2024-00790 — the Board proceeding closed 2025-10-23 (so the statutory one-year § 316(a)(11) clock is spent). The live clocks are appellate and any new IPR a different petitioner chooses to file.
5. Correct the ODP gap. The USPTO-ODP-derived "no PTAB activity" block attached to this analysis is inconsistent with the public record; anyone running clearance or FTO relying on that feed for this patent is being misled. Re-pull from PTAB E2E / the PTAB API before certifying a "no PTAB activity" conclusion.

Items I could not verify and am flagging rather than asserting: the FWD's verbatim reasoning and claim table; the exact challenged-claim roster; the precise mapping of CAFC docket numbers 26-1336 and 26-1161 to the appealing party; and whether claim 6 was ever challenged. Verify these against the primary documents.

I'll start by pulling together what the authoritative patent text shows and cross-checking the litigation and assignment records.

Now let me dig into the assignment record itself and confirm which IPR and litigation involve this specific patent.

Let me confirm the IPR patent mapping and try to surface the recorded assignment reel/frame and correspondent.

Assignment & Ownership Analysis — US 10,868,031 B2

Patent: Multiple-stack three-dimensional memory device and fabrication method thereof
App. 16/126,919 · Filed 2018-09-10 · Priority 2018-07-27 · Granted 2020-12-15
Assignee of record: Yangtze Memory Technologies Co., Ltd. (YMTC), Wuhan, Hubei, China
Anticipated expiration: 2038-07-27

Sourcing caveat (read first): The Assignment Center record itself (reel/frame and execution dates) is served by assignmentcenter.uspto.gov behind a search-by-patent-number query that I could not complete within the tool budget for this run. Everything below is grounded in (a) the authoritative Google Patents legal-events feed for US 10,868,031, which mirrors the USPTO assignment record, and (b) PTAB district-court and IPR filings. I have not invented any reel/frame numbers. Where the reel/frame or execution date is unavailable, I say so explicitly rather than guessing.

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Inventors

Ten named inventors, all of record as assignors on the same recorded conveyance, all listed at the same employer/address (Wuhan, Hubei, China) — i.e., all were YMTC employees at filing:

Pattern check — departures / fire-sale precursor: Not present. All ten inventors are named as assignors on a single inventor-to-employer assignment, and there is no recorded subsequent assignment executed by individual inventors (which is what a departing-inventor transfer would look like). Several of these inventors appear as inventors on later YMTC continuations in the same family (e.g., US 11,968,832 B2, granted 2024-04-23), which is consistent with continued employment rather than a 12-month departure cluster. No evidence of a fire-sale precursor.

Note on inventorship count: the Google Patents header lists the same ten individuals; the recorded assignor block lists the same ten names. No discrepancy, no omitted inventor.

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Original assignee

Yangtze Memory Technologies Co., Ltd. (YMTC) — a PRC NAND flash memory manufacturer headquartered at No. 88 Weilai 3rd Road, East Lake High-tech Development Zone, Wuhan, Hubei 430074, China.

• Primary line of business: 3D NAND flash memory design and fabrication (Xtacking architecture). Per TrendForce data cited in Sept-2026 reporting, YMTC ranked #3 worldwide in NAND flash by both revenue and shipments in Q1 2026.
• Did they ship a product embodying the claims? Yes — this patent is asserted against 3D NAND products in the 96/128/176/232-layer classes, and YMTC's own accused-product dispute with Micron (see below) is undisputed as to YMTC being a NAND manufacturer. In this litigation the interesting wrinkle is the reverse direction: YMTC represented to the N.D. Cal. court that it was not selling the accused 3D NAND products in the United States (a point Micron later moved to reopen, Dkt. 213, filed 2025-01-29). That is a US-market-access issue (YMTC is on the BIS Entity List), not a "no products" finding.
• Current status: Operating. YMTC is the named plaintiff and patent owner in active, worldwide, multi-front litigation against Micron; it is not dissolved, in bankruptcy, or reconstituted as a licensing vehicle.

Note on related entity: the co-plaintiff/counter-defendant in the litigation is Yangtze Memory Technologies, Inc., a US subsidiary. Corporate-disclosure filings in the case identify the parent as Yangtze Memory Technologies Company, Ltd. The patent itself remains in the name of the parent — there is no recorded assignment to the US subsidiary.

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Assignment timeline

One recorded assignment exists. After that, the chain terminates at the original assignee. This is the expected shape for a vertically integrated manufacturer that has never divested the patent.

• Execution date: not stated in the sources available / recorded 2018-11-28 — Reel/Frame: not retrievable in this run (Assignment Center search-by-patent-number required for verification)
  • Conveyance: Assignment of Assignors' Interest (37 CFR 3.11 recordation of the original inventor→employer assignment)
  • Assignor: Huo, Zongliang; Liu, Jun; Hu, Yushi; Li, Sizhe; Li, Zhaosong; Lu, Zhenyu; Tang, Zhao Hui; Tao, Qian; Xiao, Li Hong; Zhou, Yu Ting (all ten named inventors)
  • Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD. (Wuhan, Hubei, China)
  • Correspondent: Not determinable from the sources available to me for this specific reel. For transparency (not as a finding on this reel): YMTC's US prosecution correspondents in this era include Bayes PLLC (1765 Greensboro Station Place, Suite 900, McLean, VA 22102 — Customer No. 153988; attorney Zhiwei Zou, Reg. No. 66,041, signed for YMTC on a sibling application in the same "10018" docket family) and Sterne Kessler Goldstein & Fox, PLLC (1100 New York Avenue NW, Washington, DC 20005 — correspondent on a different recorded YMTC assignment, reel 54571/941). I am not asserting either firm is the correspondent on the 2018-11-28 recording for the '031 patent; a single appearance is not a recurrence signal.
  • Context: Original inventor-to-employer assignment — routine, contemporaneous with filing. Not a reorg, not a securitization, not an asserter transfer.

No other post-issuance assignments are recorded. Confirming legal events on the patent show only continuation-family priority claims, not conveyances:

• 2020-10-16 — priority to US 17/072,958 → US 11,968,832 B2
• 2024-02-07 — priority to US 18/435,294 → US 12,575,105 B2
• 2025-05-19 — priority to US 19/212,180 → US 2025/0280538 A1

All continuation members remain in YMTC's name. Ownership is continuous and single-headed from 2018 to date.

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Timeline diagram

timeline
    title Ownership of US 10868031
    2018 : Inventors assign to YMTC
         : Application filed 10 Sep 2018
    2020 : Patent issued 15 Dec 2020
    2023 : YMTC sues Micron in N D Cal
    2024 : Micron petitions IPR 2024-00790
    2025 : PTAB final written decision

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NPE / troll-pattern signals

Litigation / validity context (drives the verdict)

• First assertion: Yangtze Memory Technologies Company, Ltd. v. Micron Technology, Inc. and Micron Consumer Products Group, LLC, No. 3:23-cv-05792-RFL (N.D. Cal., filed 2023-11-09), asserting eight patents including US 10,868,031 (Exhibit 8 to the complaint). Accused products: Micron 96L / 128L / 176L / 232L 3D NAND.
• Second wave: 2024-07-12, YMTC asserted eleven more patents against the same Micron 3D NAND products plus DDR5; consolidated into the same case 2024-08-21.
• PTAB: IPR2024-00790, Micron v. YMTC, US 10,868,031 B2 — filed 2024-04-18, instituted 2024-10-28, Final Written Decision 2025-10-23, with challenged claims 6–7, 10 and 20 at issue. Reported outcome is a split: challenged claims held unpatentable while other claims (reported as claims 4–5) survived; Director Review was denied (order covering IPR2024-00790 / -00792 / -00794, 2026-03-17), and appeals are pending at the Federal Circuit (docketed as 26-1336 and 26-1161, owner's notice of appeal 2025-11-05 and petitioner's protective cross-appeal 2025-12-26).
• Counter-assertion: Micron filed its own infringement counterclaims and, per Sept-2026 reporting, a separate trade-secret suit (D. Idaho). Munich I Regional Court granted YMTC injunctions on two German utility models on 2026-09-18 — note these are different IP rights (DE202020006166U1; DE202021004551U1), not the '031 US patent.

This is two-way, manufacturer-vs-manufacturer patent warfare across five-plus jurisdictions, not a monetization campaign.

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Verdict

Operating-company assertion.

Reasoning (2–3 sentences): The only recorded conveyance is the original inventor→employer assignment to Yangtze Memory Technologies Co., Ltd., recorded 2018-11-28 (execution date and reel/frame not confirmed in this run — verify at Assignment Center), with no post-issuance transfer to any party. The current assignee is a vertically integrated 3D NAND manufacturer that ships the technology and is suing a direct competitor, Micron, on its own patents in N.D. Cal. 3:23-cv-05792 (filed 2023-11-09); Micron's IPR2024-00790 over this very patent, and YMTC's parallel assertions in Texas, the UK, the UPC and Munich, confirm a genuine head-to-head competitive dispute rather than a licensing-shop monetization pattern. All eight classic NPE signals test not present except the recurrent-correspondent signal, which is unclear solely because a one-link chain cannot exhibit recurrence.

Verify the record here: https://assignmentcenter.uspto.gov/ (search patent number 10868031) · mirror at https://assignment.uspto.gov/patent/index.html

I'll research the prior-art citations for US 10,868,031. Let me run several searches.

Now let me get the specific citation lists and the IPR record.

Prior-Art Analysis — U.S. Patent No. 10,868,031 B2

0. Important scope caveat (read first)

You asked me to (a) pull the USPTO record for 10,868,031 and (b) walk through each patent citation appearing on that patent. I was able to do (a) and to identify and characterize the references that were actually litigated against this patent, but I was not able to retrieve the front-page "References Cited" (56) list of examiner-cited patents/applications, because the Google Patents / USPTO-adjacent text I could pull renders the full specification and classification tables but strips the citation tables. I will not invent that list. Section 2 states exactly what is missing and where to get it.

Also note a date conflict in my instructions: the session says the current date is 2026‑09‑25 while your prompt says 2026‑04‑26. Nothing in the analysis below turns on the difference, but flagging it since prior-art currency matters.

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1. Confirmed identification of the patent (exact number, no substitution)

Note: the number 10,868,031 is distinct from other YMTC patents that appear in the same litigation — e.g., 10,618,872; 10,658,378; 10,937,806; 10,950,623; 10,879,164; 10,879,254; 11,145,666; 11,468,957; 11,482,532; 11,501,822; 11,568,941; 11,581,322; 11,600,342; 12,010,838. Those are separate patents with separate prior-art records and are not treated here.

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2. What is missing: the examiner-cited (front-page) references

I could not extract the granted patent's "(56) References Cited" list. Consequences:

• I cannot tell you which patents/applications the Examiner cited during prosecution. Anything I listed there would be fabricated.
• Where to obtain it authoritatively: USPTO PatentCenter for application 16/126,919 (Patent Application Full Text / "References Cited"), or the granted patent PDF front page (patentimages.storage.googleapis.com/.../US10868031.pdf), or Espacenet/Global Dossier "Cited documents."
• What I can give you with grounding: (i) the admitted background art inside the '031 specification itself (§3A), and (ii) the references asserted and adjudicated by the PTAB in the IPR, which is the most probative, court-tested prior-art record for this patent (§3B–3C).

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3. Prior-art references I could verify

3A. Admitted background art in the '031 specification (Applicant Admitted Prior Art)

• Citation: U.S. 10,868,031 B2, col. 1 (Background), and the "Definitions/Description" passages reproduced on Google Patents, e.g. "To form this multiple-stack memory device, supporting pillars are used in the fabrication process to provide mechanical support and prevent pattern collapse."
• Date: Filed 2018-09-10; the admission speaks as of the 2018-07-27 priority date.
• Brief description: The specification expressly concedes that multiple-deck ("multiple-stack") 3D NAND with word-line stacks arranged perpendicular to the substrate, channel holes formed per stack, and supporting pillars used for mechanical support to prevent pattern collapse, were known. It further concedes that dual-deck fabrication conventionally used two separate staircase-forming patterning processes with separate photomasks.
• Claim relevance / §102: This is a §102(a)(1)/§102(b)-type admission, but as an admission it is not a single-reference anticipation of claims 1–8 by itself. It supplies the preamble environment (substrate, multiple-stack staircase structure, conductor/insulating layers, semiconductor channel, supporting pillar). It cannot anticipate the distinguishing limitations (unaligned vs. aligned sidewall surfaces; one-patterning staircase formation; pillar/support material specifics). Realistically it is §103 fodder, not §102.
• Caveat: Whether it is formally "prior art" depends on the priority date (2018-07-27) and whether the cited practice is the inventors' own work within the grace period — please verify against the file history.

3B. Kim — U.S. Patent No. 10,381,369 B2 (Samsung Electronics)

• Full citation: U.S. Patent No. 10,381,369 B2, Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures, inventors Joongshik Shin, Hongsoo Kim, Hyunmog Park; assignee Samsung Electronics Co., Ltd.
• Dates: Application No. 15/841,644; filed 2017-12-14; granted 2019-08-13.
• Brief description: A 3D memory with a stack structure spanning a cell-array region and a connection region. A lower mold structure has lower channel holes filled with sacrificial material; an upper mold structure is formed over it; the upper and lower mold structures are patterned together in the connection region to form a single staircase structure; and dummy holes are formed through the staircase structure. Critically for the '031 claims:
  • The vertical channel structure that penetrates the joined upper+lower structures has a side wall with a stepped (non-planar) profile at the level where the upper structure meets the lower structure / etch-stop layer.
  • The vertical dummy structure penetrating the staircase has a side wall with a planar profile at that same level.
  • Kim also describes an etch-stop layer between lower and upper structures, sacrificial filling in the lower channel holes, and dummy structures in the connection region.
• §102 vs. §103 and which claims: This is the reference the PTAB relied on in IPR2024-00790, and the Board found claims 1–3 unpatentable as obvious (a §103 ground, not §102 anticipation). Mapping that emerges from the record:

• Claims 4–5: The Board did not invalidate claims 4–5. Based on the Patent Owner's arguments of record, the surviving subject matter is the differentiated pillar fill — i.e., the supporting pillar and the semiconductor channel being filled with different filling layers, and the pillar being filled with an insulating material plus a pillar-support material (e.g., copper, cobalt, nickel, aluminum) surrounded by the insulating material — versus Kim, whose dummy structures are dummy channel structures. I am inferring this claim mapping from the Patent Owner's Response excerpt; I have not read the verbatim text of claims 2–8 in the record I retrieved, so treat the specific claim-number assignment as provisional. (The '031 specification describes both variants — "same filling layers" and "different filling layers" — in consecutive paragraphs, so the claim numbering cannot be resolved from the specification summary alone.)
• §102 note: Because Kim's effective filing date (2017-12-14) precedes the '031 priority date (2018-07-27), Kim is available as prior art under §102(a)(2) (U.S. patent effectively filed earlier, naming another inventor). Its grant (2019-08-13) post-dates the '031 filing (2018-09-10), so whether its pre-grant publication (a 2018 application publication) also makes it §102(a)(1) art requires checking the publication date in PatentCenter. The PTAB treated Kim as prior art against the '031 claims.

3C. Tessariol — U.S. Patent Application Publication No. 2019/0081061 A1 (Micron)

• Full citation: U.S. Patent Application Publication No. 2019/0081061 A1 (Tessariol et al.), Micron Technology, Inc. — identified in the IPR record as Exhibit 1036 ("Tessariol").
• Publication date: 2019-03-14 (per the secondary report identifying this number as "Tessariol").
• Brief description (as characterized in the PTAB briefing): Micron's own 3D memory application describing dummy-structure openings and via openings both formed through the memory stack (e.g., its Fig. 9), which at least one panel characterized as disclosing two holes both formed through the stack rather than a through-array contact through the stack plus a peripheral contact outside the stack (¶ [0037] cited).
• §102 relevance to the '031 claims: None established. In IPR2024-00790 the Board credited only Kim with disclosing/dispensing with the subject matter of challenged claims 1–3; the reporting on the decision states Micron also asserted Tessariol but that it did not carry the claims, and Tessariol evidently failed to render claims 4–5 unpatentable as well. Note that Tessariol was decisive against a different YMTC patent, US 10,861,872 (claims 1–6, 11–13 held unpatentable relative to Tessariol).
• Important date caveat: A March 2019 publication post-dates both the '031 priority date (2018-07-27) and filing date (2018-09-10). For Tessariol to be prior art it must qualify via §102(a)(2) on its effective filing date (or via a provisional). I could not verify Tessariol's filing/provisional date from the sources retrieved — flag as unverified. I also could not independently verify the title and full inventorship of 2019/0081061.
• Do not confuse this with Tessariol's appearance in other YMTC IPRs (e.g., IPR2024-00789 against 10,618,872, and briefing in the 10,879,254/10,879,164 family), where its role and Exhibit number may differ.

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4. Bottom line on §102

• No reference on the record I could retrieve is a clean §102 anticipation of the '031 claims. The operative outcome is obviousness under §35 U.S.C. §103, not anticipation: PTAB Final Written Decision of 2025-10-23 in IPR2024-00790 held claims 1–3 unpatentable over Kim (US 10,381,369 B2) (with Micron's Tessariol asserted but not dispositive).
• Claims 4–5 survived ("部分支持"), and a Request for Director Review was denied (Paper 38, dated 2026-03-17), leaving the surviving claims as the live issue on appeal (CAFC 26-1161 / 26-1336 per the litigation data).
• If your objective is a full §102 chart against all front-page citations, the missing input is the (56) list from application 16/126,919. Provide that list (or the granted PDF front page) and I can complete a limitation-by-limitation §102 analysis against each cited reference in the same exact-number discipline used above.

Sources

• Google Patents, US10868031B2: https://patents.google.com/patent/US10868031B2
• Google Patents, US10381369B2 (Kim/Samsung): https://patents.google.com/patent/US10381369
• IPR2024-00790 docket (Micron v. YMTC), FWD 2025-10-23; Director Review denied 2026-03-17
• YMTC Patent Owner's Response extract, IPR2024-00790 (2025-01-21)
• Reporting on the FWD identifying "Kim = US 10,381,369" and "Tessariol = US 2019/0081061": https://news.qq.com/rain/a/20251025A049MK00
• Litigation context: N.D. Cal./D. Del. Case 3:23-cv-05792; YMTC press coverage listing 10,868,031 among the asserted patents.

I'll ground this analysis with a few targeted searches, then build the §103 framework on the prior-art record already established.

Obviousness Analysis — U.S. 10,868,031 B2 (35 U.S.C. § 103)

Cross-reference note: This builds on, and does not repeat, the Patent summary, Litigation summary, PTAB challenges, Assignment history, and Prior-art sections. I rely on the existing record for bibliographic data, the Kim (§3B) and Tessariol (§3C) characterizations, the IPR2024-00790 outcome (claims 1–3 unpatentable; claims 4–5 sustained), and the missed §3A admitted-background-art discussion.

New evidence added in this pass (not previously available to the earlier sections):

1. Verbatim claim 1 text — recovered from YMTC's Patent Owner Response in IPR2024-00790 (Paper 12, filed 2025‑01‑21). This upgrades the earlier "verbatim US claim text unverified" caveat. Claim 1 is quoted in full below.
2. Kim's disclosure language, confirmed from the US10381369 specification (Google Patents): the "stepped profile" channel sidewall and "planar profile" dummy-structure sidewall at the upper/lower interface, plus single-pass patterning of upper and lower mold structures in the connection region.
3. Independent confirmation that the '031 prosecution involved a restriction requirement requiring the applicant to elect either "a memory device" or "a method for forming a memory device" (PO Response, citing Ex. 1002 at 663–669), and that the applicant elected the device invention without traverse. This is a materially useful fact for the §103 analysis (see §2.4).

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0. Contradictions and gaps that must be flagged before relying on anything below

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1. Governing §103 framework

The Board in the parallel Micron/YMTC IPRs recited the standard framework verbatim (see IPR2024‑00794 institution decision, quoted in the record): a claim is unpatentable under §103 if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious at the time of invention to a POSITA — KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007) — resolved on the Graham v. John Deere factual predicates: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; and (4) objective evidence of non-obviousness.

Because the '031 has a 2018 priority date, the AIA §102/§103 regime applies (no pre-AIA §102(e)/(g) distinctions). The relevant availability provisions are therefore:

• §102(a)(1) — patented, described in a printed publication, or in public use/on sale before the effective filing date;
• §102(a)(2) — described in a U.S. patent, U.S. patent application publication, or WIPO publication effectively filed before the effective filing date (this is the provision that reaches references whose own publication post-dates the '031 but whose filing pre-dates it).

Effective filing date: 2018‑07‑27 (priority) / 2018‑09‑10 (actual filing). Every ground below must clear this date on the reference's side, not merely on its publication side.

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2. POSITA, prior-art window, and the claim that must be beaten

2.1 Level of ordinary skill (element 3)

Per the IPR record, the adopted POSITA is a person with a bachelor of science degree in electrical engineering (or a similar discipline) and 2–3 years of professional experience working with memory devices. I note for transparency that the identical-quotation source I retrieved is the '623-patent institution decision (IPR2024‑00794), not the '031 decision; the earlier PTAB section attributes the same definition to the '031 proceeding. Verify the '031 definition against the IPR2024‑00790 Institution Decision page 1 before relying on it. It is not outcome-determinative here — no proposed combination turns on a skill-level boundary — but it is the reference point for "reasonable expectation of success."

2.2 Relevant prior-art field

The field is multi-deck ("multi-stack") 3D NAND fabrication, and specifically: (i) forming staircases in a multi-deck stack, (ii) forming channel holes that span decks, and (iii) forming support/dummy pillars that prevent pattern collapse during high-aspect-ratio etches and during the sacrificial-nitride→metal word-line replacement. The '031 specification itself concedes all three as known (Prior-art §3A) — this materially narrows "the scope and content of the prior art" that the patentee can exclude.

2.3 The claim to be analyzed — verbatim claim 1

Recovered from PO Response Paper 12 (IPR2024‑00790), which reproduces the claim with element labels:

[1.pre] A memory device comprising:
[1.a] a substrate;
[1.b] a multiple-stack staircase structure comprising a plurality of staircase structures stacked over the substrate,
[1.c] wherein each of the plurality of staircase structures comprises a plurality of conductor layers, wherein each of the plurality of conductor layers is located between two insulating layers;
[1.d] a filling structure surrounding the multiple-stack staircase structure;
[1.e] a semiconductor channel extending through the multiple-stack staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces; and
[1.f] a supporting pillar extending through at least one of the multiple-stack staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

This confirms the earlier reconstruction: claim 1 is a purely structural claim. No step of making appears in the claim. That is the single most important fact for the §103 case, because it removes the product-by-process argument that would otherwise muddy the analysis (and confirms that the AU claim's "wherein the semiconductor channel is formed by…" clause has no US counterpart in claim 1 — resolving prior-art §3's open question in the negative, at least for claim 1).

2.4 Two claim-construction linchpins (these decide the case)

(a) "Multiple-stack staircase structure" = the multi-deck stack as a whole, or only the stepped region?
The '031 specification says "multiple-stack staircase structure" is "interchangeable with 'staircase structure'" and that the "staircase structure" is formed "in core region 310" (FIG. 3 discussion). If the term is construed as the full multi-deck stack spanning the core array + step region, then a channel in the array region and a pillar in the step region both "extend through the multiple-stack staircase structure," and Kim maps directly. If it is construed narrowly as only the stepped/retro-stepped region, then Kim's array-region channel does not extend through Kim's connection-region staircase, and claim 1 is harder to reach. This is the hinge. It is also exactly the kind of term the Federal Circuit appeal (CAFC 26‑1161 / 26‑1336) may reach.

(b) "Unaligned" / "aligned sidewall surfaces."
The specification supplies an express definition: "unaligned surfaces" = "inconsistent hole dimensions caused by etching holes with high aspect-ratio (e.g., greater than 4)" at an interface where two separately-etched sub-holes were adjoined; "aligned" = surfaces of a hole "formed without adjoining sub-pillar holes." Under Phillips, there is a strong argument these are relative structural terms defined by the fabrication history that produced them — which, for validity, is fine, because the claim is structural and the prior art structure either has the geometry or it does not.

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3. The primary mapping: Kim (US 10,381,369 B2) against claim 1

Kim was already identified in Prior-art §3B as the reference the Board credited against claims 1–3. The searches in this pass confirm Kim's specification language word-for-word:

• "the upper and lower mold structures can be patterned in the connection region to form a staircase structure and a plurality of dummy holes can be formed to vertically penetrate through the staircase structure";
• "a vertical channel structure … can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure"; and
• "a vertical dummy structure can vertically penetrate through the staircase structure, where the vertical dummy structure having a side wall with a planar profile at a level … where the upper structure meets the lower structure."

3.1 Element-by-element table

Result: Kim discloses every element. That is why the Board reached unpatentability for claims 1–3, and why the §103 inquiry here is not really a "difference" question but an obviousness-as-a-design-choice question: Kim had already put the two structures — the stepped channel and the planar dummy — on the same die.

3.2 Why the stepped/planar geometry is the expected consequence, not an invention

This is the crux and it is worth stating plainly for any petition or invalidity contention:

1. A channel hole spanning two decks must be formed by etching a lower sub-hole, filling it with sacrificial material (so the upper deck can be deposited), then etching an upper sub-hole that adjoins the lower one, then removing the sacrificial fill. Two independent high-aspect-ratio etches → an inherent step/misalignment at the junction. That is the definition of "unaligned sidewall surfaces" in the '031 spec, and Kim's "stepped profile" is the identical artifact. A POSITA would expect it.
2. A support pillar need not span decks in the same way: it is a mechanical member, not an electrical one, and can be etched in a single pass through the already-assembled multi-deck stack. One etch → one continuous sidewall → "aligned sidewall surfaces." Kim's "planar profile" dummy is that structure.
3. Therefore, achieving "aligned pillar + unaligned channel" is a direct, predictable consequence of choosing to (i) abut per-deck sub-holes for the channel and (ii) single-pass etch the support hole. No new physics, no unexpected result.

KSR rationale engaged: (C) use of a known technique (single-pass support-hole etch) to improve a similar device (multi-deck stack) in the same way; and (A) combining prior-art elements (per-deck abutting channel + through-stack support hole) according to known methods to yield predictable results.

3.3 Anticipated PO rebuttals and responses

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4. Grounds of rejection — combinations and the motivation to combine

I set these out as candidate grounds with the specific motivation for each. Grounds A–C are directed at claims 1–3 (the FWD already proved A). Grounds D–E are aimed at the surviving claims 4–5, which are the commercially operative target.

Ground A — Kim alone, §103 (claims 1–3)

Motivation: not a combination at all; Kim's own specification describes the exact two-structure arrangement. This is the Board's finding and is the strongest available ground. Note: the Board framed it as obviousness rather than anticipation, so a petitioner is best served presenting it as §103 to mirror the FWD finding.

Ground B — AAP (the '031's own Background) + Kim, §103 (claims 1–3)

Motivation: the specification admits that multi-stack 3D NAND with per-stack channel holes and supporting pillars used to "provide mechanical support and prevent pattern collapse" was known (Prior-art §3A). The only thing left for the claim is the geometry of the sidewalls, which Kim supplies. This combination is useful defensively: it forecloses any argument that the "supporting pillar" concept itself was the point of novelty.

Ground C — Kim + Tessariol (US 2019/0081061 A1), §103 (claims 1–3, and the "filling structure" limitation)

Motivation: both are 3D NAND references from the same technical field addressing the same problem (forming through-stack openings while maintaining stack integrity); a POSITA seeking a robust "filling structure surrounding the staircase" disclosure would have looked to Tessariol's teaching of dummy-structure openings and via openings both formed through the memory stack (¶ [0037] relied on in the parallel briefing), which reinforces the 1.d element.

⚠️ Date gate for Tessariol — the highest-risk predicate in the whole analysis. US 2019/0081061 A1 published 2019‑03‑14, after both the '031 priority (2018‑07‑27) and filing (2018‑09‑10). It is prior art only under §102(a)(2), and only if its effective U.S. filing date pre-dates the '031's. An 18-month publication convention implies a filing around September 2017, which would qualify — but this is an inference from the publication date, not verified. The fact that the Board instituted on grounds using Tessariol (and invalidated a different YMTC patent, US 10,861,872, over it) is strong circumstantial evidence that it qualifies. Confirm Tessariol's 35 U.S.C. §102(d) effective filing date before relying on it. If Tessariol fails the date test, Ground C collapses and Ground A/B must carry claims 1–3 alone.

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Ground D — Kim + a support-pillar/dummy-pillar reference, §103 (the claim(s) reciting same filling layers)

If a dependent claim recites that the supporting pillar and the semiconductor channel comprise the same filling layers (a variant the '031 spec expressly describes — "these layers in pillar holes are referred to as dummy charge trapping films… dummy semiconductor channel films… dummy dielectric cores"), then the art is straightforward: the record already contains references teaching dummy pillars filled simultaneously with and from the same materials as the channel. Critically, the searches this pass surfaced a USPTO paper filed in the same campaign (a YMTC-targeting petition) quoting a 3D-memory reference at ¶ [0060]:

"In some embodiments, dummy channel structures … are formed simultaneously with channel structures … in the same fabrication steps, such that the opening of each dummy channel structure is filled with at least some of the materials filling in channel structures."

Motivation: process economy — filling the dummy and channel holes in one deposition sequence eliminates a photomask and a fill step, which is the express object of the '031 ("simplifying the fabrication process … reducing cost"). KSR rationale (C)/(D): applying a known technique (shared fill) to a known structure (multi-deck stack with support holes) to yield the predictable result of identical fill stacks.
Caveat: the excerpt above was retrieved from a petition document (PTACTs artifact) and I did not resolve the underlying reference's identity or its publication date. A petitioner must identify the primary document and clear the 2018‑07‑27 date gate. Do not cite it as-is.

Ground E — Kim + a "different-fill / metal-cored pillar" reference, §103 (claims 4–5 — the hard target)

This is where the money is, and I am deliberately blunt: Micron tried and failed on claims 4–5. The surviving subject matter, per the PO Response's own framing, is the differentiated pillar fill: "the supporting pillar and the semiconductor channel are filled with different filling layers … the supporting pillar is filled with 'at least one of an insulating material and a pillar-support material surrounded by the insulating material,' while the semiconductor channel is filled with 'at least one of a charge trapping film, a semiconductor channel film, and a dielectric core'," with the pillar-support material optionally "copper, cobalt, nickel, and aluminum."

Why the obviousness case is harder here: Kim's dummy structure is a dummy channel structure — same fill family as the channel. Nothing in Kim suggests substituting a stiff metal core for the channel fill. The commercial motivation (stiffness → less pattern collapse) is real but was not, on this record, in Kim.

What a new petitioner needs — two separate showings:

1. A pillar-vs-channel differential-fill reference. Candidates likely to qualify on date are SanDisk/Toshiba's "support pillar structure" family, which teaches support openings formed in separate processing steps from the memory openings and "filled with different materials using a different set of deposition steps," and support-pillar structures comprising a dummy memory film + dummy vertical semiconductor channel where the support pillar "lacks a semiconductor material portion which is in contact with the semiconductor material layer" (i.e., a structurally and materially distinct pillar). The applications I retrieved (US 2020/0303398 A1; US 2020/0403005 A1) publish in 2020 and therefore likely post-date the '031 priority — their earlier priority applications (or the equivalent Toshiba JP filings) must be located and date-checked.

2. A metal-in-high-aspect-ratio-hole reference (the Cu/Co/Ni/Al limitation). This is the easiest sub-limitation to meet and the hardest to make motivated. Metal liner/plug fill of high-aspect-ratio contacts was ubiquitous pre-2018 (Cu damascene liners; Co and Ni liners for contact/via fill; W/ALD-W in 3D NAND contacts). Motivation: the '031's own specification supplies it — a pillar-support material is chosen for "sufficient stiffness and/or support functions" to provide mechanical support. A POSITA seeking maximum stiffness-to-volume in a high-aspect-ratio pillar would select a metal with a refractory/high-modulus liner system; Cu, Co, Ni, Al are the enumerated standard BEOL metals. KSR rationale (E): "obvious to try" a finite, identified set of known metals to obtain the known benefit of stiffness.

Realistic assessment: Ground E is a conceivable but unproven ground. The prior-art section's conclusion stands — the surviving claims 4–5 must be attacked with art Micron did not deploy, and the burden is on identifying a pre-2018‑07‑27 reference that either (i) fills a support pillar with a metal, or (ii) teaches the reason to prefer a metal core over a channel-stack fill for a support pillar. I could not verify the existence of such a reference in this session and will not assert one.

Ground F — Kim + a multi-deck "connection-layer" reference, §103 (any double-channel dependent claim)

For any dependent claim reciting a connection layer in the semiconductor channel between two adjacent staircase structures (the "double channel" variant of FIG. 6; connection layer = doped semiconductor, portions of the channel on either side being sub-channels):

• What is needed: a reference teaching a doped/conductive plug or epitaxial junction joining two independently-formed sub-channels at a deck interface. The concept of a "junction"/"pedestal"/"connection" between deck channels is a standard multi-deck fabrication artifact (needed because a single continuous epitaxial channel across two decks is difficult), and the '031 itself frames it as a drain-region analogue ("Connection layers 606 can function as drain regions and can connect semiconductor sub-channels").
• Motivation: electrical continuity across decks. Without a connecting layer, the upper sub-channel is electrically floating — an inoperable device. A POSITA must provide a connection if it elects the double-deck, separately-filled channel route. That is a strong (D) "known device ready for improvement" rationale.
• Caveat: I did not locate and verify a specific pre-2018‑07‑27 reference in this session. Treat Ground F as a framework, not a chart.

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5. Motivation-to-combine — consolidated

Reasonable expectation of success: high for Grounds A–D (Kim actually practiced the geometry). Lower but arguable for E (metal-in-pillar is a process-integration risk — metal contamination into the array, thermal budget — counterarguments a POP could run).

Teaching away: I found none. Kim does not disparage through-stack dummy holes or planar-profile pillars; to the contrary, Kim teaches the planar-profile pillar as a feature of the connection region. The only "away" signal a POP might construct is that a metal pillar risks contamination — that is an argument for insulating-liner + metal, which is precisely the claim's own recited structure ("a pillar-support material surrounded by the insulating material").

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6. Objective indicia (§103 element 4)

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7. Bottom line — claim-by-claim

Synthesis: For the broadest, sole independent claim 1 and its immediate dependents 2–3, the §103 case is strong and already adjudicated — Kim is a single-reference, element-for-element disclosure of both sidewall geometries, with a corroborating admission of the remaining environment in the '031's own Background. The genuine §103 difficulty is confined to claims 4–5, where the differentiating feature is the material composition of the pillar rather than its geometry, and where the motivation must be built from the '031's own stiffness rationale plus a pre-July-2018 reference teaching a metal-cored, liner-isolated support pillar. I have not identified such a reference with confidence in this session and flag it as the required next research step.

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8. Practical consequences for a challenge (ties back to the PTAB and Litigation sections)

1. Micron is estopped (§315(e)(2)) from re-running its Kim/Tessariol §103 combinations in district court. Any new petitioner gets a clean slate against claims 1–6 / 1–5.
2. The efficient target is claims 4–5, and the efficient ground is a two-reference combination: Kim (for everything claim 1 requires — it is already Board-credited) + one new reference supplying the differentiated, liner-isolated metal support pillar. A single new reference is enough; you do not need to re-litigate claim 1's geometry.
3. Do not build a petition on the AAP alone — it supplies only the preamble environment and fails on 1.e/1.f.
4. Date-check Tessariol's effective filing date and any SanDisk/Toshiba support-pillar priority document before filing. Tessariol's entire availability rests on a §102(a)(2) inference from its 2019‑03‑14 publication date.

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9. Items I am explicitly not asserting

• The verbatim text of claims 2–6 (only claim 1 is verified).
• That Tessariol's effective filing date pre-dates 2018‑07‑27 (inference only).
• The identity and date of the reference containing the "dummy channel structures … formed simultaneously with channel structures" passage — quoted from a petition document, source unresolved.
• That any pre-July-2018 reference discloses a metal-cored support pillar in a 3D NAND stack (Ground E is a framework, not a finding).
• A pre-July-2018 reference for the connection-layer double-channel feature (Ground F).
• The '031's POSITA definition as stated in the '031 IPR itself (quoted from the '623 proceeding).
• The contradiction in §0/C1 (which reference was "primary") — I have not resolved it.

Sources relied on in this pass: PO Response, IPR2024‑00790 Paper 12 (2025‑01‑21), via https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2024-00790/…; Google Patents US10381369B2 (https://patents.google.com/patent/US10381369); PTACTs petition artifacts at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556953](/patent/1556953)/download-documents; SanDisk/Applied Materials support-pillar publications cited above; Order Denying Director Review, IPR2024‑00790/‑00792/‑00794 (2026‑03‑17).