US 12010838

I'll search for the requested patent and any CAFC 2026 docket activity.

The USPTO/PTAB search returned useful results but no CAFC docket. Let me run more targeted searches for Federal Circuit activity.

The searches confirm the patent's basic data and PTAB proceedings. Let me verify whether any CAFC 2026 appeal specifically involves this '838 patent.

US Patent 12,010,838 — Analyst Summary

I searched for patent number 12010838 specifically. I did not find (and am not reporting) results for similar numbers such as 12,108,600 (Lodestar/Micron staircase patent) or the related-family patents 10,680,003 / 11,145,666 / 12,137,558.

Confirmed bibliographic data (from USPTO-issued patent text via Docket Alarm Exhibit 1001 and Google Patents)

• Patent number: US 12,010,838 B2 (cited in PTAB papers as "the '838 patent")
• Title: Staircase Structure for Memory Device
• Assignee: Yangtze Memory Technologies Co., Ltd., Hubei (CN)
• Inventors (12): Zhenyu Lu; Jun Chen; Xiaowang Dai; Jifeng Zhu; Qian Tao; Yu Ru Huang; Si Ping Hu; Lan Yao; Li Hong Xiao; A Man Zheng; Kun Bao; Haohao Yang
• Application No. / Filing date: 17/447,456, filed September 13, 2021 (a continuation of US 16/885,858 → US 11,145,666, itself a continuation of US 16/126,956 → US 10,680,003; priority chain runs to PCT/CN2018/098962 (filed Aug. 6, 2018) and CN application 201710750398.4 (filed Aug. 28, 2017))
• Issue date: June 11, 2024
• Status: Active; adjusted expiration noted as 2039-04-20 (Google Patents), with a 257-day term adjustment noted on the patent face
• Law firm of record: Sterne, Kessler, Goldstein & Fox P.L.L.C.
• Abstract: "A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack."

Independent claims — plain-language overview

The issued patent has 20 claims; the independent claims are 1, 8, and 12 (all others are dependent).

• Claim 1 — A staircase structure of a memory device. The stepped word-line contact region ("staircase") has a first material layer (e.g., an insulating layer) sitting on only a first portion of a second material layer (e.g., a conductive layer) beneath it. A landing pad (word-line contact pad) sits on the second portion of the second material layer. The pad has two side surfaces: its first side surface contacts the first material layer, and its second side surface is laterally displaced (set back / inset) from the side surface of the underlying second portion. In short: a contact pad that abuts the adjacent insulating layer on one side and is inset from the edge of the conductive layer beneath it on the other side.

• Claim 8 — A memory device (with memory string + staircase). A memory device has a memory string (e.g., a vertical NAND string) over a substrate and a staircase structure adjacent to it. In the staircase, each step has a conductive layer with first and second portions; an insulating layer of a first thickness is disposed over the first portion; and a landing pad is disposed on the second portion, in contact with a side surface of the insulating layer, the pad having a second thickness greater than the first thickness (i.e., the landing pad is thicker than the adjacent insulating layer).

• Claim 12 — A memory device (structural version). A memory device comprising the same core structure as claim 1, framed at the device level: a first material layer disposed over a first portion of a second material layer, and a landing pad over the second portion, where the pad's first side surface contacts the first material layer and its second side surface is laterally displaced from the side surface of the second portion of the second material layer.

Technical gist: The invention is a 3D-NAND word-line "staircase" contact architecture in which each landing pad is inset relative to the underlying conductive layer and physically abuts the adjacent insulating layer, improving electrical-contact isolation/reliability for BEOL word-line fan-out.

CAFC 2026 docket check

• A direct search for a CAFC appeal tied to 12010838 in 2026 returned no results.
• The PTAB record for the '838 patent is: PGR2025-00021 (Micron Technology, Inc. v. Yangtze Memory Technologies Co., Ltd.) — petition filed Jan. 6, 2025, challenging claims 1, 3–7, and 12–20; per Unified Patents portal data it was instituted (pending) as of Sept. 3, 2025, with a Patent Owner response expert declaration entered Nov. 26, 2025. The parallel IPR2025-00229 was procedurally terminated June 12, 2025 (dismissed as premature under 35 U.S.C. § 311(c), in favor of the PGR).
• CAFC appeals I found involve related YMTC–Micron disputes but not the '838 patent itself: e.g., CAFC No. 26-1110 (appeal from PTAB IPR2024-00794 — a different patent) and CAFC No. 26-2127 (listed as appealing PTAB IPR2025-00189, which challenges US 11,145,666, the parent of the '838 patent — i.e., a related family member, not 12010838).

Uncertainty / caveats

• Several search results carry dates after the stated current date (e.g., a Justia entry dated June 15, 2026 for 26-1110; a CAFC case 26-2127 said to be filed Aug. 10, 2026). I cannot independently verify those future-dated entries and flag the discrepancy rather than rely on them.
• I could not confirm from the available sources whether the instituted PGR2025-00021 has produced a final written decision or any resulting CAFC appeal specifically for patent 12010838; no such CAFC docket appeared in my searches.

Key sources: USPTO patent text (Docket Alarm Ex. 1001 copy of US 12,010,838 B2); Google Patents (US12010838B2); PTAB papers PGR2025-00021 and IPR2025-00229 (Docket Alarm, Casemine, Unified Patents portal); Justia CAFC docket 26-1110.

Litigation Involving U.S. Patent 12,010,838 (US12010838B2)

Based on searches of PACER-derived dockets, PTAB records, and litigation databases (Unified Patents portal, CourtListener, PacerMonitor, DocketAlarm, Casemine), all identified litigation involving US 12,010,838 ("Staircase Structure for Memory Device," owned by Yangtze Memory Technologies Co., Ltd. / "YMTC") is between YMTC and Micron Technology. The matter is part of the broader YMTC v. Micron 3D NAND patent war. Details below.

A. District Court (Infringement Actions by YMTC Against Micron)

1. YMTC I — Yangtze Memory Technologies Company, Ltd. v. Micron Technology, Inc. and Micron Consumer Products Group, LLC

• Case No.: 3:23-cv-05792-RFL
• Jurisdiction: U.S. District Court, Northern District of California (San Francisco Division) — Note: Google Patents/Unified Patents labels this case as "California Eastern District Court," but PACER-based sources (PacerMonitor, Justia, CourtListener) confirm it is N.D. Cal., before Judge Rita F. Lin.
• Filed: November 9, 2023
• Parties: Plaintiff YMTC; Defendants Micron Technology, Inc. and Micron Consumer Products Group, LLC (Micron also asserted counterclaims against YMTC and Yangtze Memory Technologies, Inc.)
• Role of '838 patent: The original complaint asserted 8 earlier-issued patents (issued before the '838 patent's June 11, 2024 grant). The '838 patent entered the N.D. Cal. fight via the later-filed "YMTC II" action (below), which was consolidated into 3:23-cv-05792-RFL — docket entries reference "3:24-cv-04223-RFL which has been consolidated with Case No. 3:23-cv-05792-RFL."
• Current status: Pending (consolidated lead case before Judge Rita F. Lin). Recent docket activity includes an order denying a motion to partially lift a stay (Jan. 15, 2026), indicating the case is stayed in part, likely pending the PTAB post-grant proceedings on the '838 patent and related patents.

2. YMTC II — Yangtze Memory Technologies Company, Ltd. v. Micron Technology, Inc. and Micron Consumer Products Group, LLC

• Case Nos.: 5:24-cv-04223 (original docketing) and 3:24-cv-04223 (later docketing) — these appear to be the same case reflected under both N.D. Cal. division numbers (the complaint and summons carry the same filing-fee receipt number, ACANDC-19614572; CourtListener docket 68941809 is titled "3:24-cv-04223" while the summons references "5:24-cv-04223"). Unified Patents lists both numbers.
• Jurisdiction: U.S. District Court, Northern District of California (originally before Magistrate Judge Joseph C. Spero; reassigned to Judge Richard Seeborg, then related/consolidated into Judge Rita F. Lin's 3:23-cv-05792)
• Filed: July 12, 2024
• Parties: Plaintiff YMTC; Defendants Micron Technology, Inc. and Micron Consumer Products Group, LLC
• Role of '838 patent: This is the complaint that expressly asserts US 12,010,838. The complaint's patent analyses list "U.S. Patent No. 12,010,838 – Staircase Structure for Memory Device" (related to the '11,145,666 patent family), alleging infringement by Micron's 128L/176L (and other) 3D NAND products. Also asserts other patents including 10,672,711, 11,101,276, 11,568,941, 10,879,164, etc.
• Current status: Pending; consolidated with Case 3:23-cv-05792-RFL (N.D. Cal.), where the '838 patent remains at issue subject to the stay posture noted above.

B. PTAB Proceedings (Validity Challenges by Micron Against the '838 Patent)

3. PGR2025-00021 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

• Patent: US 12,010,838 B2 (claims 1, 3–7, 12–20 challenged)
• Filed: January 6, 2025 (post-grant review petition)
• Institution: Granted September 2–3, 2025 (Decision Granting Institution)
• Status: Pending – Instituted (as of the most recent PTAB docket records located). Trial has been active: Patent Owner's Response (Nov. 25, 2025), Petitioner's Reply (Feb. 17, 2026), Patent Owner's Sur-Reply (Mar. 31, 2026), Patent Owner's Request for Oral Argument (Apr. 21, 2026). Panel includes APJ Kimberly McGraw.
• Note: A Law360 headline dated June 9, 2026 ("PTAB Rules Micron Didn't Show Yangtze Patent Is Invalid") reports a PTAB final decision in YMTC's favor in this dispute; the snippet does not expressly confirm the '838 patent number, so I cannot state with certainty that it is the final decision in this specific PGR.

4. IPR2025-00229 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

• Patent: US 12,010,838 B2
• Filed: November 29, 2024 (IPR petition; same claims/grounds as the PGR)
• Status: Terminated (procedural) — June 12, 2025. The Board granted Micron's unopposed motion to terminate/dismiss (Paper 20) because the IPR petition was premature under 35 U.S.C. § 311(c) — it was filed less than 9 months after the June 11, 2024 grant of the '838 patent, while the parallel PGR2025-00021 was still pending. No institution decision; proceeding dismissed without prejudice; Micron obtained a refund of post-institution fees.

C. Notes on Data Artifacts / Corrections

• The Google Patents litigation panel attributes PGR2025-00021 and IPR2025-00229 to "Unified Patents PTAB Data" as "Petitioner." That is a data-source attribution artifact — the actual petitioner in both PTAB matters is Micron Technology, Inc.
• The Google Patents/Unified Patents portal labels for the district court entries (e.g., "California Eastern District Court" for 3:23-cv-05792) are inaccurate; PACER-derived dockets confirm all district-court matters above are in the Northern District of California.

Summary Table

If you need the specific '838-patent infringement contentions (which Micron products are accused under which claims) or the PGR grounds/prior art, I can pull those from the complaint and PGR petition exhibits next.

Proceedings overview

The USPTO Open Data Portal block in this prompt shows zero AIA trial proceedings for US 12010838, but web search independently surfaced two PTAB proceedings that the ODP has not yet indexed: PGR2025-00021 (Micron v. YMTC — post-grant review, instituted and still pending) and IPR2025-00229 (Micron v. YMTC — terminated pre-institution on procedural grounds). Net scorecard: 1 active trial, 1 procedurally terminated IPR, 0 claims invalidated, 0 claims sustained on the merits, 0 settlements, 0 institution denials. Bottom line for a defendant: the patent has not yet been tested on the merits — all 20 claims remain in full force, and the only live challenge (Micron's PGR) was instituted on 2025-09-02 with a Final Written Decision due on or about 2026-09-02, i.e., imminent as of today. This is not a "hardened" patent and not a "dead" patent — it is mid-flight, and the earlier IPR "loss" for Micron was a procedural dismissal for premature filing, not a merits win for YMTC.

Sources: PGR2025-00021 docket (ipverse/GreyB), IPR2025-00229 termination order (Casemine), Petition analysis — IPR2025-00229, Petition analysis — PGR2025-00021, Micron's Explanation of Multiple Petitions (DocketAlarm).

PGR2025-00021 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

• Type: Post-Grant Review (PGR)
• Filed: 2025-01-06 (petition; filed alongside Micron's "Explanation of Multiple Petitions," ranking this PGR ahead of its parallel IPR)
• Status: Trial Instituted / Pending (Google Patents metadata: "filed (Pending — Instituted)"). Plain English: the PGR is live; merits briefing is complete and a Final Written Decision is due imminently.
• Judge panel: Administrative Patent Judges Jo-Anne M. Kokoski, Kimberly McGraw, and Michael T. Cygan (same panel designated on the PGR's counsel-withdrawal orders and on the parallel IPR2025-00229).
• Petition grounds: All challenges are § 103 obviousness against claims 1, 3–7, and 12–20 (claims 2, 8, 9, 10, and 11 were not challenged), per Micron's own petition summary:
  • Ground 1: Claims 1, 4–7, 12–17, 19–20 obvious over Kim (US Patent 10,229,929);
  • Ground 2: Claims 3 and 18 obvious over Kim in view of Yang (US Patent 9,941,153);
  • Ground 3: Claims 1, 4–7, 12, 16–17, 19–20 obvious over Lee (US 2014/0191389);
  • Ground 4: Claims 3 and 18 obvious over Lee in view of Haller;
  • Ground 5: Claims 13 and 15 obvious over Lee in view of Park.
  • The petitions are not § 112 or § 102-anticipation-only challenges; Micron's expert is Dr. Jack C. Lee, with YMTC's expert being Dr. Konstantinos P. Giapis.
• Institution decision: Granted — "Decision Granting Institution of Post-Grant Review" entered 2025-09-02. Before the merits institution decision, YMTC sought discretionary denial (arguing Micron's "barrage of 26 petitions challenging 251 claims across 19 patents" was duplicative of the stayed N.D. Cal. litigation); the Director's office (Acting Deputy Chief APJ Kalyan K. Deshpande; Acting Under Secretary Coke Morgan Stewart recused) denied discretionary denial on 2025-06-24/25 and referred the petition to the panel, reasoning that the parallel district court case had been stayed and that "early challenges" to recently issued patents (issued 2021–2024) "favor robust, predictable patent rights and weigh against discretionary denial." I could not verify from the sources retrieved whether institution covered all 15 challenged claims or all 5 grounds — the subsequent full merits briefing (PO Response, Petitioner Reply, Sur-reply) confirms the trial is proceeding on the challenged claims.
• Final Written Decision: Not yet located. Merits briefing ran: Patent Owner's Response (2025-11-25, with the Giapis declaration), Petitioner's Reply (2026-02-17), Patent Owner's Sur-reply (2026-03-31), plus expert depositions and motions to seal through May 2026. Under 35 U.S.C. § 326(a)(11), the FWD is due one year from institution, i.e., on or about 2026-09-02 — due as of the date of this analysis (2026-09-03). The public docket sources reviewed (which run through ~May 2026) show no FWD yet; check PTAB E2E for a decision that may have just issued.
• Settlement / termination: None. This is a contested merits trial, not a settlement.
• Appeal: None possible yet — no FWD exists to appeal.
• Defensive value: For Micron (and privies), this PGR is the live threat to the patent; if the imminent FWD cancels claims 1, 3–7, and/or 12–20, the district court case (stayed since 2025-03-14) will be materially altered. For a new defendant not in privity with Micron, the PGR has no estoppel effect, but its grounds (Kim, Lee, and combinations) are now publicly mapped in expert declarations — a ready-made invalidity roadmap. Watch for the FWD — it is due now.

IPR2025-00229 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review (IPR)
• Filed: 2024-11-29 (petition filed; filing date accorded 2025-01-30 per Board notice)
• Status: Terminated — Procedural Termination (Google Patents metadata: "filed (Procedural Termination)"). Plain English: dismissed pre-institution at Micron's own request; no merits decision.
• Judge panel: APJs Jo-Anne M. Kokoski, Kimberly McGraw, and Michael T. Cygan; Judge McGraw authored the termination order.
• Petition grounds: Identical to the PGR — same claims (1, 3–7, 12–20) and same § 103 grounds over Kim, Kim + Yang, Lee, Lee + Haller, and Lee + Park. Micron filed it as an insurance policy in case its PGR was deemed time-barred, expressly stating both petitions "address the same set of claims" and "include the same grounds," and ranking the PGR first.
• Institution decision: Never reached. On 2025-06-12 the Board granted Micron's unopposed motion to terminate (Paper 20), holding the IPR petition was statutorily premature under 35 U.S.C. § 311(c) — the '838 patent issued 2024-06-11, and the petition was filed less than nine months later (before 2025-03-11), with no PGR yet instituted or terminated that would have opened the IPR window. The Board dismissed the petition (citing SharkNinja v. Dyson, IPR2023-01323, and v. Foundry LLC, IPR2024-00281) — without prejudice.
• Final Written Decision: None (terminated pre-institution).
• Settlement / termination: Not a settlement. Micron certified "there are no other agreements, oral or written, between the parties made in connection with, or in contemplation of, termination of the proceeding." Termination was solely to consolidate the challenge into the PGR.
• Appeal: None (no FWD; a pre-institution dismissal on § 311(c) grounds is not appealable by the petitioner as a merits determination).
• Defensive value: Zero precedential weight on validity — it is a procedural nullity. But it shows Micron's strategy: it intended to challenge every one of claims 1, 3–7, and 12–20 on the same five obviousness grounds now being litigated in the PGR. Any defendant can presume those grounds are Micron's strongest.

Strategic summary

Claim status — nothing has been canceled or sustained on the merits yet. US 12010838 has 20 claims. Micron challenged claims 1, 3–7, and 12–20 (15 claims) in both proceedings; claims 2, 8, 9, 10, and 11 (5 claims) have never been challenged and remain entirely untested. Because the PGR's FWD has not yet issued, all 20 claims are presently enforceable. If the imminent FWD is adverse to YMTC, the canceled set will most likely be drawn from claims 1, 3–7, and 12–20; claims 2 and 8–11 would survive regardless unless separately attacked.

Estoppel landscape. No § 315(e)(2) estoppel has yet attached because no FWD exists. Once the PGR FWD issues, Micron and its privies will be estopped in the stayed N.D. Cal. litigation (3:23-cv-05792-RFL / 3:24-cv-04223-RFL, consolidated and stayed 2025-03-14) from raising any ground Micron raised or reasonably could have raised in the PGR — meaning the Kim/Lee art and combinations, plus any other § 102/103 ground available during the PGR, will be off-limits to Micron in court. Critically, the PGR filing window closed on 2025-03-11 (nine months post-grant), and any new defendant is free to deploy the same Kim/Lee art in district court or via its own IPR (subject to the § 315(b) one-year bar measured from service of the complaint against that defendant). A defendant that is not Micron's privy loses nothing by the PGR; a defendant that is (e.g., a Micron customer sued on this patent) must track the FWD closely because estoppel will bind it.

Pattern signals. This is not an isolated dispute: YMTC sued Micron in the N.D. Cal. (case 3:23-cv-05792, filed 2023-11-09, plus a second action 3:24-cv-04223, consolidated 2024-08-21), and YMTC itself characterized Micron's response as a campaign of 26 petitions across 19 YMTC patents — with multiple companion Micron-v.-YMTC proceedings on other YMTC patents (e.g., IPR2025-00191 and IPR2025-00228 reached FWD; IPR2025-00244/00245/00294 were denied institution; all per IP-Verse's PTAB tracker). YMTC has also filed its own IPRs against Micron patents, and in January 2026 Director Squires vacated institution and denied two of those YMTC petitions on real-party-in-interest grounds tied to YMTC's state-owned parent — a dispute now on appeal to the Federal Circuit (docketed 2025-06-15). Notably, Unified Patents is not the petitioner here — the "Unified Patents" branding on the Google Patents litigation links is only the data aggregator; the actual petitioner in both proceedings is Micron. The absence of any third-party petitioner is itself a signal: in a high-stakes, geopolitically charged 3D-NAND fight, only Micron (the litigation adversary) has bothered to attack this particular patent.

Recommended next steps

1. Check PTAB E2E for the PGR2025-00021 Final Written Decision immediately — it is statutorily due on or about 2026-09-02 (one year from the 2025-09-02 institution decision), and today is 2026-09-03. The public dockets reviewed here stop at May 2026 and show no FWD; it may have issued within the last day or two. Link: PTAB E2E or the PGR2025-00021 docket.
2. If you are Micron or a Micron privy: the stayed N.D. Cal. case (3:23-cv-05792-RFL / 3:24-cv-04223-RFL) will lift when the PGR concludes; prepare for § 315(e)(2) estoppel to foreclose the Kim/Lee grounds in court, and review the FWD for the panel's claim-construction and motivation-to-combine reasoning the moment it drops.
3. If you are a new, unrelated defendant: you are not estopped. The PGR papers (Kim = US 10,229,929; Lee = US 2014/0191389; Yang = US 9,941,153, plus Haller/Park) are a fully mapped invalidity playbook with expert declarations already on the public record — pull Ex. 1003 (Dr. Lee's declaration) from the PGR and reuse the mappings in your own IPR petition or invalidity contentions, mindful of the § 315(b) one-year clock from service of any complaint against you.
4. Caveat on the record: the USPTO ODP has not yet indexed either proceeding, and no FWD text was locatable in the sources retrieved for this analysis. Before any pleading relies on the PGR's outcome, confirm the FWD's existence and claim-level disposition directly on PTAB E2E.

I'll research the assignment chain for US Patent 12010838. Let me start with the USPTO records and cross-reference sources.

The Google Patents legal-event data already shows a key record. Let me dig into the litigation and any other assignment records.

I have reached the tool-call limit, so I'll now consolidate the verified findings. One important caveat up front: my available sources (Google Patents legal-event feed, Unified Patents/PTAB portal, CourtListener, and press coverage) did not expose the raw USPTO Assignment Center reel/frame or correspondent-of-record fields for this patent. I have not fabricated those identifiers and flag each place where they remain unverified rather than guessing.

Inventors

All 12 named inventors, in the order listed on the assignment recorded against this application:

Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang

• Employer at time of filing: Yangtze Memory Technologies Co., Ltd. (YMTC), Wuhan, Hubei, China — the inventors' identities track YMTC's internal engineering teams (e.g., Jun Chen and Lan Yao are listed on YMTC-assigned patent portfolios; the recorded assignment transfers rights from these individuals directly to YMTC).
• Unusual departure pattern: none detected. No evidence in the available record that the inventors left YMTC around filing, and no fire-sale precursor is present. The inventors' assignment to YMTC is the conventional employer capture, recorded on the continuation filing date.

Original assignee

Yangtze Memory Technologies Co., Ltd. (a.k.a. Yangtze Memory Technologies Company, Ltd. / YMTC / 长江存储科技有限责任公司). It appears as the assignee on the issued patent and as plaintiff in the district-court actions.

• Product embodiment: Yes. YMTC is an integrated-device manufacturer of 3D NAND flash (its Xtacking-architecture products, including 128L/176L/232L generation NAND, SSDs, eMMC/UFS storage). The claimed staircase/word-line fan-out structures are core to the 3D NAND products YMTC ships.
• Line of business: design and manufacture of 3D NAND flash memory and storage solutions; China's leading 3D NAND maker (founded 2016, Wuhan).
• Current status: Operating. Per its Rule 7.1 disclosure in the Micron litigation, its corporate parent is Yangtze Memory Technologies Holding Co., Ltd. YMTC remains an active manufacturer and litigant (placed on the U.S. Entity List in Oct 2022, but continuing operations and asserting patents through at least 2025-2026).

Assignment timeline

The USPTO Assignment Center records were not directly retrievable in the search run, so I cannot cite reel/frame numbers or correspondents with confidence. What the available legal-event data shows:

• 2021-09-13 (recorded) — Reel/frame: not available in accessed sources (Google Patents legal-event entry; direct reel/frame not verified)
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)
  • Assignor: Hu Si Ping, Huang Yu Ru, Dai Xiaowang, Tao Qian, Chen Jun, Lu Zhenyu, Bao Kun, Xiao Li Hong, Yang Haohao, Yao Lan, Zheng A Man, Zhu Jifeng (the 12 inventors)
  • Assignee: Yangtze Memory Technologies Co., Ltd.
  • Correspondent: not available in accessed sources
  • Context: standard inventor-to-employer assignment recorded on the filing date of continuation application 17/447,456 (which issued as US 12010838).

Finding: no post-issuance assignment, no transfer to any LLC, no security agreement, and no chain of title beyond the original inventor-to-YMTC assignment appears in the accessed records. The absence of downstream transfers is itself the meaningful finding — the original operating assignee still owns the patent. Verification link: https://assignmentcenter.uspto.gov/ (search patent 12010838); patent-level legal events also mirrored at https://patents.google.com/patent/US12010838/en.

Timeline diagram

timeline
    title Ownership of US 12010838
    2017 : Priority filed in China
    2018 : PCT filed
         : First US application filed
    2020 : First family patent issued
    2021 : Continuation application filed
         : Inventors assign to YMTC
    2023 : YMTC sues Micron in California
    2024 : US12010838 issued
         : YMTC asserts patent against Micron
         : Micron files IPR challenge
    2025 : Micron files PGR challenge

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The patent has never left the operating manufacturer YMTC. No "IP Holdings / Licensing / Ventures" LLC appears anywhere in the chain.

2. Known asserter in the chain — not present. YMTC is not on the Acacia / Marathon / IV / Conversant / Spangenberg-type NPE lists. It is a semiconductor IDM. Although YMTC is a plaintiff in multiple cases (3:23-cv-05792 and 3:24-cv-04223, N.D. Cal.), it asserts its own manufacturing technology against its direct competitor Micron — the profile of an operating-company assertion, not a listed NPE.

3. Repeat correspondent across the chain — unclear. Correspondent names are not visible in the sources I could access (assignment reel/frame records were not retrievable). There is only one recorded assignment link, so a "recurring" correspondent pattern cannot exist on this patent's record; no NPE-list correspondent tie was identified.

4. Cascading transfers — not present. There is no chain of chained LLC transfers. The record shows a single inventor-to-company assignment.

5. Pre-litigation transfer — not present. The only recorded assignment (2021-09-13) predates the first YMTC v. Micron complaint (Nov 2023, case 3:23-cv-05792) and the second (July 2024, case 3:24-cv-04223, which asserts US 12010838) by 2-3 years. Nothing was transferred in the six months before suit to enable standing or venue.

6. Bankruptcy fire-sale — not present. No assignor in the chain has undergone a Chapter 7/11 patent sale; YMTC is not in bankruptcy.

7. Privateering — not present. YMTC is asserting its own patents in its own name against Micron, a direct 3D NAND and DRAM competitor, in what YMTC describes as defense of its Xtacking technology. There is no operating-company-behind-an-NPE structure and no SEC/coverage evidence of a privateering arrangement.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. YMTC remains the owner and is affirmatively asserting.

Verdict

Operating-company assertion.

The patent's chain of title is a single inventor-to-employer assignment (recorded 2021-09-13) ending at Yangtze Memory Technologies Co., Ltd., a functioning 3D NAND manufacturer that ships Xtacking-architecture products embodying the claimed staircase structures. YMTC is asserting this patent (among others) against Micron — a direct competitor — in N.D. California (3:24-cv-04223, filed 2024-07-12), which is the classic operating-company enforcement posture. No shell entities, no cascading transfers, no NPE-list participants, and no pre-suit assignment appear in the record, so none of the troll-pattern signals are present. Verification: USPTO Assignment Center search for 12010838 at https://assignmentcenter.uspto.gov/ (reel/frame and correspondent fields should be confirmed there directly, as they were not machine-readable in the sources accessed for this analysis).

I'll research US Patent 12010838 and its cited prior art. Let me run several searches.

The initial results show this patent is the subject of active PTAB challenges (PGR2025-00021 and IPR2025-00229). Now let me locate the actual "References Cited" (patent citations) listed on the face of US 12010838 and on Google Patents.

I've gathered what the search tools will allow. Before presenting the analysis, I need to flag one important limitation and one important clarification:

Limitation: I could not retrieve the official front-page "References Cited" list (examiner citations) for US 12010838 B2 from the USPTO/Google Patents within this session — the full patent text supplied in the prompt does not include that section, and targeted searches returned no page with the examiner's citation list. The best-verified prior-art record for this patent comes from the two active PTAB petitions (PGR2025-00021 and IPR2025-00229, Micron Technology Inc. v. Yangtze Memory Technologies Co., Ltd.), which identify the prior art Micron asserts is most relevant. I present that below with verification status noted for each field.

Clarification on § 102 vs. § 103: Every ground asserted in the retrieved PTAB record is framed under 35 U.S.C. § 103 (obviousness), not § 102 (anticipation). No pure § 102 anticipation ground appears in the record I could retrieve. Where a single reference (e.g., Kim or Lee) is asserted to disclose every claim element, it could potentially support a § 102 analysis, but the petitioners characterize even those as § 103 grounds. I flag this per reference below.

1. Patent under analysis (verified)

Status: Active. Also relevant: the prompt shows US 12010838 B2 is in litigation (N.D. Cal. 3:24-cv-04223 and 5:24-cv-04223; E.D. Cal. 3:23-cv-05792) and is the subject of PGR2025-00021 (pending–instituted) and IPR2025-00229 (procedural termination), both brought by Micron Technology, Inc. (https://portal.unifiedpatents.com/ptab/case/PGR2025-00021; https://portal.unifiedpatents.com/ptab/case/IPR2025-00229).

2. Claim map of the '838 patent (for reference mapping below)

• Claim 1 – Staircase structure: first material layer over a first portion of a second material layer; landing pad over a second portion; landing pad has first side surface in contact with the first material layer and a second side surface laterally displaced from a side surface of the second portion.
• Claims 2–7 – depend from claim 1: (2) dielectric layer contacting the landing pad's bottom/second side and the second-portion side; (3) lateral displacement of 10–300 nm; (4) conductive landing pad; (5) specific conductive materials (W, silicide, Ni, Ti, Pt, Al, TiN, TaN, WN); (6) second material layer over another first material layer with lateral displacement; (7) first/second conductive materials substantially the same.
• Claim 8 – Memory device: memory string + staircase; conductive layer first/second portions; insulating layer of first thickness over the first portion; landing pad on second portion, thicker than the insulating layer.
• Claims 9–11 – depend from claim 8.
• Claim 12 – Memory device claim tracking claim 1's structural language.
• Claims 13–20 – depend from claim 12: (13) curved first side surface; (14)–(15) lateral-distance relationships; (16) second material layer = tungsten and titanium nitride; (17) same conductive material; (18) 10–300 nm lateral distance; (19) silicon-oxide dielectric layer; (20) another first material layer lateral-displacement limitation.

3. Most relevant prior art — verified from the PTAB petitions (PGR2025-00021 / IPR2025-00229)

These are the references Micron designates as Ex. 1005–1009 in the petitions (verified via https://www.docketalarm.com/cases/PTAB/IPR2025-00229/.../Petition_as_filed and the PGR2025-00021 Ex. 1003 declaration).

3.1 Kim — U.S. Patent No. 10,229,929 (Ex. 1005)

• Citation: U.S. Patent No. 10,229,929 B2 (inventor surname "Kim"; asserted as Ex. 1005). (Publication/issue date not retrievable in this session — treat as unverified.)
• Description (from record): A 3D memory staircase/contact-pad reference. The PGR declaration maps Kim against claims 1, 4–7, 12–17 and 19–20 element-by-element ([1.Pre]–[1.B.2], [4], [5], [6]/[20], [7]/[17], [13], [14], [15], [16], [19]). The IPR petition cites Kim, 8:29–34 for the proposition that contact pads in such staircase structures can have a "curved surface," and refers to "stacked conductive layers (pad portions)."
• Asserted ground (verified): PGR Ground 1 — claims 1, 4–7, 12–17, and 19–20 "obvious over Kim"; also primary reference in Ground 2 (claims 3, 18, with Yang).
• § 102 assessment: Kim is the strongest single-reference candidate. If Kim indeed discloses every element of claims 1, 4–7, 12–17, 19–20 as arranged in the claims, it could potentially anticipate under § 102 — but the petition frames the challenge as § 103, and the PGR declaration maps each claim element to Kim plus reasoned obviousness. Whether Kim alone "describes" the claimed arrangement (anticipation) vs. renders it obvious depends on the intrinsic disclosure (e.g., whether Kim's disclosure of "curved" pads, lateral displacement, and the W/TiN conductive layers is explicit or inferential).

3.2 Lee — U.S. Patent Application Publication 2014/0191389 A1 (Ex. 1006)

• Citation: U.S. Patent Application Publication No. 2014/0191389 A1 (inventor surname "Lee"; published 2014, per the publication number). (Precise publication date unverified.)
• Description (from record): The IPR petition describes Lee as disclosing a device with "alternating conductive and insulating layers" (Lee [0021], [0010], [0041], [0046]) and a staircase with a pad portion "PAD" whose shape is controlled via an "ion implantation process" (Lee [0035], [0038]–[0041]); the PGR petition cites Lee [0049] re "stacked conductive layers (pad portions)."
• Asserted grounds (verified): PGR Ground 3 — claims 1, 4–7, 12, 16–17, and 19–20 obvious over Lee alone; claims 3 and 18 obvious over Lee + Haller; claims 13–15 obvious over Lee + Park.
• § 102 assessment: Lee is the second strong single-reference candidate (for the subset of claims Micron mapped to Lee alone: 1, 4–7, 12, 16–17, 19–20). Potential § 102 anticipation would require Lee's publication to predate 2017-08-28 (it does, being a 2014 publication) and to disclose each limitation explicitly. Claims 3/18 and 13–15 are combination grounds (Lee + Haller; Lee + Park), so those are not pure § 102 candidates against Lee.

3.3 Yang — U.S. Patent No. 9,941,153 (Ex. 1007)

• Citation: U.S. Patent No. 9,941,153 B2 (inventor surname "Yang"; asserted as Ex. 1007). (Issue date unverified in this session.)
• Description (from record): Used as a secondary reference in PGR Ground 2 to supply the missing 10–300 nm lateral-dimension limitation of claims 3 and 18 in combination with Kim. The IPR petition likewise cites Yang (Ex. 1007) for the dimension/configuration teaching.
• Asserted ground (verified): Claims 3 and 18 obvious over Kim + Yang.
• § 102 assessment: Not a standalone § 102 candidate on the retrieved record — it supplies a limitation missing from Kim, i.e., a classic § 103 combination.

3.4 Haller — U.S. Patent No. 9,520,402 (Ex. 1008)

• Citation: U.S. Patent No. 9,520,402 B2 (inventor surname "Haller"; asserted as Ex. 1008). (Issue date unverified in this session.)
• Description (from record): The ex-parte case summary states claims 3 and 18 are challenged as obvious over "Lee and Haller (providing specific dimensions for Lee's barrier layer)" — i.e., Haller supplies the claimed 10–300 nm lateral-distance range (claims 3 and 18) to Lee.
• Asserted ground (verified): Claims 3 and 18 obvious over Lee + Haller.
• § 102 assessment: Combination reference only; not a standalone § 102 candidate.

3.5 Park — U.S. Patent No. 10,297,543 (Ex. 1009)

• Citation: U.S. Patent No. 10,297,543 B2 (inventor surname "Park"; asserted as Ex. 1009). (Issue date unverified in this session.)
• Description (from record): Used to teach a "curved"/"rounded" landing-pad side surface (claims 13–15) to prevent short circuits. The petition cites Park 7:17–29 (ion implantation and oxidation to form a pad with "rounded" sides), Park 11:35–41, and Park Fig. 8. The PGR declaration maps Park against claim 13 ("curved side surface") and claims 14–15 (lateral-distance relationships).
• Asserted ground (verified): Claims 13–15 obvious over Lee + Park.
• § 102 assessment: Combination reference; not a standalone § 102 candidate on the retrieved record.

4. Other prior art mentioned in the proceedings (lower confidence)

The IPR/PGR papers also mention, for the proposition that curved/rounded or shadowed pads were known:

• Yun (cited as Ex. 1021 in one PGR document; e.g., "Yun, 8:33–40" re rounded side surfaces; "Yun, 9:41–65" re step-coverage) — exact publication number not verified in this session.
• "Nam" (cited e.g. at [0066], Figs. 30–39, re ion implantation to form "convex"/"bull nose" contact pads) — exact publication number not verified.
• Plummer (Ex. 2028) — the Silicon VLSI Technology textbook, used by the Patent Owner on the meaning of "poor step coverage," not asserted against the claims.

I could not verify the full bibliographic data (inventor given names, exact issue/publication dates, assignees) for Kim, Yang, Haller, Park, Yun, or Nam from the retrieved snippets. I am flagging these as unverified rather than guessing.

5. Documents in the patent family (NOT prior art, but often confused with citations)

Because US 12010838 B2 is a continuation, its family members appear in its bibliographic record and are sometimes mistaken for "citations":

• US 10,680,003 B2 (parent, issued 2020-06-09)
• US 11,145,666 B2 (parent, issued 2021-10-12)
• US 2019/0081070 A1 (family publication, 2019-03-14)
• WO 2019/042091 A1 (PCT publication)
• CN 107644876 B (Chinese priority application)
• TWI721303 B (Taiwan family member)
• Child continuations: US 12,137,558 B2 (US18/054,468) and US 2025/0031366 A1 (US18/907,135)

None of these is § 102/§ 103 prior art against the '838 patent; they share its priority date.

6. Bottom line

• The most relevant prior art identified on the verified record is, in order of asserted importance: Kim (US 10,229,929) and Lee (US 2014/0191389 A1) as single-reference bases, supplemented by Yang (US 9,941,153) and Haller (US 9,520,402) for the 10–300 nm range (claims 3/18), and Park (US 10,297,543) for the curved-pad limitations (claims 13–15).
• All asserted grounds in the PTAB record are § 103 obviousness grounds. No § 102 anticipation ground was identified in the retrievable record. The closest candidates for a potential § 102 analysis are Kim (claims 1, 4–7, 12–17, 19–20) and Lee (claims 1, 4–7, 12, 16–17, 19–20), since each is asserted alone.
• If you need the examiner's actual front-page "References Cited" list for the certificate of US 12010838 B2, I recommend pulling the PDF from USPTO Patent Center (application 17/447,456) or the "Patent Citations" tab on Google Patents (https://patents.google.com/patent/[US12010838B2](/patent/US12010838B2)/en) directly — that tab was not retrievable through my searches in this session.

Obviousness Analysis — U.S. Patent 12,010,838 B2 ("Staircase Structure for Memory Device")

1. Scope and posture

U.S. Patent 12,010,838 B2 (the "'838 patent") issued June 11, 2024 to Yangtze Memory Technologies Co., Ltd. (YMTC). It is the third continuation in a family tracing to CN Application 201710750398.4 (filed Aug. 28, 2017) via U.S. 16/126,956 (→ 10,680,003), U.S. 16/885,858 (→ 11,145,666), and U.S. 17/447,456. The independent claims (1, 8, 12) are directed to staircase structures/3D memory devices in which a landing pad sits on a second portion of a conductive layer, its first side surface contacts an adjacent insulating ("first material") layer, and its second side surface is laterally displaced from the side surface of the underlying second portion. Claim 8 adds that the landing pad is thicker than the insulating layer; claims 13–15 add a curved first side surface and specific lateral-distance relationships; claims 3 and 18 add a 10–300 nm lateral-displacement range.

The most relevant prior-art testing of this patent is already underway before the PTAB:

• PGR2025-00021 (Micron Technology, Inc. v. YMTC) — instituted and pending, challenging claims 1, 3–7 and 12–20 on five § 103 grounds.
• IPR2025-00229 (same parties, same grounds) — terminated as premature under 35 U.S.C. § 311(c) (granted motion, June 12, 2025), because it was filed less than nine months after grant.

Because the identical grounds are before the Board in PGR2025-00021, the combination analysis below tracks the asserted grounds, which are the strongest articulated § 103 case against the patent.

2. Legal framework

Obviousness under 35 U.S.C. § 103 is assessed under the Graham factors: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations. Under KSR, a combination of prior-art elements is obvious when a skilled artisan had reason to combine known elements with a reasonable expectation of success, and predictable variations of known designs can be obvious even without an explicit teaching, suggestion, or motivation to combine.

3. The prior-art references at issue

Primary references (asserted to each teach all elements of the independent claims):

• Kim (U.S. Patent 10,229,929) — "semiconductor memory devices having enhanced reliability." Kim discloses a 3D memory device with a cell array region (CAR) and adjacent contact region (CTR) having a stepwise "stacking structure SS" of alternating insulating layers 110 and gate electrodes 300. Each gate electrode ends in a pad unit PAD comprising a base pad PAD_B and a protrusion pad PAD_P. Kim expressly teaches that the protrusion pad may be "between and spaced apart from two edges of a surface of the base pad," i.e., inset from the edges of the underlying conductive pad. The protrusion pad is formed inside an opening 122_O in an auxiliary insulating layer 122 that is of the same material as insulating layers 110 and forms "one structure" with them. Notably, Kim was not cited or considered during prosecution — petitioner relied on this to defeat a § 325(d) discretionary-denial argument.
• Lee (U.S. Pub. 2014/0191389 A1) — 3D memory device with a staircase structure and "pad portions PAD" on the conductive layers. Lee teaches an optional barrier layer 28 at the end of each conductive step that remains in the final product, shortening the underlying conductive layer so the pad overhangs it — creating the claimed lateral displacement. Lee was not considered during prosecution of this patent either (it does not appear among the references of record on the face of the '838 patent).

Secondary references (supply missing limitations):

• Yang (U.S. Patent 9,941,153) — structurally analogous 3D memory device with inset landing pads; teaches pad setback/lateral displacement of about 20–190 nm (within the claimed 10–300 nm range).
• Haller (U.S. Patent 9,520,402) — provides specific dimensions applicable to a barrier-layer/pad geometry of the type taught by Lee.
• Park — teaches contact pads with curved/rounded side surfaces (e.g., a "raised pad portion" with "rounded" sides formed by ion implantation/oxidation) and explains that curved surfaces increase the minimum distance between a pad and adjacent conductive layers, reducing short-circuit risk. (Park was cited on the face of the '838 patent family; the petition's Ground 5 uses it for claims 13–15.)

References of record considered during prosecution (face of the patent and parent 11,145,666) include, among others: 9,006,884; 9,331,082; 9,343,452 (Yun); 9,375,540 (Hyun); 9,419,013; 9,478,487; 9,520,402 (Haller); 9,711,609 (Lim); 9,741,563; 9,941,153 (Yang); 10,002,880 (Nagashima); 10,395,982 (Nam); 10,403,641 (Kim et al.); and publications by Cho, Iino, Lee, Oh, Hong, Ishimura, Son, Park (2018/0166380), Chun, Yoo, Kim, and Terasawa. Kim (10,229,929) and Lee (2014/0191389) are not in that list, which is why the § 325(d) issue arose.

4. Ground-by-ground obviousness analysis

Ground 1 — Claims 1, 4–7, 12–17, and 19–20 obvious over Kim alone

Element-by-element:

• Preamble — "staircase structure of a memory device": Kim's stepwise stacking structure SS in the contact region is a staircase structure of a 3D memory device.
• [1.A]/[12.A] "first material layer … disposed over a first portion of the second material layer": Kim's alternating insulating layers 110 (e.g., silicon oxide) and gate electrodes 300 map to the first/second material layers. Petitioner's mapping treats insulating layer 110 together with the adjacent portion of auxiliary insulating layer 122 as the "first material layer" because Kim states the two are the same material and "form one structure," and 122 is part of the stacked staircase (it defines the opening in which the pad is formed and remains in the final device).
• [1.B]/[12.B] "landing pad disposed over a second portion of the second material layer": Kim's protrusion pad PAD_P sits on base pad PAD_B at the end of gate electrode 300.
• [1.B.1] "landing pad comprises a first side surface and a second side surface": Kim discloses PAD_P in an "island shape" or "rectangular parallelepiped shape," each having multiple side surfaces.
• [1.B.2] "first side surface is in contact with the first material layer and the second side surface is laterally displaced from a side surface of the second portion of the second material layer": PAD_P fills opening 122_O in auxiliary insulating layer 122, so its side surface contacts that insulating structure; Kim's teaching that PAD_P is "inside and spaced apart from the edges" of the base pad places PAD_P's opposite side surface inward from — i.e., laterally displaced from — the side surface of the underlying conductive pad/gate electrode. This is the core claim limitation, and it is disclosed expressly in Kim.
• Dependent claims: claim 4/5 (conductive pad materials — tungsten, silicide, TiN, TaN, WN, etc.) are conventional gate/pad metals Kim describes; claim 7/17 (pad and conductive layer of substantially the same conductive material) matches Kim forming both the gate electrodes and pads in the same conductor-fill step; claim 6/20 (the second material layer of one level over another first material layer, with the next level's insulating side surface displaced from the pad's second side surface) is the ordinary alternating-staircase geometry of Kim's Figures 4B/13–16; claim 16 (tungsten + TiN) is a conventional word-line stack disclosed in the art; claim 19 (overlying dielectric of the same material as the insulating layer, e.g., silicon oxide) matches Kim's insulating/ILD materials.

Why a POSITA would find this obvious: Kim is a single reference that the petitioner maps to every claim element; no combination is needed. Under § 103 a single reference can render a claim obvious where the differences are only design choices or inherent properties (here, the inset-pad geometry is expressly described). A POSITA seeking to make electrical contact to word lines of a 3D NAND staircase would have had a reasonable expectation of success in adopting Kim's inset protrusion pad because Kim already demonstrates the structure and its reliability benefit (protecting the pad edge from etch damage/shorts).

Ground 2 — Claims 3 and 18 obvious over Kim in view of Yang

• Limitation: "a lateral distance between the second side surface and the side surface of the second portion of the second material layer is between 10 nm and 300 nm."
• Kim's gap: Kim teaches the inset geometry but not specific dimensions.
• Yang's contribution: Yang discloses an analogous 3D memory device with inset landing pads and a pad setback/lateral displacement of about 20–190 nm — squarely within the claimed 10–300 nm window.

Motivation to combine: Both references address the same manufacturing problem — avoiding over-etching and electrical failures at the landing-pad/word-line boundary in 3D NAND staircase structures. A POSITA implementing Kim's design would look to Yang for conventional, proven dimensions for the pad setback because the structures are architecturally analogous. Selecting a numerical setback within the claimed range from Yang's disclosed 20–190 nm would be a routine, predictable design optimization, not an inventive step — the classic KSR "obvious to try" / predictable-variation scenario. Expectation of success is high because Yang's dimensions are already demonstrated in the same type of device.

Ground 3 — Claims 1, 4–7, 12, 16–17, and 19–20 obvious over Lee alone

• Lee discloses a 3D memory device with a staircase structure, alternating insulating and conductive layers, and pad portions PAD on the conductive layers — mapping to the "first/second material layer" and "landing pad" elements.
• The disputed element is again the lateral displacement ([1.B.2]). In Lee's base embodiment the pad is aligned with the underlying conductive layer, but Lee expressly teaches an optional modification: forming a barrier layer 28 at the end of each conductive step. Because the barrier layer remains in the final product and shortens the conductive layer, the overlying pad overhangs it — i.e., the pad's second side surface is laterally displaced (outward) from the side surface of the conductive portion beneath it, exactly as claim 1/12 requires.

Motivation: The motivation is internal to Lee: Lee says the barrier-layer modification is used to "ensure sufficient distance" between vertically stacked conductive layers and prevent electrical breakdown. A POSITA reading Lee would be directed to that embodiment for exactly the reliability purpose the '838 patent credits to its own displaced-pad geometry. Because the reference itself supplies the reason to modify, the "combination" is really just following Lee's own teaching — no hindsight reconstruction is needed.

Ground 4 — Claims 3 and 18 obvious over Lee in view of Haller

• As with Kim/Yang, Lee teaches the displaced-pad structure created by barrier layer 28 but does not quantify the displacement.
• Haller supplies conventional dimensions for the pad/barrier geometry, providing the 10–300 nm lateral-displacement range (or a sub-range within it).

Motivation to combine: Lee teaches the structure and the problem (breakdown-voltage margin); Haller teaches the routine dimensional envelope for such barrier/pad structures. A POSITA combining them would do no more than size a known structural feature using known values to achieve a known benefit — precisely the kind of "ordinary innovation" that § 103 and KSR treat as unpatentable.

Ground 5 — Claims 13–15 obvious over Lee in view of Park

• Claim 13 adds: "the first side surface comprises a curved side surface."
• Claims 14–15 add lateral-distance relationships between the curved first side surface, the straight second side surface, and adjacent layer side surfaces (e.g., the first side surface is closer than the second side surface to the adjacent level's side surface).

Kim/other art already suggests curvature (relevant background): Kim itself states its protrusion pad may have a shape including a "curved surface based on a virtual rectangular parallelepiped shape," and cylindrical/island pad shapes with curved sides are disclosed in the art (e.g., Yun, Nam).

Why Lee + Park: For a POSITA implementing Lee's pad (or Kim's pad), substituting a curved side surface for the straight side of the pad that contacts the insulating layer would have been an obvious design choice. Park teaches contact pads with curved/rounded sides and explains the functional benefit: a curved surface increases the minimum distance between the pad and adjacent conductive layers, reducing the risk of short circuit (Park, 11:35–41). Park also shows such rounded pads can be made by ion implantation/oxidation — a process fully compatible with Lee's and Kim's fabrication flows.

Motivation to combine: The combination solves a known problem (pad-to-adjacent-word-line shorting) with a known solution (curved/rounded pad profile) already used in staircase-type 3D memories. The resulting claims 14–15 geometry — where the curved side sits closer to the neighboring layer than the outer side — is an inherent consequence of forming an inset pad with one curved and one straight side, i.e., an obvious arrangement rather than a patentable distinction. Expectation of success is high because curved pads had already been successfully integrated in analogous devices (Park, Yun, Nam) and because Kim itself lists a curved surface as an acceptable pad shape.

5. Patent Owner's principal counter-arguments (for balance)

The PGR is pending, and YMTC's responses (Preliminary Response; Patent Owner's Response supported by Dr. Konstantinos Giapis, Nov. 26, 2025) dispute the mapping, chiefly on the ground that:

• In Kim, the protrusion pad PAD_P sits inside an opening of auxiliary insulating layer 122, so its side surface contacts an overlying/auxiliary insulating structure rather than the laterally adjacent "first material layer" of the alternating stack in the precise vertical relationship claimed; and Kim allegedly does not show the second side surface of the pad displaced from the side surface of the "second portion" of the underlying conductive layer in the claimed sense.
• In Lee, the pad is aligned with the conductive layer in the primary embodiment, and the barrier-layer embodiment is said to be a process artifact rather than the claimed final structure.
• YMTC argues Kim alone does not teach the "curved side surface" of claim 13.
• The Board has not yet issued a final written decision; institution was not a merits holding on these disputes.

6. Assessment

On the current record, the strongest § 103 case against the '838 patent is:

1. Kim alone (claims 1, 4–7, 12–17, 19–20) — a newly introduced reference not before the examiner that expressly teaches the inset, contact-pad-on-conductive-layer staircase geometry the independent claims capture;
2. Kim + Yang (claims 3, 18) — supplying the only missing numerical range from an analogous device;
3. Lee alone (claims 1, 4–7, 12, 16–17, 19–20) — with an internal motivation (breakdown-voltage margin) for the barrier-layer embodiment producing the displaced pad;
4. Lee + Haller (claims 3, 18) — conventional dimensioning; and
5. Lee + Park (claims 13–15) — a known curved-pad solution to a known shorting problem.

Each combination is a "combination of familiar elements according to known methods" that "yields predictable results" (KSR), and the motivations are grounded in express teachings of the references (Kim's inset pad; Lee's barrier layer; Park's curved pads; Yang's and Haller's dimensions). The practical significance of the analysis is underscored by the PTAB's institution of PGR2025-00021 on these identical grounds. The remaining dispute is essentially whether the claim language should be read narrowly enough to exclude Kim's and Lee's disclosed structures — a claim-construction contest that will be resolved in the pending trial, not a genuine question of whether the concept of a laterally displaced, side-contacting landing pad was inventive as of the August 2017 priority date.

Key sources: PGR2025-00021 petition and declaration of Dr. Jack C. Lee (DocketAlarm/PTACTS, Ex. 1003); PTAB papers in PGR2025-00021 (asserted-grounds table; PO Response, Nov. 26, 2025); IPR2025-00229 termination order (June 12, 2025); USPTO file-wrapper images of the '838 patent listing references cited (Ex. 1001); parent U.S. 11,145,666 reference list; Google Patents record for US12010838B2.