US RE38806

Search results for US RE38806

I searched for the specific reissue patent number USRE38806 (not similar numbers) and located both USPTO/PTAB records and a 2026 Federal Circuit decision directly addressing it. Key confirmation: Katana Silicon Technologies LLC v. Micron Technology, Inc., Nos. 2024-2100, 2024-2101, 2024-2103 (Fed. Cir. Apr. 21, 2026) — decided five days ago — affirms PTAB unpatentability findings for this exact patent (claims 1–33 of RE38,806).

Bibliographic data

Abstract (verbatim): "A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate."

Plain-language overview of the independent claims

The full claim set was not reproduced in the materials available to me (the claim text is cut off at claim 26), so I can state the independent claims with high confidence only as follows; claims 27–33 could not be fully verified.

• Claim 1 (stacked CSP, both chips mounted via back-side adhesion layers, wire-bonded): A chip-size-package, stacked-chip device with an insulating substrate whose wiring layer has electrode sections. A first chip carries a first adhesion layer on its back (non-circuit) surface and sits face-up on the wiring layer through that layer. A second chip carries a second adhesion layer on its back and is mounted on the circuit-formed front surface of the first chip through that layer. Both chips are wire-bonded to electrode sections and the whole assembly is resin-sealed. Core idea: adhesion layers are pre-applied to the wafer backs so adhesive does not overflow, letting bond wires attach close to chip edges (smaller package) and requiring only one alignment step when stacking.

• Claim 2 (same stack, first chip attached by paste): Same structure as claim 1, except the first chip is mounted on the wiring layer through a paste applied to its back, rather than through a pre-adhered first adhesion layer; the second chip still has the second adhesion layer on its back.

• Claim 3 (flip-chip bottom die + wire-bonded top die, back-to-back): The first chip has a circuit on its front and an adhesion layer on its back. It is bump-bonded face-down to the wiring layer through metal bumps. The second chip (circuitless back surface) is mounted on the back of the first chip through the adhesion layer — i.e., back-to-back. The second chip is wire-bonded to electrode sections; both chips and the wire are resin-sealed.

• Claim 23 (apparatus recited via wafer-level fabrication of both chips): The substrate has a wiring layer (with electrode sections) on its front and packaging-use external terminals on its back, electrically connected through via holes. The first chip is defined by forming a first adhesion layer on a wafer back and dicing; it is mounted on the substrate through that layer. The second chip is likewise formed (second adhesion layer on a wafer back, then dicing) and mounted on the first chip's circuit-formed surface. Both are wire-bonded to electrode sections and resin-sealed.

• Claim 24 (same, first chip attached by insulating paste): Like claim 23, but the first chip is mounted through an insulating paste rather than an adhesion layer formed on the wafer; the second chip is made with a second insulating adhesion layer applied at wafer stage.

• Claim 30 (independent method claim, per the CAFC opinion): A manufacturing method requiring, in substance: forming a first insulating adhesion layer on the back of a first wafer (circuit on front); dicing into first chips; mounting the first chip on the wiring layer back-side down; forming a second insulating adhesion layer on the back of a second wafer; dicing into second chips; mounting the second chip on the first chip back-side down; wire-bonding each chip to electrode sections of the wiring layer; and sealing with resin. The CAFC noted this claim uses "forming" language and does not exclude adhesion layers made from an adhesive/glue/paste that is later cured (the dispositive construction issue on appeal).

Litigation/PTAB status (2026 CAFC docket)

• PTAB: Micron Technology, Inc. filed three inter partes review petitions (IPR2023-00071, -00072, -00073, filed Oct. 28, 2022) challenging RE38,806 and U.S. Patent No. 6,352,879. The Board instituted review May 15, 2023 and issued Final Written Decisions May 13, 2024, holding all challenged claims — claims 1–33 of RE38,806 and claims 1–15 of the '879 patent — unpatentable as obvious under 35 U.S.C. § 103, primarily over WO 96/13066 (Mostafazadeh) in combination with other references. Katana appealed (Notice of Appeal July 12, 2024).
• CAFC 2026: In Katana Silicon Technologies LLC v. Micron Technology, Inc., Nos. 2024-2100, 2024-2101, 2024-2103 (Fed. Cir., decided April 21, 2026, nonprecedential; panel: Taranto, Clevenger, Stoll; opinion by Stoll), the court affirmed the Board. The sole dispute was claim construction of "adhesion layer": Katana argued it means "a pre-formed layer that is adhered" (e.g., a solid thermo-compression sheet); the Board and Federal Circuit adopted Micron's construction — "a layer that adheres" — finding no lexicography or disclaimer in the specification requiring a pre-formed solid sheet. Under that construction, the obviousness holding was affirmed.
• Related district-court litigation: Katana asserted RE38,806 (with related patents 6,352,879, 6,731,013, 6,100,594, and 6,229,217) against Micron in W.D. Tex. (1:22-cv-00214), later transferred to D. Idaho; related CAFC appeals (Nos. 23-2007, 23-2095) concerned an $8M bond issue under Idaho's bad-faith-assertion statute and were dismissed for lack of jurisdiction (Dec. 2025 per one report).

Sources

• Google Patents bibliographic record: https://patents.google.com/patent/USRE38806/en
• CAFC opinion (April 21, 2026): https://www.courtlistener.com/opinion/[10846083](/patent/10846083)/katana-silicon-technologies-llc-v-micron-technology-inc/
• PTAB dockets: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2023-00071 ; RPX/IPR2023-00072
• Summary: https://www.vitallaw.com/news/patent-fed-cir-ptab-s-findings-of-unpatentability-for-miniaturized-semiconductor-patents-affirmed/…

Uncertainty notes: (1) The priority date appears as 1998-01-14 on Google Patents but 1998-01-13 in some databases; I could not independently resolve the underlying JP filing date. (2) The full text of claims 27–33 was not available in the provided patent extract, so I could not confirm whether any additional independent claims exist beyond 1, 2, 3, 23, 24, and 30. (3) The 6,100,594 grant date is reported variously as Aug. 7 or Aug. 8, 2000.

Based on my searches, US Patent RE38,806 ("Semiconductor device and method of manufacturing the same") has been involved in known litigation, primarily brought by its current owner Katana Silicon Technologies LLC (a patent monetization entity; formerly assigned from Sharp Corp.). Below is what I can confirm from the search results, with source citations.

District Court Infringement Actions

1. Katana Silicon Technologies LLC v. Western Digital Technologies, Inc.

• Plaintiff: Katana Silicon Technologies LLC
• Defendant: Western Digital Technologies, Inc.
• Jurisdiction: U.S. District Court for the Western District of Texas, Waco Division
• Case No.: 6:21-cv-00374
• Filing date: April 19, 2021
• Patents asserted: RE38,806 (the "'806 Patent"), U.S. 6,352,879, and U.S. 6,181,002
• Status: Active through at least late 2021/2022 (complaint, amended complaint, answers, claim construction briefing, and protective-order activity appear on the docket). I could not confirm a final judgment or disposition from the search results.
• Sources: CourtListener docket (https://www.courtlistener.com/docket/59833540/katana-silicon-technologies-llc-v-western-digital-technologies-inc/); original complaint PDF (https://storage.courtlistener.com/recap/gov.uscourts.txwd.[1130810](/patent/1130810)/gov.uscourts.txwd.1130810.1.0.pdf — expressly alleging infringement of RE38,806 at ¶¶ 23–25); IPR exhibit referencing "Katana Silicon Technologies LLC v. Western Digital Technologies (E.D. Tex. 2021)."

2. Katana Silicon Technologies LLC v. Micron Technology, Inc., et al.

• Plaintiff: Katana Silicon Technologies LLC
• Defendants: Micron Technology, Inc.; Micron Semiconductor Products, Inc.; Micron Technology Texas, LLC
• Jurisdiction: U.S. District Court for the Western District of Texas, Austin Division (Judge Lee Yeakel)
• Case No.: 1:22-cv-00214
• Filing date: March 4, 2022
• Patents asserted: RE38,806, U.S. 6,352,879, and U.S. 6,731,013 (IPWatchdog's roundup additionally lists family members U.S. 6,100,594 and 6,229,217 in connection with this filing)
• Status: Docket showed the case "Pending" as of May 2022 (answers due June 6, 2022). I could not confirm the final disposition from the search results. The closely related IPRs below (filed Oct. 2022 by Micron) would typically have led to a stay or termination.
• Sources: UniCourt (https://unicourt.com/case/pc-db5-katana-silicon-technologies-llc-v-micron-technology-inc-et-al-[1150598](/patent/1150598)); IPWatchdog (https://ipwatchdog.com/2022/03/17/patent-filings-roundup...); complaint (RPX Insight, https://insight.rpxcorp.com/litigation_documents/14647215).

PTAB Proceedings (Inter Partes Review)

3. Micron Technology, Inc. v. Katana Silicon Technologies LLC, IPR2023-00071

• Petitioner: Micron Technology, Inc.
• Patent Owner: Katana Silicon Technologies LLC
• Tribunal: PTAB (Tech Center 2800)
• Proceeding: IPR2023-00071 (challenging RE38,806)
• Petition filed: October 28, 2022
• Institution granted: May 15, 2023
• Final Written Decision: May 13, 2024 — all challenged claims held unpatentable as obvious (over WO 96/13066 "Mostafazadeh" in combination with other references)
• Status: Appealed by Patent Owner — Notice of Appeal filed July 12, 2024; PTAB status shown as "Final Written Decision – Appealed"
• Two companion proceedings, IPR2023-00072 and IPR2023-00073, were filed the same day against RE38,806 and/or the related U.S. 6,352,879 patent, and were heard/decided together (Final Written Decisions in all three affirmed on appeal).
• Sources: IPverse (https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2023-00071); RPX Empower (https://litigation.rpxcorp.com/ptab/15295-micron-technology-v-katana-silicon-technologies-llc-ipr-of-806).

Federal Circuit Appeal

4. Katana Silicon Technologies LLC v. Micron Technology, Inc., No. 24-2100 (Fed. Cir.)

• Appellants: Katana Silicon Technologies LLC
• Appellee: Micron Technology, Inc.
• Decision date: April 21, 2026 (nonprecedential)
• Outcome: Affirmed the PTAB's Final Written Decisions in IPR2023-00071 (and the two companion IPRs), sustaining the Board's construction of "adhesion layer" as "a layer that adheres" and the conclusion that the challenged claims of RE38,806 and 6,352,879 were obvious and unpatentable.
• Panel: Judge Stoll (authoring); attorneys of record included Howard Lithaw Lim (Carter Arnett PLLC) for Katana and Andrew Dufresne (Perkins Coie LLP) for Micron.
• Sources: Vital Law/IP Law Daily (https://www.vitallaw.com/news/patent-fed-cir-ptab-s-findings-of-unpatentability-for-miniaturized-semiconductor-patents-affirmed/...); CCH/CAFC opinion PDF (http://business.cch.com/ipld/KatanaSiliconTechnologiesMicronTechnologyFedCir20260421042126.pdf); CourtListener opinion (https://www.courtlistener.com/opinion/[10846083](/patent/10846083)/katana-silicon-technologies-llc-v-micron-technology-inc/).

Cautions and limitations

• I found no evidence of litigation against defendants other than Western Digital and Micron in these searches, but I could not exhaustively verify every case involving RE38,806 (e.g., through the Stanford NPE database, which does list RE38806 but whose case list I could not fully retrieve).
• Final dispositions of the two district court cases (W.D. Tex. 6:21-cv-00374 and 1:22-cv-00214) were not confirmed from the search results; given the 2024 IPR invalidation and the April 2026 Federal Circuit affirmance, those cases were likely stayed, dismissed, or resolved, but I do not have a reliable docket entry stating that.
• The patent's legal status is shown as Expired – Lifetime (anticipated expiration Dec. 30, 2018, based on the parent U.S. 6,100,594 family), which limits any ongoing enforcement.

Proceedings overview

Despite the USPTO ODP snapshot in this prompt showing "no AIA trial proceedings on file" (that ingest is clearly stale or incomplete), live records show two inter partes reviews were filed against RE38806 — IPR2023-00071 and IPR2023-00072 — both by Micron Technology, Inc. against patent owner Katana Silicon Technologies, LLC. Both were instituted, both ended in Final Written Decisions (2024-05-13) holding every challenged claim unpatentable, and the Federal Circuit affirmed both on 2026-04-21 (Nos. 2024-2100, 2024-2101, joined with 2024-2103 on the sibling '879 patent). Collectively, the two IPRs covered every claim of RE38806 except claim 29, meaning the patent has been effectively gutted: a defendant facing a demand letter today can answer that the asserted claims are canceled, the patent expired in 2018, and the patent owner lost on appeal.

IPR2023-00071 — Micron Technology, Inc. v. Katana Silicon Technologies, LLC

• Type: Inter Partes Review
• Filed: 2022-10-28
• Status: Terminated — Final Written Decision, appealed and affirmed (no settlement)
• Judge panel: Institution panel included APJ Elizabeth Roesel; after a Panel Change Order (2023-09-25), the FWD panel was APJs Minn Chung (lead author), Julia Heaney, and Sheldon M. McGee (per Patexia/IPR docket records).
• Petition grounds: § 103 obviousness over WO 96/13066 ("Mostafazadeh") in combination with other references (e.g., Ball, Fogal). Challenged claims: 3, 4, 5, 8, 11, 20, 21, 22, 27, 28, 31, and 33 of RE38806 (Patexia docket data).
• Institution decision: Granted 2023-05-15 — the Board found a reasonable likelihood Micron would prevail on at least one challenged claim.
• Final Written Decision (2024-05-13): The Board held all challenged claims (3, 4, 5, 8, 11, 20, 21, 22, 27, 28, 31, 33) unpatentable as obvious under § 103. The Board construed "adhesion layer" as "a layer that adheres" — rejecting Katana's proposed "a pre-formed layer that is adhered" (i.e., limited to a solid thermo-compression sheet) — reasoning that the claims and specification call for "forming" the adhesion layer on the wafer back surface and permit it to be "formed in situ," and that the specification's thermo-compression-sheet embodiments are not definitional. (Recorded in the FWD, Paper, 2024-05-13.)
• Settlement / termination: None — no settlement; the case ran to FWD.
• Appeal: Katana appealed (Notice of Appeal 2024-07-12). Federal Circuit docket No. 2024-2100, argued with 2024-2101/-2103. On 2026-04-21, the CAFC (Judge Stoll; nonprecedential) affirmed, holding that "the term 'adhesion layer' merely requires a layer that provides adhesion," with no lexicography or disavowal limiting it to a preformed sheet. Opinion: CAFC 24-2100 / CourtListener.
• Defensive value: These dependent claims are dead, confirmed by the Federal Circuit. No infringement theory built on them survives.

IPR2023-00072 — Micron Technology, Inc. v. Katana Silicon Technologies, LLC

• Type: Inter Partes Review
• Filed: 2022-10-28
• Status: Terminated — Final Written Decision, appealed and affirmed (no settlement)
• Judge panel: Same consolidated Micron v. Katana panel structure as IPR2023-00071; FWD panel of APJs Minn Chung, Julia Heaney, and Sheldon M. McGee after the 2023-09-25 panel change.
• Petition grounds: § 103 obviousness over Ball, Fogal, and Mostafazadeh (WO 96/13066), with other references. Challenged claims: 1, 2, 6, 7, 9, 10, 12–19, 23–26, 30, and 32 — i.e., the independent apparatus claims 1 and 2, the wafer-stage/dicing method claims (e.g., 23, 24, 30), and their dependents (per Katana's Notice of Appeal, which expressly lists these claims as held unpatentable).
• Institution decision: Granted 2023-05-15 (Paper 16) — reasonable likelihood on at least claim 1, 2, 6, 7, 9, 10, 12–19, 23–26, 30, or 32.
• Final Written Decision (2024-05-13, Paper 42): The Board held claims 1, 2, 6, 7, 9, 10, 12–19, 23–26, 30, and 32 unpatentable. As recorded in Katana's Notice of Appeal, the Board's unpatentability table includes claims 1, 2, 12, 13, 23, 24, and 30 under § 103(a) over Ball + Fogal + Mostafazadeh. The same "adhesion layer" = "a layer that adheres" construction drove the result. All independent claims of RE38806 were thereby canceled.
• Settlement / termination: None.
• Appeal: Katana appealed (Notice of Appeal 2024-07-12). Federal Circuit docket No. 2024-2101, consolidated with 2024-2100/-2103; affirmed 2026-04-21 (same opinion; the sole dispute was the "adhesion layer" construction, and the court agreed with the Board).
• Defensive value: This is the decisive proceeding — it killed the independent apparatus claims (1, 2) and the independent method/device claims (23, 24, 30). The core of the patent is gone.

Strategic summary

CANCELED vs. SUSTAINED vs. UNTESTED. Between IPR2023-00071 and IPR2023-00072, Micron challenged every claim of RE38806 except claim 29. The Board held all challenged claims unpatentable, and the Federal Circuit affirmed on 2026-04-21. That leaves, on the face of the patent, only claim 29 untested — a dependent claim whose parent (one of the canceled independent claims) no longer stands, and which therefore has no enforceable scope. The reissue certificate canceling claims 1–28 and 30–33 should already have issued or will issue following the affirmed FWDs. Independently of the IPRs, Google Patents records the patent as Expired – Lifetime (anticipated expiration 2018-12-30), so even the surviving claim 29 cannot reach post-expiry conduct, and pre-expiry damages are the only theoretical exposure. Related context: IPR2023-00073 (same parties, same day) challenged and killed all 15 claims of the sibling patent 6,352,879, which is why the CAFC disposed of all three appeals together.

Estoppel landscape. § 315(e)(2) estoppel binds Micron and its privies, but it is now academic — Micron won. A new defendant is not estopped by Micron's IPRs and could in theory raise any § 102/§ 103 ground (including Mostafazadeh-based combinations) in district court or a fresh petition. In practice there is little need: the asserted claims are canceled, and Katana is collaterally estopped from re-asserting claims it lost in IPR. Because the claims were invalidated on § 103 grounds, § 101/§ 112 defenses were never tested — but they are unnecessary given the cancellations. One caution: if Katana asserts claim 29 (the sole unchallenged claim) in litigation, its validity is untested by the PTAB, and a defendant would need its own § 102/§ 103 case (or a new IPR) — but the claim is dependent on canceled parents and the patent is expired, so any such assertion should be feeble.

Pattern signals. This is a classic NPE enforcement campaign: Katana Silicon Technologies LLC (which took the patent from Sharp Corp. in 2018) sued Micron in the W.D. Tex. in 2022 over RE38,806, 6,352,879, and 6,731,013, and had earlier litigated RE38,806 against Western Digital (E.D. Tex. 2021). Micron answered with three coordinated IPRs (2023-00071/-072/-073) and an Idaho Bad Faith Assertions of Patent Infringement Act counterclaim after transfer to D. Idaho; Katana is associated with Longhorn IP LLC, and the CAFC (in Micron v. Longhorn IP, 2025-12, Lourie/Schall/Stoll) dismissed Katana/Longhorn's interlocutory appeal of an $8M bond. The patent owner litigated the IPRs to the Federal Circuit and lost — the "adhesion layer" construction battle (preformed sheet vs. "a layer that adheres") is now adverse law against Katana in every forum.

Recommended next steps

1. If you are a defendant and the demand cites RE38806 claims 1–28 or 30–33: those claims are canceled. Point to the FWDs in IPR2023-00071 and IPR2023-00072 (both entered 2024-05-13) and the CAFC affirmance in Katana Silicon Technologies LLC v. Micron Technology, Inc., Nos. 2024-2100/-2101/-2103 (2026-04-21, nonprecedential, Judge Stoll) — CAFC opinion PDF and CourtListener. A continued infringement theory on those claims is sanction-bait.
2. Do not rely on the ODP "no proceedings" block — it contradicts the public PTAB docket. Pull the FWDs and the reissue certificate directly from PTAB E2E / USPTO Patent Center to confirm the exact canceled claim set before responding.
3. If claim 29 is cited (the only claim never challenged), your exposure is limited to pre-2018-12-30 conduct, the claim is dependent on canceled parents, and you remain free to raise § 102/§ 103 grounds (Mostafazadeh/Ball/Fogal combinations are proven winners) plus any § 112 issues — Micron's estoppel does not bind you.
4. No active PTAB milestones remain — all three proceedings are terminated, the statutory one-year trial clocks ran out long ago, and the CAFC has affirmed. Any further step would be a certiorari petition by Katana (unlikely and time-barred as of ~2026-07-20). The litigation tail is in D. Idaho on the Bad Faith Assertions Act counterclaims, not on claim validity.

Inventors

All four inventors are JP-resident Sharp engineers; the application was filed by Sharp Kabushiki Kaisha (per Espacenet: "Applicant(s): SHARP KK [JP]"). No unusual post-filing departure pattern is documented — I found no evidence any inventor left Sharp within 12 months of filing, and no inventor-level assignments to third parties. The relevant "departure" in this chain is corporate, not individual: Sharp's entire semiconductor patent portfolio left Sharp via the 2016 Foxconn acquisition and then a 2018 transfer to an NPE affiliate (below).

Original assignee

• Entity on the issued patent: Sharp Corporation (Sharp Kabushiki Kaisha), Osaka, Japan — shown as "Original Assignee" on Google Patents for RE38,806 and as applicant on Espacenet.
• Line of business / product: Sharp is/was a diversified electronics manufacturer (displays, solar, sensors, and historically its own semiconductor/LSI operations). Whether Sharp ever shipped a specific product embodying the CSP stacked-chip claims is unclear — the claims cover chip-size-package assembly technology, and no product-level evidence surfaced in my searches.
• Current status: Operating, but since August 2016 Sharp has been a subsidiary of Hon Hai / Foxconn Technology Group after Foxconn's acquisition of a controlling stake. This matters because the 2018 monetization of these patents was reported by IAM as a Foxconn-driven transfer of "former Sharp semiconductor patents."

Assignment timeline

Important caveat up front: I could not pull live reel/frame data from the USPTO Assignment Center (search limit reached), and the secondary sources do not print reel/frame numbers. The one recorded post-issuance assignment is corroborated by Google Patents' legal-event feed (reproduced in the authoritative patent text above): an "Assignment of Assignors Interest" recorded 2018-08-12, assignor Sharp Corporation, assignee Katana Silicon Technologies LLC. Reel/frame and the correspondent of record are not verified. I am flagging each entry's verification status rather than inventing details.

• (Executed ~1998–2000; recording unverified) — Original assignment, inventors → Sharp Corporation

  • Conveyance: original assignment from inventors to employer (presumed recorded at issuance of US 6,100,594; not independently verified)
  • Reel/frame: not retrieved | Correspondent: not retrieved
  • Context: standard employer assignment at prosecution

• Executed ~June 2018 / recorded 2018-08-12 — Reel/frame not retrieved (Google Patents legal event of 2018-08-12; IAM coverage dated 2018-06-19)

  • Conveyance: Assignment of Assignors' Interest ("SEE DOCUMENT FOR DETAILS" per Google Patents)
  • Assignor: Sharp Corporation (as recorded; note that by this date Sharp was Foxconn-controlled, and IAM described the commercial deal as Foxconn transferring former Sharp patents)
  • Assignee: Katana Silicon Technologies LLC
  • Correspondent: not retrieved
  • Context: transfer-to-asserter — portfolio sale into the Longhorn IP NPE family (see NPE signals below)

• (Possible intermediate Sharp → Foxconn-affiliated entity, 2016–2018; unverified) — IAM's June 2018 report describes the deal as originating "from Foxconn," which implies an internal Sharp→Foxconn step around the 2016 acquisition. No recorded US assignment to a Foxconn entity for this specific patent was verified, and Google Patents shows the 2018 recorded assignor as Sharp Corporation itself. I am not asserting this intermediate link as a recorded fact.

Bottom line: if the Assignment Center shows no further entries, that is consistent with my findings — the meaningful recorded chain for RE38,806 is Sharp → Katana Silicon Technologies LLC (2018-08-12), and the patent has been with Katana (a Longhorn IP affiliate) since.

Timeline diagram

timeline
    title Ownership of US RE38806
    1998 : Filed by Sharp Corp
    2000 : US 6100594 issued
    2005 : Reissue USRE38806 granted
    2016 : Sharp acquired by Foxconn
    2018 : Assigned to Katana Silicon LLC
    2022 : Suit filed vs Micron in WDTX
         : Micron files three IPRs
    2024 : PTAB finds claims unpatentable
    2026 : CAFC affirms PTAB decision

NPE / troll-pattern signals

1. Shell-entity transfer — Present (strong). The 2018-08-12 recorded assignment moved RE38,806 from operating company Sharp (via Foxconn) to Katana Silicon Technologies LLC, which is a licensing-only affiliate of the Texas NPE Longhorn IP. Corroboration is not naming-based inference: IAM's June 19, 2018 report ("Longhorn IP unit acquires former Sharp semiconductor patents from Foxconn… The licensing company, run by Khaled Fekih-Romdhane and Chris Dubuc, is calling its new vehicle Katana Silicon Technologies LLC") and Longhorn's own Katana page ("Katana Silicon Technologies (KST) is a Longhorn IP affiliate… acquired… from… Sharp") are concrete. Katana lists no products; its described business is acquiring and licensing patent portfolios.

2. Known asserter in the chain — Present (strong). Katana Silicon Technologies LLC is the current assignee and is a Longhorn IP affiliate (Longhorn IP blog, "PTAB REJECTS MICRON'S CHALLENGE TO KATANA PATENT": "Katana Silicon Technologies (KST) is a Longhorn IP affiliate"). Longhorn IP is widely tracked as an NPE; its principal Khaled Fekih-Romdhane is a former Acacia executive (TechRights, June 20, 2018). The Federal Circuit itself described the setup: "Katana, allegedly controlled by Longhorn IP, sued Micron in the Western District of Texas, asserting infringement of three expired semiconductor patents: U.S. Patents RE38,806, 6,352,879, and 6,731,013" (CAFC, Dec. 18, 2025).

3. Repeat correspondent across the chain — Unclear / not verifiable. I could not retrieve the recorded correspondents' names for the 2018-08-12 entry or any earlier entries. No finding either way.

4. Cascading transfers — Unclear / weak. The documented path is Sharp (2018 recorded assignor) → Katana, with an implied Sharp→Foxconn internal step in 2016–2018. That is at most two links, not a rapid multi-LLC cascade. Note, however, that Longhorn IP runs multiple parallel portfolio LLCs (Katana Silicon Technologies is its "fifth portfolio"), which is the same shell-per-portfolio structure TechRights flagged ("Notice how Longhorn IP uses shells").

5. Pre-litigation transfer — Not present under the 6-month test. Assignment recorded 2018-08-12; the first infringement suit naming RE38,806 (Katana v. Micron, W.D. Tex. 1:22-cv-00214) was filed March 2022 — roughly 3.5 years later, outside any 6-month window. The transfer was clearly for assertion (see the 2022–2026 litigation history), but it was not timed immediately before suit.

6. Bankruptcy fire-sale — Not present. Sharp was never in Chapter 7/11; its 2016 change of control was an acquisition by Foxconn, not a bankruptcy patent sale (contrast Kodak/Nortel patterns).

7. Privateering — Present (moderate-strong). IAM reported the deal as Foxconn (which owned Sharp by then) transferring former Sharp semiconductor patents to Longhorn IP's Katana vehicle, and TechRights characterized it the same way ("Foxconn transfers former Sharp patents to Texas-based NPE"). The asserted target, Micron, is a semiconductor manufacturer — consistent with an operating company parking legacy patents with an NPE affiliate to assert against a competitor space. The strongest independent evidence of the privateering structure is the CAFC's Dec. 18, 2025 opinion describing Katana as "allegedly controlled by Longhorn IP."

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN; it terminates at an asserting NPE affiliate.

Verdict

NPE — high confidence.

Two strong signals are independently documented rather than inferred from naming: (1) the 2018-08-12 recorded assignment moved RE38,806 from Sharp Corporation to Katana Silicon Technologies LLC, a licensing-only affiliate of Texas NPE Longhorn IP (confirmed by IAM, Longhorn's own Katana page, and the CAFC's description of Katana as "allegedly controlled by Longhorn IP"); and (2) Katana is a known high-frequency asserter that sued Micron in W.D. Tex. in March 2022 over RE38,806 and related expired Sharp patents, prompting Micron's three IPRs (IPR2023-00071/-00072/-00073), a PTAB unpatentability decision (May 13, 2024), an $8M bond under Idaho's bad-faith-assertion statute, and a Federal Circuit affirmance (April 21, 2026). The one weakness in the record is that I could not verify the reel/frame and correspondent details from the USPTO Assignment Center directly; the chain itself is well corroborated.

Verify at: USPTO Assignment Center search — https://assignmentcenter.uspto.gov/ (search "RE38806" or "Katana Silicon Technologies LLC"; also indexed at https://assignment.uspto.gov/patent/index.html). Key supporting sources: Google Patents legal-event feed for USRE38806 (2018-08-12 Sharp→Katana entry); IAM, June 19, 2018 ("Longhorn IP unit acquires former Sharp semiconductor patents from Foxconn"); Longhorn IP Katana page; CAFC Dec. 18, 2025 opinion (A&O Shearman summary); Federal Circuit Apr. 21, 2026 opinion in Katana Silicon Technologies LLC v. Micron Technology, Inc., Nos. 2024-2100, -2101, -2103.

Based on the searches I was able to complete (I hit the tool-step limit before I could pull the USPTO full-text citation list or the complete IPR exhibit lists), here is what I can reliably report, with explicit uncertainty flags where applicable.

Important framing note on "anticipation" (§ 102) vs. the actual record

In the IPR proceedings (IPR2023-00071/-00072/-00073), the PTAB held all of claims 1–33 of RE38,806 unpatentable under 35 U.S.C. § 103 (obviousness) — not under § 102 — primarily over WO 96/13066 (Mostafazadeh) in combination with other references. The Federal Circuit affirmed (Katana Silicon Technologies LLC v. Micron Technology, Inc., Nos. 2024-2100, -2101, -2103, Fed. Cir., Apr. 21, 2026). So on the available record, no reference was found to single-handedly anticipate any claim under § 102; the closest art was used in § 103 combinations. Below I map each citation to the claim elements it appears to disclose, and flag where a true single-reference § 102 anticipation case could not be confirmed from the sources I retrieved.

Patent citations on the face of RE38806 (identified so far)

The "Referenced Cited" listing (per Justia's record of RE38806; the list was truncated in my retrieval) shows at least:

The ellipses in the Justia result suggest additional entries exist that I could not retrieve. Uncertainty flag: I could not obtain the complete, authoritative USPTO "References Cited" list for RE38806 within the tool-step budget.

Prior art described in the RE38806 specification itself

The specification (which is authoritative and in the provided text) discusses two background references that correspond to the JP citations above:

1. JP 9-121002 (Tokukaihei 9-121002), published May 1997 — "Semiconductor Device and Manufacture Thereof" (per Unified Patents listing on the parent patent).

• The RE38806 specification states it discloses a CSP with: (a) a face-up chip wire-bonded to a wiring pattern on an insulating substrate (its FIG. 13(a)), and (b) a face-down chip connected by bump electrodes (its FIG. 13(b)), both with via holes connecting to external connection terminals on the substrate back — i.e., single-chip CSP structures with the substrate/wiring/via-hole/external-terminal framework.
• Claim-element overlap: Discloses the insulating substrate + wiring layer with electrode sections, via holes, external connection-use terminals, wire bonding of a chip, bump bonding of a chip, and resin sealing — elements common to claims 1, 2, 3, 23, 24, and the method claims. It does not disclose the stacked two-chip arrangement with back-side adhesion layers.
• § 102 potential: Could only potentially anticipate claims that do not require the stacked/two-chip/adhesion-layer limitations. On the available evidence it was not asserted as a single-reference anticipator of any RE38806 claim; the IPR used it, if at all, only as background/secondary art. Not confirmed as anticipating any claim alone.

2. JP 5-90486 (Tokukaibei 5-90486), published April 1993 — stacked-package art (Rohm).

• The RE38806 specification states it discloses stacked packages in which (a) a pair of chips are adhered back-to-back and mounted on another pair via metal bumps, and (b) a chip is adhered with its circuit surface facing the back surface of another chip — but in ceramic packages (not CSP).
• Claim-element overlap: Discloses stacked/laminated chips and back-to-back or face-to-back adhesion, relevant to the stacking limitations of claims 1–3, 6–8, 23–26. It does not disclose the CSP substrate/wiring-layer/via-hole/external-terminal structure or wafer-stage pre-applied adhesion layers.
• § 102 potential: Lacks too many CSP structural elements to anticipate the independent claims; not asserted as an anticipator in the IPR. Not a § 102 anticipation candidate on the available record.

3. WO 96/13066 (Mostafazadeh) — not an on-face citation, but the most relevant prior art in the litigated record.

• International publication WO 1996/13066, published 1996 (before the Jan. 1998 priority date).
• Micron's lead reference in all three IPRs (Exhibit 1003); the PTAB found claims 1–33 obvious over it in combination with other references, and the CAFC affirmed under the Board's construction of "adhesion layer" as "a layer that adheres."
• Claim-element overlap: Discloses a stacked-chip arrangement with adhesion layers between/behind dies, wire bonding, and resin encapsulation — the closest single disclosure to claims 1, 2, 23, 24, 30 and their dependents.
• § 102 potential: Because the PTAB's holding rested on § 103 combinations (and the CAFC's affirmance turned on claim construction, not on any single-reference § 102 finding), I cannot confirm from the retrieved materials that WO 96/13066 alone anticipates any claim. It is the strongest candidate for a potential § 102 challenge to the stacked-CSP independent claims, but the actual adjudicated ground was obviousness.

Claims analysis and uncertainties

• Independent claims likely relevant: 1, 2, 3, 23, 24 (apparatus) and 30 (method, per the CAFC opinion). Claims 27–33 were not fully retrievable.
• Per-reference § 102 status: Based on the retrieved record, the Board invalidated all claims under § 103, not § 102. I therefore cannot responsibly assert that any single citation "anticipates" a specific claim under § 102 without the full text of each reference and the complete claim set, neither of which I could fully obtain.
• Unresolved items to verify against USPTO records (e.g., USPTO PatentCenter, PatFT/AppFT, or the USPTO assignment/full-text database):
  1. The complete "References Cited" list of RE38806 (the Justia record appeared truncated; Google Patents' citation tab was not retrievable in usable form).
  2. The title, filing date, and content of US 6,077,724 (Chen) — published June 2000, i.e., after the Jan. 1998 priority date, so it could only be § 102(e) prior art if its effective filing date predates Jan. 14, 1998, which I could not verify. Treat its § 102 status as unconfirmed.
  3. The full list of IPR exhibits (Micron's exhibit 1003 was WO 96/13066; other combination references — e.g., 1004, 1005, etc. — were not retrievable in my searches).
  4. Whether the priority date is Jan. 13 or Jan. 14, 1998 (minor database discrepancy noted in the earlier analysis).

If you want, I can continue with additional searches on the USPTO citation list, the full text of US 6,077,724, and Micron's complete IPR exhibit/ground lists in a follow-up round.

Obviousness Analysis — U.S. Patent RE38,806 ("Semiconductor Device and Method of Manufacturing the Same")

Scope note and evidentiary basis

This analysis evaluates the patentability of RE38,806 (reissue of U.S. 6,100,594) under 35 U.S.C. § 103. The most probative evidence available is the adjudicated record: the PTAB's Final Written Decisions in IPR2023-00071/-00072/-00073 (May 13, 2024) holding all challenged claims (1–33) unpatentable as obvious, and the Federal Circuit's affirmance in Katana Silicon Technologies LLC v. Micron Technology, Inc., Nos. 2024-2100, -2101, -2103 (Fed. Cir., decided Apr. 21, 2026). The Board's primary reference was International Publication WO 96/13066 ("Mostafazadeh"), combined with "other references" that the Federal Circuit described as "not pertinent to this appeal." I did not have full access to the Final Written Decisions, so the complete list of secondary references used in each ground could not be independently verified; the combination analysis below therefore centers on (a) Mostafazadeh, whose role is confirmed on the record, and (b) the two stacked-package/CSP references that the '806 specification itself admits as prior art — JP 9-121002 (Tokukaihei 9-121002) and JP 5-90486 (Tokukaibei 5-90486). These are the closest references the patentee itself identified and are the natural building blocks for the claimed stacked-CSP structure.

I. Legal framework

Obviousness under § 103 is assessed under Graham v. John Deere Co., 383 U.S. 1 (1966): (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; and (4) secondary considerations. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), reinforces that a combination of known elements each performing its known function, yielding a predictable result, is ordinarily obvious, and that a court should ask whether a skilled artisan had a reason to combine, not whether the combination was "obvious to try" in the pejorative sense.

Level of ordinary skill. A person of ordinary skill in the art (POSITA) would be a packaging engineer or semiconductor process engineer with several years' experience in die-attach, wire bonding, flip-chip assembly, and CSP/ball-grid-array packaging, familiar with wafer-level processing (e.g., back-grinding, film lamination, spin coating, dicing) and with resin encapsulation. No party dispute on this point is reflected in the appeal; nothing in the '806 specification requires unusual skill to practice its two-chip stacks.

Controlling claim construction. The dispositive legal issue was the meaning of "adhesion layer." Katana urged "a pre-formed layer that is adhered" (i.e., a solid thermo-compression sheet laminated to the wafer before dicing). The Board and the Federal Circuit adopted Micron's construction — "a layer that adheres" — reasoning that: the claim language is purely functional; the specification describes both adhesive-agent (paste/potting) and thermo-compression-sheet approaches and their respective drawbacks; the disclosed solution common to both drawbacks is forming an adhesion layer at the wafer stage before dicing; and there is no lexicography or disavowal excluding adhesive layers that are applied wet, dried, diced, and later cured (the Mostafazadeh process). See CAFC op. at 4–9; J.A. 16–26, 1280–85. This construction is analytically critical: under it, the claims sweep in B-stage/dried adhesive layers and are not limited to pre-formed solid sheets, which is precisely what makes Mostafazadeh a devastating primary reference.

II. Scope and content of the prior art

1. WO 96/13066 (Mostafazadeh). A die-attach/adhesive-layer reference. Per the Federal Circuit's description of the record (J.A. 1280–85, 1297), Mostafazadeh recognizes the advantages of forming an adhesion layer on a wafer before the wafer is diced, so that individual chips carry adhesive layers that "neither overflow nor underfill the chip's surface." The adhesive layer is formed on the wafer, dried, diced into chips, and later cured during bonding. That is the same problem-solution pairing found in the '806 specification: the patent's Background condemns paste potting (overflow can force bond pads/wires outward, enlarging the package, or contaminate electrode pads; underfill can cause chip separation) and notes the double-alignment burden of thermo-compression sheets. The '806 solution — an insulating adhesion layer pre-disposed on the back of a chip at wafer stage — is functionally identical to Mostafazadeh's wafer-level adhesion layer.

2. JP 9-121002 (Tokukaihei 9-121002, "121002/1997"). Admitted prior art in the '806 Background (FIG. 13(a)–(b)). It discloses CSP structures comprising a wiring component/substrate with a wiring pattern, a semiconductor chip, and either (a) a face-up chip wire-bonded to the wiring pattern, resin-sealed, with the wiring pattern routed to external connection terminals through through-holes/vias, or (b) a face-down chip bump-bonded to the wiring pattern. This supplies the CSP substrate architecture: insulating substrate + wiring layer with electrode (inner connection) sections + via holes + arrayed packaging-use external terminals — the framework of claims 1, 2, 23, and 24.

3. JP 5-90486 (Tokukaibei 5-90486, "90486/1993"). Admitted prior art in the '806 Background (FIG. 14(a)–(b)). It discloses stacked packages in which pairs of semiconductor chips are adhered together — back-to-back (back surfaces facing) and face-to-back arrangements — and mounted on other chips via metal bumps. This supplies the multi-chip stacking motivation and geometry (stacking two chips with adhesive between them, including back-to-back chip pairs) missing from the single-chip CSP references.

4. Conventional techniques acknowledged in the '806 specification. Gold-ball wire bonding from chip pads to substrate electrode sections, gold-bump stud bonding, spin-coated insulating coatings, epoxy paste die attach, thermo-compression sheets, solder-resist, and resin transfer molding/sealing are all described in the '806 specification as known. A POSITA would treat these as general knowledge available to fill routine details.

III. Mapping the prior art to the claims

Claim 1 (and apparatus claims 23, and parallel method claim 30). Element-by-element:

Claim 2 (and 24). Same as claim 1 except the first chip is attached to the wiring layer by paste rather than a pre-adhered layer. This is closer to the prior art, not farther: paste die attach was the conventional potting method described in the '806 Background itself, and the "adhesion layer" construction covers a paste layer that adheres. Under the Board's construction, claim 2 reads directly onto a stacked-CSP built with conventional epoxy paste for the bottom die and a Mostafazadeh-style wafer-level layer for the top die.

Claim 3 (and dependents 4, 5, 20–22). First chip bump-bonded face-down to the wiring layer; second chip's back adhered back-to-back to the first chip's back through the adhesion layer; the second chip wire-bonded and the assembly resin-sealed. Mapping:

• Face-down bump-bonded CSP die: JP 9-121002 FIG. 13(b) (bump electrode connecting chip to wiring pattern).
• Back-to-back stacked die pair: JP 5-90486 (chips adhered with back surfaces facing).
• Adhesion layer formed at wafer stage: Mostafazadeh.
• Wire bonding of the upper chip to substrate electrode sections and resin sealing: JP 9-121002 FIG. 13(a) + conventional wire bonding.

Dependent claims. Claims 6–11 (support member under a protruding portion of the upper chip, optionally of matched linear-expansion coefficient) are routine mechanical reinforcement choices — dummy/spacer supports were conventional in stacked packages, and matching coefficients of thermal expansion to silicon was standard practice. Claims 12–19 (splitting a shared electrode section into two portions, daisy-chaining chip-to-chip, or routing the upper chip's wire through a dummy pad on the lower chip) are ordinary wire-routing design choices for avoiding wire sweep/crossing — the kind of predictable selection a layout engineer makes daily. Claims 4 (same-shape back surfaces), 5/21 (light-blocking layer), and 20/22 (underfill or insulating layer around bumps) are each conventional features (shaped die matching, light-blocking foil/black die-attach, capillary or no-flow underfill) applied for their known functions. Method claim 30 tracks the Mostafazadeh process sequence (form layer on wafer back → dice → mount → bond), plus the stacking and wire-bonding steps supplied by the JP references.

IV. Motivation to combine

The Board found, and the Federal Circuit affirmed, a sufficient reason to combine Mostafazadeh with the other references. The principal motivations are these:

1. Shared problem — adhesive overflow/underfill at the chip-attach interface. The '806 specification's own Background identifies precisely the two failure modes of conventional die attach: excess adhesive overflowing the chip edge (forcing bond locations outward and enlarging the package, or contaminating pads) and insufficient adhesive leaving gaps that resin cannot fill (causing delamination). Mostafazadeh is directed to the identical problem and solves it the identical way — forming the adhesive layer on the wafer before dicing so each chip carries a dried, uniform layer that neither overflows nor underfills. A POSITA reading the '806 disclosure would immediately recognize Mostafazadeh as the very teaching that makes the claimed structure workable, and would have a strong reason to substitute or combine Mostafazadeh's wafer-level adhesion layer for the troublesome paste potting and the alignment-heavy thermo-compression sheet described in the '806 Background. The Federal Circuit expressly noted that Mostafazadeh "discloses the very advantage" Katana claimed for its invention — evenness, with no extension beyond the die's mounting surface — undercutting any argument that the advantage was nonobvious.

2. Design need/market pressure — miniaturized high-density packaging. The '806 Background describes the industry trajectory from multi-chip modules (area-limited) to stacked packages (JP 5-90486) to CSP (JP 9-121002), and states the object of the invention as a device combining stacked-package and CSP structures. That object is itself evidence of a recognized design need: put more chips in a chip-sized footprint. KSR instructs that "design need and market pressure to solve a technical problem" and "the existence of a finite number of identified, predictable solutions" support obviousness. A POSITA seeking a stacked CSP would naturally look to the two closest known solutions — the stacked-die package (JP 5-90486) and the wire-bonded/bumped CSP (JP 9-121002) — and to the best-known die-attach solution to the overflow problem (Mostafazadeh), and combine them.

3. Predictable combination of known elements performing known functions. Each claim element, taken singly, was admittedly old: CSP substrates with vias and ball terminals (JP 9-121002); stacked die with adhesive (JP 5-90486); wafer-level die-attach layers (Mostafazadeh); wire bonding; resin sealing. The combination does not produce an unexpected result — it yields a predictably smaller stacked package. The only arguably novel coordination — placing the adhesion layer on the chip backs before stacking so that no wet adhesive is present at the wire-bonding stage (permitting bonds closer to chip edges) — is exactly what Mostafazadeh teaches for the substrate interface and what a POSITA would apply with reasonable expectation of success to the chip-to-chip interface as well. No criticality, no unexpected synergy, and no teaching-away appears in the record.

4. No secondary considerations of substance. The record reflects no persuasive evidence of long-felt need, industry copying, commercial success, or unexpected results attributable to the claimed features (the patent owner's expert and evidentiary challenges were rejected by the Board). The claims were upheld only in the sense of surviving institution; on the merits the Board found them obvious, and the Federal Circuit found no error.

5. The construction point defeats the patent owner's only meaningful distinction. Katana's argument — that the specification's two preferred embodiments both use a thermo-compression sheet, making that sheet definitional — was rejected because importing preferred-embodiment limitations into claims absent lexicography or disavowal is impermissible, and because the specification affirmatively discusses adhesive-agent drawbacks and describes the solution as wafer-stage layer formation, not sheet lamination. Once "adhesion layer" means "a layer that adheres," Mostafazadeh's dried-then-cured wafer-level adhesive layer is an "adhesion layer" formed on the back surface of the wafer, and the principal claimed point of novelty evaporates. Katana's further argument on claim 30's "forming" language failed for the same reason: "forming" was given its ordinary meaning, and forming a layer by coating/drying on a wafer is squarely within it.

V. Conclusion

Claims 1–33 of RE38,806 are obvious under 35 U.S.C. § 103 over WO 96/13066 (Mostafazadeh) in combination with the stacked-package and CSP references the specification itself admits — JP 5-90486 (die stacking, including back-to-back pairs) and JP 9-121002 (wire-bonded and bumped CSP substrates with vias, electrode sections, and arrayed external terminals) — together with conventional wire-bonding, underfill, and resin-sealing techniques. A POSITA would have been motivated to combine these references because (i) Mostafazadeh solves the very overflow/underfill problem the '806 specification identifies, by the very wafer-stage-layer means the claims require; (ii) the industry's recognized design need for a stacked, chip-size package created a market pressure to merge the stacked-die and CSP teachings; and (iii) the result is a predictable combination of known elements performing known functions with a reasonable expectation of success. This conclusion is consistent with the PTAB's Final Written Decisions of May 13, 2024 (all challenged claims unpatentable) and the Federal Circuit's affirmance of April 21, 2026.

Uncertainty caveats. (1) The complete list of secondary references in each IPR ground resides in the Final Written Decisions, which I could not fully retrieve; the Federal Circuit's "not pertinent to this appeal" characterization means the identity of those references was not material to affirmance, and I have not verified whether the Board relied specifically on JP 9-121002/JP 5-90486 or on different secondary references. (2) Claim 29 and the full text of claims 26–33 were not available in the supplied extract, so my claim-by-claim mapping for that group is inferential. (3) The priority date discrepancy (1998-01-13 vs. 1998-01-14) does not affect the obviousness analysis because all references discussed predate either date.