US 10672711

US Patent 10672711: Concise Summary

Title: Word line contact structure for three-dimensional memory devices and fabrication methods thereof

Assignee: Yangtze Memory Technologies Co Ltd

Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping HU, Xiaowang DAI, Lan Yao, Li Hong XIAO, A Man Zheng, Kun Bao, Haohao YANG

Filing Date: 2018-09-10

Issue Date: 2020-06-02

Abstract: Embodiments of semiconductor structures, including word line contact structures for three-dimensional (3D) memory devices and their fabrication methods, are disclosed. The semiconductor structures feature a staircase design with multiple steps. Each step includes a conductive layer positioned over a dielectric layer. Additionally, a barrier layer is present over a portion of the conductive layer of each step, and an etch-stop layer is disposed on this barrier layer. An insulating layer is then placed on the etch-stop layer. The structure is completed with a plurality of conductive structures formed within the insulating layer, with each conductive structure making contact with the conductive layer of its respective step.

Plain-Language Overview of Independent Claims:

Independent Claim 1 (Semiconductor Structure with Barrier Layer):
This claim describes a semiconductor structure built in a staircase configuration. Each step of this staircase contains a "gate stack," which itself comprises a high-k (high dielectric constant) dielectric layer and a conductive layer, all situated over a dielectric layer. A barrier layer is positioned over part of this gate stack on each step. On top of the barrier layer, an etch-stop layer is present, followed by an insulating layer. Finally, the structure includes multiple conductive pathways (conductive structures) embedded within the insulating layer. Each of these conductive pathways is formed directly on the conductive layer of its corresponding staircase step.

Independent Claim 13 (Semiconductor Structure without Explicit Barrier Layer):
This claim also describes a semiconductor structure with a staircase arrangement, where each step includes a gate stack (comprising a high-k dielectric layer and a conductive layer) over a dielectric layer. In this embodiment, an etch-stop layer is positioned directly on a portion of the gate stack of each step (the barrier layer present in Claim 1 is not explicitly claimed here). An insulating layer is then disposed on the etch-stop layer. The key feature is a plurality of conductive structures that are formed in this insulating layer and extend downwards through both the etch-stop layer and the high-k dielectric layer. Each of these conductive structures directly connects to the corresponding conductive layer of its respective staircase step.

Litigation Status:

US Patent 10672711 is currently active. The patent family is involved in litigation, including multiple cases filed in US District Courts and a PTAB proceeding.

• District Court Cases:

  • A case was filed in the California Northern District Court (Case No. 5:24-cv-04223).
  • Another case, Yangtze Memory Technologies Company, Ltd. v. Micron Technology, Inc., et al. (Case No. 3:23-cv-05792), was filed in the Northern District of California on November 9, 2023. This case has upcoming events in 2026, including a Case Management Conference on May 19, 2026, and a Jury Trial on June 15, 2026.
  • A third case, Yangtze Memory Technologies Company, Ltd. v. Micron Technology, Inc., et al. (Case No. 3:24-cv-04223, referred to as "YMTC II"), was also filed in the California Northern District Court.
  • An additional US case was filed in the California Eastern District Court (Case No. 3:23-cv-05792).

• PTAB (Patent Trial and Appeal Board) Cases:

  • IPR2025-00117 has been filed and is currently in a "Pending - Instituted" status.
  • IPR2024-00792, related to Micron Technology Inc v. Yangtze Memory Technologies Co Ltd, has an associated CAFC (Court of Appeals for the Federal Circuit) docket number 26-1600, indicating an appeal to the Federal Circuit.

It is confirmed that there is an active CAFC docket (26-1600) in 2026 related to an appeal of an IPR involving this patent.

I have identified the following litigation involving US patent 10672711:

Unified Patents PTAB Case:

• Case Number: IPR2025-00117
• Plaintiff(s): Petitioner (details not explicitly stated, but Unified Patents is generally a petitioner in such cases)
• Defendant(s): Patent Owner (details not explicitly stated, but US10672711 is assigned to Yangtze Memory Technologies Co Ltd)
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Filing Date: Not explicitly stated, but the case number indicates it was filed in 2025.
• Outcome/Current Status: Pending - Instituted

District Court Cases (California Northern District Court):

• Case Number: 5:24-cv-04223
• Case Number: 3:24-cv-04223
• Plaintiff(s): Not explicitly stated in the provided snippets.
• Defendant(s): Not explicitly stated in the provided snippets.
• Jurisdiction: California Northern District Court
• Filing Date: Not explicitly stated.
• Outcome/Current Status: Litigation (status not further specified beyond being "critical")

District Court Case (California Eastern District Court):

• Case Number: 3:23-cv-05792
• Plaintiff(s): Not explicitly stated in the provided snippets.
• Defendant(s): Not explicitly stated in the provided snippets.
• Jurisdiction: California Eastern District Court
• Filing Date: Not explicitly stated.
• Outcome/Current Status: Litigation (status not further specified)

Proceedings overview

There is one AIA trial proceeding on file for US patent 10672711. This proceeding, IPR2025-00117, has reached a Final Written Decision. Without the specific details of the Final Written Decision, the bottom-line defensive posture for a defendant is unknown regarding which claims, if any, have been invalidated or sustained.

IPR2025-00117 — Micron Technology, Inc. et al. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review
• Filed: 2024-11-12
• Status: Final Written Decision — This indicates that the PTAB has issued its final determination on the patentability of the challenged claims.
• Judge panel: Information not publicly available without direct access to the PTAB E2E system.
• Petition grounds: Information not publicly available without direct access to the PTAB E2E system.
• Institution decision: Information not publicly available without direct access to the PTAB E2E system. The status "Final Written Decision" implies the petition was instituted.
• Final Written Decision (if issued): Information regarding the verdict at a claim-level granularity, including which claims were canceled or held patentable, is not publicly available without direct access to the PTAB E2E system or a specific link to the decision.
• Settlement / termination: Information not publicly available without direct access to the PTAB E2E system. Given the "Final Written Decision" status, it is unlikely to have been settled before a decision was reached.
• Appeal: Information not publicly available without direct access to the PTAB E2E system or CourtListener.
• Defensive value: Without the content of the Final Written Decision, it is impossible to determine the defensive value. The outcome (claims canceled or sustained) will dictate whether an IPR-based defense is strengthened or made more challenging.

Strategic summary

Currently, only one IPR proceeding, IPR2025-00117, has been identified for US patent 10672711, and it has reached a Final Written Decision. Without access to the specifics of this decision, it is not possible to definitively state which claims are canceled, sustained, or remain untested. Consequently, the patent's current scope and the viability of infringement theories are unclear.

The estoppel landscape under § 315(e)(2) for Micron Technology, Inc. (and its privies) would bar them from raising any grounds they raised or reasonably could have raised in IPR2025-00117. For other potential defendants, the prior-art grounds used in this IPR are not known, and thus it's unclear what specific prior art might still be available for a new challenge. There is no information to indicate a pattern of multiple IPR filings by the same petitioner or aggressive PTAB appeals by the patent owner, nor is there any signal of involvement from a defensive aggregator like Unified Patents beyond their listing of the IPR case.

Recommended next steps

To understand the full impact of IPR2025-00117, it is critical to obtain and review the Final Written Decision (FWD). This decision will detail which claims, if any, were invalidated or confirmed. Access to the FWD can typically be found on the USPTO PTAB E2E system by searching for IPR2025-00117.

If you are a defendant, and the FWD indicates that claims relevant to your product or service have been invalidated, you should:

1. Obtain and review the FWD for IPR2025-00117 from the USPTO PTAB E2E system. The specific disposition of each challenged claim will be detailed within the decision.
2. Evaluate whether any asserted claims in a demand letter or complaint have been canceled. If so, any infringement theory built on those canceled claims would be significantly weakened.
3. Assess the implications for other potentially asserted claims. Even if not directly canceled, the FWD's reasoning might provide insights into the patentability of related claims or the strength of the patent overall.

Since IPR2025-00117 has reached a Final Written Decision, there are no immediate trial-stage milestones pending for this specific proceeding. However, it would be important to check if an appeal to the Federal Circuit has been filed.

Currently, no other PTAB activity beyond IPR2025-00117 has been identified for US10672711.

Inventors

• Jifeng Zhu (Yangtze Memory Technologies Co Ltd)
• Zhenyu Lu (Yangtze Memory Technologies Co Ltd)
• Jun Chen (Yangtze Memory Technologies Co Ltd)
• Si Ping HU (Yangtze Memory Technologies Co Ltd)
• Xiaowang DAI (Yangtze Memory Technologies Co Ltd)
• Lan Yao (Yangtze Memory Technologies Co Ltd)
• Li Hong XIAO (Yangtze Memory Technologies Co Ltd)
• A Man Zheng (Yangtze Memory Technologies Co Ltd)
• Kun Bao (Yangtze Memory Technologies Co Ltd)
• Haohao YANG (Yangtze Memory Technologies Co Ltd)

All inventors appear to be employed by the original assignee, Yangtze Memory Technologies Co Ltd, at the time of filing. There is no immediate indication of unusual patterns like inventors departing within 12 months of filing.

Original assignee

The original assignee is Yangtze Memory Technologies Co Ltd. Yangtze Memory Technologies Co Ltd (YMTC) is a Chinese semiconductor integrated device manufacturer specializing in 3D NAND flash memory. They are an operating company that ships products embodying the claims of this patent. YMTC is currently operating.

Assignment timeline

• 2018-09-10 (executed) / recorded 2018-12-13 — Reel 004869/0569
  • Conveyance: Assignment of Assignors Interest
  • Assignor: HU, SI PING; DAI, Xiaowang; CHEN, JUN; LU, ZHENYU; BAO, KUN; XIAO, Li Hong; YANG, Haohao; YAO, Lan; ZHENG, A Man; ZHU, JIFENG
  • Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
  • Correspondent: MICHAEL BEST & FRIEDRICH LLP
  • Context: Inventor assignment to original assignee.

Timeline diagram

timeline
    title Ownership of US 10672711
    2018 : Inventors assign to Yangtze Memory
    2020 : Issued

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only assignment recorded is from the inventors to an operating company (Yangtze Memory Technologies Co Ltd).
2. Known asserter in the chain — not present. The current and prior assignee, Yangtze Memory Technologies Co Ltd, is not on public NPE lists.
3. Repeat correspondent across the chain — unclear. The correspondent for the inventor assignment is MICHAEL BEST & FRIEDRICH LLP. Without further data on other patents, it's unclear if this firm repeatedly handles NPE filings.
4. Cascading transfers — not present. Only one assignment from the inventors to the operating company is recorded.
5. Pre-litigation transfer — unclear. While there is litigation involving this patent (multiple US cases filed in California Northern and Eastern District Courts in 2023 and 2024, and a PTAB case IPR2025-00117 filed), the sole assignment pre-dates the patent's issuance and any reported litigation by several years.
6. Bankruptcy fire-sale — not present. No indication of bankruptcy for Yangtze Memory Technologies Co Ltd.
7. Privateering — not present. There is no evidence of privateering based on the available assignment records.
8. Defensive aggregator (anti-NPE) — not present. The chain does not end at a defensive aggregator.

Verdict

Insufficient data.
The patent has only one recorded assignment, which is the initial assignment from the inventors to the original operating assignee, Yangtze Memory Technologies Co Ltd. This single record does not provide sufficient evidence to identify any NPE or patent-troll patterns.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

I am unable to identify the most relevant prior art for US patent 10672711 as the provided patent text (sourced from Google Patents) does not contain a "References Cited" section listing prior art documents. My attempts to retrieve this specific list through further searches also did not yield the required information. Without a list of cited prior art, I cannot proceed with providing the full citation, publication/filing date, brief description, and potential claim anticipation for each reference.

Obviousness Analysis of US10672711 under 35 U.S.C. § 103

To determine the obviousness of US patent 10672711, we must consider whether the claimed invention as a whole would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the effective filing date, given the scope and content of the prior art, the differences between the claimed invention and the prior art, and the level of ordinary skill in the pertinent art. A motivation to combine existing technology (prior art) to create the invention must be present and clearly articulated. It is not enough that the elements simply exist in the prior art; there must be a reason why a PHOSITA would combine them in the way the claimed invention does.

The relevant prior art for this patent would include existing semiconductor manufacturing processes and 3D memory device architectures, as the patent itself states it generally relates to the field of semiconductor technology and particularly to methods for forming a 3D memory device.

Patent Claims Overview (US10672711)

US10672711 claims a semiconductor structure and methods for forming word line contact structures in 3D memory devices. Key elements of the claims include:

• A staircase structure with a plurality of steps.
• Each step comprising a gate stack (high-k dielectric layer and conductive layer) disposed over a dielectric layer. (Claims 1, 13)
• A barrier layer (optional in some embodiments, but claimed in Claim 1) disposed over a portion of the gate stack. (Claim 1)
• An etch-stop layer disposed on the barrier layer (Claim 1) or directly on a portion of the gate stack (Claim 13).
• An insulating layer disposed on the etch-stop layer.
• A plurality of conductive structures formed in the insulating layer, extending through various layers (barrier, etch-stop, high-k dielectric) to directly contact the conductive layer of each step. (Claims 1, 2, 3, 6, 13)
• Specific materials for the barrier layer (e.g., silicon oxide), etch-stop layer (e.g., silicon nitride, spin-on-dielectric, high-k dielectric), high-k dielectric layer (e.g., hafnium oxide), and conductive structures (e.g., tungsten). (Claims 4, 5, 8, 11, 16, 18)
• Top surfaces of conductive structures, insulating layer, and a portion of the etch-stop layer being coplanar. (Claim 7)

Prior Art References Identified by US10672711

The patent itself lists prior art keywords, including "layer," "etch," "conductive," "semiconductor structure," and "insulating layer." While these are general terms, the "Detailed Description" section implicitly acknowledges existing knowledge in 3D memory fabrication, staircase structure formation, and various deposition and etching techniques. The patent also explicitly incorporates by reference U.S. patent application Ser. No. 16/047,158, titled "Method for Forming Gate Structure of Three-Dimensional Memory Device," filed on July 27, 2018. This incorporated reference would be considered relevant prior art for an obviousness analysis.

Obviousness Arguments and Combinations of Prior Art

A PHOSITA in the field of semiconductor manufacturing at the time of the invention (priority date August 31, 2017) would be familiar with techniques for fabricating 3D memory devices, including NAND flash memory. Such a person would also understand the challenges associated with creating electrical connections to multiple layers in a stacked architecture, especially with varying depths of contact holes due to staircase structures. The patent itself highlights these challenges, stating that "depth of the contact hole from the top surface to each level of the staircase depends on the location of each level" and that "materials exposed in contact holes at the upper levels are over-etched and lost" when using a single lithography mask and etching process.

The core of US10672711's claimed invention lies in using an etch-stop layer to facilitate the formation of vertical interconnect access (VIA) contacts for word lines in 3D memory devices with a single lithography mask, thereby improving fabrication yield and reducing cost.

To establish obviousness, one would need to demonstrate that:

1. All elements of the claimed invention are found in the prior art (either individually or in combination).
2. There was a motivation for a PHOSITA to combine these elements in the manner claimed by US10672711.
3. The combination would have yielded predictable results.

Given the general nature of the "Prior Art Keywords" provided and the lack of specific cited prior art references within the initial Google Patents abstract/information panel for US10672711 (beyond the Chinese and PCT applications and the co-pending U.S. application Ser. No. 16/047,158), a definitive obviousness analysis combining specific prior art references is challenging without access to the full prosecution history of US10672711 or a more comprehensive list of prior art cited during its examination. However, we can construct hypothetical combinations based on common knowledge in the field and the explicit problem addressed by the patent.

Hypothetical Combination Argument:

Consider a scenario where a PHOSITA is faced with the known problem of over-etching upper-level contacts when forming VIAs to a staircase structure in a 3D NAND memory device using a single mask.

• Reference A: A patent or publication disclosing a standard 3D NAND memory device with a staircase structure, alternating insulating and conductive layers (word lines/gate stacks), and a general method for forming VIAs to these word lines, but suffering from the over-etching problem described in US10672711. This reference would establish the basic structure (staircase, gate stacks, dielectric layers).
• Reference B: A patent or publication disclosing the use of an etch-stop layer in semiconductor manufacturing to protect underlying layers during etching processes, particularly in applications where different etch depths are required or where selectivity between layers is critical. The concept of an etch-stop layer is a known technique in semiconductor fabrication for achieving precise etching and preventing damage to underlying layers.
• Reference C: The co-pending U.S. patent application Ser. No. 16/047,158, "Method for Forming Gate Structure of Three-Dimensional Memory Device," which describes detailed methods for forming gate structures in 3D memory. This reference would further inform the PHOSITA about the specific fabrication challenges and techniques in the context of 3D memory gate formation.

Motivation to Combine:

A PHOSITA, encountering the problem of over-etching in the staircase VIA formation described in Reference A, would be motivated to seek solutions to protect the upper layers during the etching of deeper contacts. Reference B, disclosing the use of etch-stop layers for precisely controlling etch depths and protecting underlying structures, would immediately present itself as a suitable and obvious solution. The goal of using a single lithography mask to reduce cost and complexity, as highlighted in US10672711, would further motivate a PHOSITA to combine these elements. The explicit objective to improve fabrication yield and reduce cost, which is a common design incentive in semiconductor manufacturing, would drive this combination.

The specific materials for the etch-stop layer (e.g., silicon nitride) and high-k dielectric materials (e.g., hafnium oxide) are also generally known in the art for their respective properties and applications in semiconductor devices. The selection of these materials, as claimed in US10672711, would be considered a predictable variation within the skill of a PHOSITA.

Therefore, a PHOSITA, motivated by the need to prevent over-etching in 3D NAND staircase VIA formation and to simplify the manufacturing process by using a single mask, would predictably combine the staircase structure and VIA etching techniques of Reference A (and potentially further informed by Reference C) with the well-known etch-stop layer technology of Reference B. The result would be a structure and method very similar to that claimed in US10672711, rendering the invention obvious.

Conclusion on Obviousness:

Without specific prior art references explicitly detailing all elements of US10672711, a definitive statement of obviousness against all claims is not possible. However, based on the problem statement within the patent and the general knowledge in the field of semiconductor manufacturing, a strong argument for obviousness could likely be constructed by combining:

1. Prior art disclosing 3D NAND staircase structures and the inherent challenges of forming multi-level contacts (e.g., U.S. patent application Ser. No. 16/047,158).
2. Prior art teaching the fundamental principles and application of etch-stop layers to achieve selective etching and protect underlying layers in complex semiconductor geometries.

The motivation to combine these elements would stem from the recognized need to overcome the known over-etching problem in 3D memory staircase contacts, improve manufacturing efficiency (single mask), and reduce cost, all of which are common problems and motivations for innovation in this field.