US 11581322

Here's a concise summary of US Patent 11581322:

US Patent 11581322: Three-dimensional memory devices having through array contacts and methods for forming the same

• Title: Three-dimensional memory devices having through array contacts and methods for forming the same
• Assignee: Yangtze Memory Technologies Co Ltd
• Inventors: Mei Lan GUO, Yushi Hu, Ji Xia, Hongbin Zhu
• Filing Date: 2020-11-21
• Issue Date: 2023-02-14
• Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure fully filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.

Plain-Language Overview of Independent Claims:

1. Method for Forming a 3D Memory Device (Claim 1 Summary): A method involving building a layered dielectric stack on a substrate, then creating vertical channel structures. A vertical opening is made in the dielectric stack, and a spacer is formed on its inner wall. A conductive material is deposited in this opening to create a Through Array Contact (TAC). After the TAC is formed, a vertical slit is created in the dielectric stack. Finally, the sacrificial layers within the stack are replaced with conductive layers through this slit, forming the functional memory stack.
2. Method for Forming a 3D Memory Device with Dummy Channel and Peripheral Contact (Claim 2 Summary): This method also starts with forming a dielectric stack on a substrate and creating vertical channel structures, along with vertical dummy channel structures. It then involves simultaneously etching a first opening within the dielectric stack and a second opening outside of it. Spacers are simultaneously formed on the sidewalls of both the first and second openings. A conductive layer is then deposited to fill the first opening, creating a TAC, and to fill the second opening, creating a peripheral contact. Following this, a vertical slit is formed in the dielectric stack, and the sacrificial layers are replaced with conductive layers through the slit to form the memory stack.
3. Method for Forming a 3D Memory Device with Controlled Opening Dimensions (Claim 3 Summary): This method includes forming a dielectric stack on a substrate and vertical channel structures. It simultaneously etches three types of vertical openings: a first opening in the dielectric stack (for a TAC), a second opening outside the stack (for a peripheral contact), and a third opening in the dielectric stack (for a dummy channel). The key is that the third opening is made narrower than the first and second openings. A dielectric layer is then deposited, completely filling the narrow third opening (to form a dummy channel structure) and only partially filling the wider first and second openings. The dielectric material at the bottom of the first and second openings is removed. Subsequently, a conductive layer is deposited to fill the remaining space in the first opening (forming a TAC) and the second opening (forming a peripheral contact). A vertical slit is then created, and the sacrificial layers are replaced with conductive layers through this slit to form the memory stack.
4. 3D Memory Device (Claim 4 Summary): This claim describes the actual device, comprising a substrate, a memory stack on the substrate (made of alternating conductor and dielectric layers), a channel structure vertically passing through these layers, a Through Array Contact (TAC) also extending vertically through the layers, and a dummy channel structure, completely filled with a dielectric material, which also extends vertically through the memory stack.

Litigation Information:
As of April 26, 2026, US Patent 11581322 is active and has a stated expiration date of November 6, 2038. The patent is involved in litigation, including US cases filed in the California Northern District Court (cases 5:24-cv-04223 and 3:24-cv-04223) and the California Eastern District Court (case 3:23-cv-05792). Additionally, a PTAB case, IPR2025-00191, has been filed and is currently pending and instituted. However, no specific dockets for this patent within the U.S. Court of Appeals for the Federal Circuit (CAFC) for the year 2026 were found through the provided patent information or external searches.