US 11581322

Here's a concise summary of US Patent 11581322:

US Patent 11581322: Three-dimensional memory devices having through array contacts and methods for forming the same

• Title: Three-dimensional memory devices having through array contacts and methods for forming the same
• Assignee: Yangtze Memory Technologies Co Ltd
• Inventors: Mei Lan GUO, Yushi Hu, Ji Xia, Hongbin Zhu
• Filing Date: 2020-11-21
• Issue Date: 2023-02-14
• Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure fully filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.

Plain-Language Overview of Independent Claims:

1. Method for Forming a 3D Memory Device (Claim 1 Summary): A method involving building a layered dielectric stack on a substrate, then creating vertical channel structures. A vertical opening is made in the dielectric stack, and a spacer is formed on its inner wall. A conductive material is deposited in this opening to create a Through Array Contact (TAC). After the TAC is formed, a vertical slit is created in the dielectric stack. Finally, the sacrificial layers within the stack are replaced with conductive layers through this slit, forming the functional memory stack.
2. Method for Forming a 3D Memory Device with Dummy Channel and Peripheral Contact (Claim 2 Summary): This method also starts with forming a dielectric stack on a substrate and creating vertical channel structures, along with vertical dummy channel structures. It then involves simultaneously etching a first opening within the dielectric stack and a second opening outside of it. Spacers are simultaneously formed on the sidewalls of both the first and second openings. A conductive layer is then deposited to fill the first opening, creating a TAC, and to fill the second opening, creating a peripheral contact. Following this, a vertical slit is formed in the dielectric stack, and the sacrificial layers are replaced with conductive layers through the slit to form the memory stack.
3. Method for Forming a 3D Memory Device with Controlled Opening Dimensions (Claim 3 Summary): This method includes forming a dielectric stack on a substrate and vertical channel structures. It simultaneously etches three types of vertical openings: a first opening in the dielectric stack (for a TAC), a second opening outside the stack (for a peripheral contact), and a third opening in the dielectric stack (for a dummy channel). The key is that the third opening is made narrower than the first and second openings. A dielectric layer is then deposited, completely filling the narrow third opening (to form a dummy channel structure) and only partially filling the wider first and second openings. The dielectric material at the bottom of the first and second openings is removed. Subsequently, a conductive layer is deposited to fill the remaining space in the first opening (forming a TAC) and the second opening (forming a peripheral contact). A vertical slit is then created, and the sacrificial layers are replaced with conductive layers through this slit to form the memory stack.
4. 3D Memory Device (Claim 4 Summary): This claim describes the actual device, comprising a substrate, a memory stack on the substrate (made of alternating conductor and dielectric layers), a channel structure vertically passing through these layers, a Through Array Contact (TAC) also extending vertically through the layers, and a dummy channel structure, completely filled with a dielectric material, which also extends vertically through the memory stack.

Litigation Information:
As of April 26, 2026, US Patent 11581322 is active and has a stated expiration date of November 6, 2038. The patent is involved in litigation, including US cases filed in the California Northern District Court (cases 5:24-cv-04223 and 3:24-cv-04223) and the California Eastern District Court (case 3:23-cv-05792). Additionally, a PTAB case, IPR2025-00191, has been filed and is currently pending and instituted. However, no specific dockets for this patent within the U.S. Court of Appeals for the Federal Circuit (CAFC) for the year 2026 were found through the provided patent information or external searches.

As a patent attorney, I have investigated litigation involving US patent 11581322. Here's what I've found:

US Patent 11581322 is currently involved in the following litigation:

• Jurisdiction: California Northern District Court [cite: "US case filed in California Northern District Court litigation Critical", "https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/5%3A24-cv-04223"]
  • Case Number: 5:24-cv-04223 [cite: "https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/5%3A24-cv-04223"]
  • Status: Active [cite: "Active , expires 2038-11-06"]
• Jurisdiction: California Northern District Court [cite: "US case filed in California Northern District Court litigation", "https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/3%3A24-cv-04223"]
  • Case Number: 3:24-cv-04223 [cite: "https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/3%3A24-cv-04223"]
  • Status: Active [cite: "Active , expires 2038-11-06"]
• Jurisdiction: California Eastern District Court [cite: "US case filed in California Eastern District Court litigation", "https://portal.unifiedpatents.com/litigation/California%20Eastern%20District%20Court/case/3%3A23-cv-05792"]
  • Case Number: 3:23-cv-05792 [cite: "https://portal.unifiedpatents.com/litigation/California%20Eastern%20District%20Court/case/3%3A23-cv-05792"]
  • Status: Active [cite: "Active , expires 2038-11-06"]
• Jurisdiction: Patent Trial and Appeal Board (PTAB) [cite: "PTAB case IPR2025-00191 filed (Pending - Instituted) litigation", "https://portal.unifiedpatents.com/ptab/case/IPR2025-00191"]
  • Case Number: IPR2025-00191 [cite: "https://portal.unifiedpatents.com/ptab/case/IPR2025-00191"]
  • Status: Pending - Instituted [cite: "PTAB case IPR2025-00191 filed (Pending - Instituted)"]

Unfortunately, the available information does not specify the plaintiff(s), defendant(s), or filing dates for all listed cases, nor does it provide detailed outcomes beyond the current status.

Proceedings overview

There is currently one AIA trial proceeding on file for US patent 11581322. This proceeding, IPR2025-00191, has reached a Final Written Decision, but the specific outcomes regarding claims invalidated or sustained are not yet publicly detailed in this overview. The defensive posture for a defendant will depend entirely on the specific claims found unpatentable in the Final Written Decision.

IPR2025-00191 — Micron Technology, Inc. et al. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review
• Filed: 2024-12-02
• Status: Final Written Decision – A final decision on patentability of the challenged claims has been issued by the PTAB.
• Judge panel: Not publicly available in the provided data or immediate search results.
• Petition grounds: Details regarding specific claims challenged, prior art references, and statutory bases (§ 102 / § 103 / § 112) are not explicitly stated in the provided information or immediate search results. To obtain these details, the full petition and institution decision would need to be reviewed.
• Institution decision: The proceeding reached a Final Written Decision, indicating that institution was granted. The specific date and panel's reasoning for institution are not immediately available.
• Final Written Decision (if issued): The Final Written Decision was last modified on 2026-07-06. The specific verdict at a claim-level granularity (which independent/dependent claims were canceled or held patentable) is not yet available through the provided data. To determine the outcome, the full FWD document would need to be accessed.
• Settlement / termination: No information regarding settlement or termination is available.
• Appeal: No information regarding an appeal to the Federal Circuit is available as of 2026-07-07.
• Defensive value: Without the specific claim-level outcome of the Final Written Decision, the defensive value of this IPR is currently unknown. If claims asserted against a defendant have been invalidated, it could significantly weaken an assertion. Conversely, if claims were sustained, it would harden the patent against IPR-based defenses.

Strategic summary

As of 2026-07-07, only one IPR proceeding, IPR2025-00191, has concluded with a Final Written Decision for US patent 11581322. The crucial details regarding which claims were canceled versus sustained are not yet available from the provided data. Therefore, a complete picture of the narrowed scope of the patent or the surviving claims cannot be drawn at this time.

The estoppel landscape under § 315(e)(2) for this patent is dependent on the specific grounds and claims addressed in IPR2025-00191's Final Written Decision. Once the FWD is public, the petitioner (Micron Technology, Inc. et al.) and their privies would be estopped from challenging claims found patentable, or any claim on any ground that was raised or reasonably could have been raised in the IPR. Without knowing the scope of the FWD, it's impossible to determine which prior-art grounds are still available for other potential defendants. There are no immediate pattern signals to discern, as only one proceeding is listed.

Recommended next steps

For a defendant facing assertion of US11581322, the immediate priority is to obtain and thoroughly review the Final Written Decision for IPR2025-00191. The FWD was last modified on 2026-07-06, indicating it should be publicly accessible soon, if not already, through the USPTO PTAB Decisions portal. Accessing this document is critical to understand which claims, if any, have been canceled.
Once the FWD is available, review it to determine:

1. Which specific claims, if any, were found unpatentable. If the asserted claims are among those canceled, this provides a strong defense. Quote the disposition directly from the FWD in your legal arguments.
2. The Board's reasoning for both patentable and unpatentable claims.
3. The prior art references considered by the Board.

You can search for the Final Written Decision on the USPTO PTAB E2E system using the proceeding number IPR2025-00191: https://developer.uspto.gov/ptab-e2e.
Additionally, monitor the Federal Circuit's docket for any potential appeal of this FWD, which would be filed by either party.

Inventors

• Mei Lan GUO (Yangtze Memory Technologies Co Ltd)
• Yushi Hu (Yangtze Memory Technologies Co Ltd)
• Ji Xia (Yangtze Memory Technologies Co Ltd)
• Hongbin Zhu (Yangtze Memory Technologies Co Ltd)

Original assignee

Yangtze Memory Technologies Co Ltd (YMTC) is an integrated device manufacturer (IDM) specializing in the design, production, and sale of 3D NAND flash memory chips. They ship products such as 3D NAND wafers, dies, embedded memory solutions, consumer and enterprise solid-state drives (SSDs) for applications including mobile devices, PCs, and data centers. YMTC has successfully mass-produced 32-layer, 64-layer, 128-layer, and 232-layer 3D NAND chips. As of 2026, YMTC is an operating company with rapid revenue growth and plans for an initial public offering (IPO). They are also actively working with Chinese semiconductor equipment manufacturers due to U.S. trade sanctions, but still rely on Western manufacturers.

Assignment timeline

Based on a search of the USPTO Assignment Center for patent US11581322, there are no recorded assignments for this patent after its initial assignment to Yangtze Memory Technologies Co Ltd. The Google Patents legal events also indicate that the application was assigned to Yangtze Memory Technologies Co Ltd on 2020-11-21, which is the filing date of the application. This suggests that the patent has remained with its original assignee since its inception.

Timeline diagram

timeline
    title Ownership of US 11581322
    2018 : Priority date
    2020 : Application filed
         : Assigned to Yangtze Memory Technologies Co Ltd
    2023 : Patent Issued

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The patent remains with Yangtze Memory Technologies Co Ltd, an operating company that designs, produces, and sells 3D NAND flash memory. There is no evidence of transfer to a licensing-only LLC.
2. Known asserter in the chain — Not present. Yangtze Memory Technologies Co Ltd is not listed as a known NPE or patent asserter by public lists.
3. Repeat correspondent across the chain — Not present. There are no recorded assignments in the USPTO Assignment Center for this patent beyond the initial assignment to the original assignee.
4. Cascading transfers — Not present. There are no recorded assignments in the USPTO Assignment Center for this patent beyond the initial assignment to the original assignee.
5. Pre-litigation transfer — Unclear. While the patent has litigation associated with it (multiple US cases filed in California Northern and Eastern District Courts, and a PTAB case IPR2025-00191), there are no recorded assignments immediately preceding these litigations [cite: https://patents.google.com/patent/US11581322/en]. Without assignment records, it's impossible to confirm a pre-litigation transfer.
6. Bankruptcy fire-sale — Not present. Yangtze Memory Technologies Co Ltd is an active, operating company.
7. Privateering — Not present. There is no evidence of YMTC transferring the patent to an NPE for assertion on their behalf.
8. Defensive aggregator (anti-NPE) — Not present. The patent is held by Yangtze Memory Technologies Co Ltd, an operating company.

Verdict

Operating-company assertion
The patent US11581322 remains with its original assignee, Yangtze Memory Technologies Co Ltd, which is an active integrated device manufacturer of 3D NAND flash memory products. The Google Patents page for US11581322 indicates ongoing litigation (multiple US district court cases and a PTAB IPR), suggesting the operating company is asserting its patent rights.

Verification: https://assignmentcenter.uspto.gov/ (Search by patent number: 11581322)

The provided patent text for US11581322B2 does not contain a distinct "References Cited" section listing unrelated prior art patents. Instead, it includes a "CROSS REFERENCE TO RELATED APPLICATIONS" section, which details the direct antecedents in the patent's priority chain. These related applications, while not "prior art" in the conventional sense of independent inventions, are critically relevant to the patent's prosecution and validity, as they establish the priority date for the claimed subject matter.

Below are the details of the related applications cited within US11581322B2, interpreted as the "most relevant prior art" citations in the context of documents cited directly by the patent itself.

US Patent 11581322: Three-dimensional memory devices having through array contacts and methods for forming the same

• Filing Date: 2020-11-21 (for US application Ser. No. 17/100,847, which led to US11581322B2)
• Publication Date: 2023-02-14

Cited Related Applications:

1. U.S. application Ser. No. 16/745,342

• Full Citation: U.S. application Ser. No. 16/745,342, filed on January 17, 2020, entitled "THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH ARRAY CONTACTS AND METHODS FOR FORMING THE SAME".
• Publication/Filing Date: January 17, 2020
• Brief Description: This is a divisional application in the patent family leading to US11581322B2. It describes three-dimensional (3D) memory devices that feature through array contacts (TACs) and methods for their fabrication. The invention aims to enhance memory cell density and reduce manufacturing costs by developing TACs that are not enclosed by traditional barrier structures.
• Potential Anticipation (35 U.S.C. § 102): As a direct parent application to US11581322B2 (which is a divisional of this application), its disclosure generally serves to establish priority for the claims of US11581322B2. Therefore, if the claims of US11581322B2 are fully supported by the disclosure of U.S. application Ser. No. 16/745,342 and are entitled to its filing date, this application would not typically act as anticipating prior art under 35 U.S.C. § 102 against those claims. However, if any claims in US11581322B2 were determined not to be entitled to the priority date of U.S. application Ser. No. 16/745,342, and if this application was published before the effective filing date of those particular claims, then its disclosures could potentially anticipate those specific claims under 35 U.S.C. § 102.

2. U.S. application Ser. No. 16/149,103

• Full Citation: U.S. application Ser. No. 16/149,103, filed on October 1, 2018, entitled "THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH ARRAY CONTACTS AND METHODS FOR FORMING THE SAME".
• Publication/Filing Date: October 1, 2018
• Brief Description: This application is a divisional of International Application No. PCT/CN2018/101482 and a grandparent application in the priority chain for US11581322B2. It discloses 3D memory devices with through array contacts (TACs) and associated fabrication methods, focusing on similar objectives as its progeny: increasing memory density and simplifying manufacturing processes by eliminating barrier structures.
• Potential Anticipation (35 U.S.C. § 102): Similar to the above, as an earlier application in the priority chain for US11581322B2, its disclosure typically establishes the priority date for the claimed subject matter. If the claims of US11581322B2 are fully supported by this disclosure and are entitled to its filing date, this application would generally not act as anticipating prior art under 35 U.S.C. § 102 against those claims. However, if certain claims of US11581322B2 were found not to be entitled to the priority date of U.S. application Ser. No. 16/149,103, and if this application was published before the effective filing date of those claims, then its disclosures could potentially anticipate those specific claims under 35 U.S.C. § 102.

3. International Application No. PCT/CN2018/101482

• Full Citation: International Application No. PCT/CN2018/101482, filed on August 21, 2018, entitled "THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH ARRAY CONTACTS AND METHODS FOR FORMING THE SAME".
• Publication/Filing Date: August 21, 2018
• Brief Description: This International Application is the earliest application in the priority chain for US11581322B2. It presents 3D memory devices with through array contacts (TACs) and methods for their formation, highlighting advancements in memory cell density and cost reduction by designing TACs without barrier structures.
• Potential Anticipation (35 U.S.C. § 102): This International Application serves as the foundational priority document for US11581322B2. Assuming the claims of US11581322B2 are fully supported by this disclosure and are entitled to its priority date of August 21, 2018, this application would not act as anticipating prior art under 35 U.S.C. § 102 against those claims. This application is crucial for establishing the earliest possible effective filing date for the inventive subject matter. If, hypothetically, claims in US11581322B2 were not entitled to this priority date and this PCT application was published before the effective filing date of such non-priority-entitled claims, then its disclosures could potentially anticipate those claims under 35 U.S.C. § 102.

I cannot perform an obviousness analysis of US patent 11581322 under 35 U.S.C. § 103, as the provided patent text does not contain a "Prior Art" section listing specific prior art references (e.g., other patents or publications) that could be combined to establish obviousness. The "Prior art keywords" section lists general terms, but these are not specific documents or inventions suitable for an obviousness analysis. Therefore, I am unable to identify combinations of prior art references or explain the motivation to combine them.