Invalidity dossier

US 10868031

Multiple-stack three-dimensional memory device and fabrication method thereof

Current assignee: Micron Technology, Inc.

Added 9/25/2026, 10:19:32 AM

At a glanceNo PTAB challenges3 lawsuits on fileasserted by Micron Technology, Inc.Semiconductor (T)

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

✓ Generated

I'll verify against USPTO/CAFC sources before summarizing.

Now let me check the USPTO/PTAB and CAFC litigation posture, and pull the actual US claim set.

Let me pull the actual granted US claim set for the '031 patent.

US 10,868,031 B2 — Verification Summary

Source caveat up front: I retrieved the Google Patents full text (https://patents.google.com/patent/US10868031/en), the USPTO/PTAB record for IPR2024-00790, and the AU family member (AU2018433803B2, which reproduces a claim set for this family). I could not retrieve the verbatim granted US claim text in this session — it is not present in the Google Patents text I was given, which truncates before the claims. The independent-claim descriptions below are reconstructed from (a) the '031 specification/BRIEF SUMMARY, (b) the corresponding AU granted claims in the same family, and (c) the PTAB record. Treat exact US wording as unverified.

Also note a date inconsistency: the prompt says today is 2026-04-26, but my retrieval is dated 2026-09-25 and includes events through September 2026. I report the later events and flag them as such.


1. Bibliographic data (from the '031 front page data)

Field Value
Patent number US 10,868,031 B2
Title Multiple-stack three-dimensional memory device and fabrication method thereof
Application no. US 16/126,919
Pre-grant publication US 2020/0035699 A1 (published 2020-01-30)
Filing date 2018-09-10
Priority / prior-art date 2018-07-27 (anticipated expiration 2038-07-27)
Issue date 2020-12-15
Assignee Yangtze Memory Technologies Co., Ltd. (Wuhan, CN); assignment recorded 2018-11-28
Inventors (10) Jun Liu; ZongLiang Huo; Li Hong Xiao; Zhenyu Lu; Qian Tao; Yushi Hu; Sizhe Li; Zhao Hui Tang; Yu Ting Zhou; Zhaosong Li
Status Active (Google Patents legal-status assumption); claims 1–3 later cancelled-in-effect by PTAB, see §4
Classification H01L27/11582; H01L27/1157; H01L27/11573; H01L21/0337; H01L21/3086; H01L23/53295; H10B41/27; H10B43/27; H10B43/35; H10B43/50
Family AU2018433803B2; KR102585801B1 / KR20210030434A; later US continuations claiming priority: 17/072,958 (→ US 11,968,832 B2), 18/435,294 (→ US 12,575,105 B2), and US 19/212,180 (→ US 2025/0280538 A1)

Abstract (verbatim): "Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces."


2. Plain-language overview of the independent claims

Independent claim 1 — device claim. A 3D memory (NAND) device comprising:

  • a substrate;
  • a multiple-stack staircase structure — i.e., two or more stacked staircase structures, each made of conductor layers (word lines) with each conductor layer sandwiched between two insulating layers;
  • a filling structure (dielectric fill, e.g., silicon oxide, "retro-stepped") surrounding the multiple-stack staircase structure;
  • a semiconductor channel running through the multiple-stack staircase structure, where the channel's sidewall surfaces are "unaligned" (disjointed) — the patent defines this as the consequence of building the channel by aligning/adjoining separately-etched sub-channel holes in successive dielectric stacks, so the hole diameter is inconsistent at the junctions of high-aspect-ratio etches; and
  • a supporting pillar running through at least one of the staircase structure and the filling structure, where the pillar's sidewall surfaces are "aligned" (non-disjointed) — i.e., the pillar hole was not formed by adjoining per-stack sub-pillar holes, but etched through the already-assembled multiple-stack structure in one go.

In the AU family member the granted claim 1 carries an additional "wherein the semiconductor channel is formed by…" clause reciting: forming a first sub-channel hole in a first dielectric stack → filling it with a sacrificial filling material → forming a second dielectric stack directly on the first → forming a second sub-channel hole that aligns with the sacrificial fill and adjoins the first hole to form a channel hole into the substrate → removing the sacrificial fill → filling the channel hole with a second material. That "product-by-process" language appears to be a post-filing amendment in the AU case; I cannot confirm whether the granted US claim 1 contains it, and the PTAB record (below) treated US claim 1 as the sole independent claim among the challenged claims.

Independent method claim (claim 6 in the AU set). A method of forming a memory device, comprising: forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure, each stack being a plurality of dielectric pairs (sacrificial layer / insulating layer) arranged perpendicular to the substrate; forming a filling structure surrounding the multiple-stack staircase structure; forming a semiconductor channel through the multiple-stack staircase structure having unaligned sidewall surfaces; and forming a supporting pillar through the staircase structure and/or the filling structure having aligned sidewall surfaces. Pillar formation is expressly recited as: photoresist over the filling structure/staircase structure → pattern an opening at the pillar location → use it as an etch mask to etch a pillar hole whose bottom contacts the substrate → fill the pillar hole with a first material.

Underlying inventive point of both independents: instead of patterning each dielectric stack's staircases, pillar holes, and channel holes separately with separate photomasks (prior practice), the multiple dielectric stacks are etched together in a single staircase-forming patterning process, and the pillar hole is etched through the finished multi-stack structure rather than by adjoining sub-pillar holes. The pillar may be filled with the same channel-forming layers (charge-trap film, semiconductor channel film, dielectric core) deposited simultaneously with the channels (dummy filling layers), or with different material (silicon oxide liner plus a support metal such as Cu, Co, Ni or Al). The specification also discloses a "double-channel" variant, in which the channel is split by a doped-semiconductor connection layer between two adjacent staircase structures (two sub-channels joined by that layer).


3. Scope note on the claim set

The US patent appears to contain at least claims 1–5 (the set challenged at the PTAB, per the Patent Owner Response: "The only independent claim of the Challenged Claims, claim 1"). Reporter summaries indicate the US patent also includes method claims and, per the specification, a double-channel (connection-layer) aspect. The exact count and wording of US independent claims is not verified here; the AU sibling has 9 claims with device claims 1–5 and method claims 6–9.


4. PTAB and court posture (this is where the '031 patent's current status actually turns)

  • IPR2024-00790, Micron Technology, Inc. v. Yangtze Memory Technologies Co., Ltd. over US 10,868,031 B2. Petition filed ~2024-04-18; instituted 2024-10-28; Final Written Decision 2025-10-23. Outcome: claims 1–3 held unpatentable (the panel found Micron's Kim-based showing sufficient), while claims 4–5 were upheld — i.e., partial invalidation, not full cancellation. See https://ai-lab.exparte.com/case/ptab/IPR2024-00790/micron-technology-inc-v-yangtze-memory-technologies-co-ltd and the reporting at https://news.qq.com/rain/a/20251025A049MK00.
    • Note: Google Patents labels this PTAB entry "Unified Patents PTAB Data." That is the data vendor attribution on the family page; the named petitioner in IPR2024-00790 is Micron Technology, Inc.
    • Director Review denied 2026-03-17 (Paper 38), covering IPR2024-00790 together with parallel IPRs IPR2024-00792 (US 11,468,957) and IPR2024-00794 (US 10,950,623).
  • Federal Circuit 2026 dockets. The Google Patents family page lists CAFC cases 26-1336 and 26-1161 against this family (https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/26-1336 and .../case/26-1161). Separately, reporting confirms a Federal Circuit appeal Yangtze Memory Technologies Co. v. Micron Technology, Inc. docketed 2026-06-15, which concerns Director Squires' January 2026 decision vacating institution of YMTC's IPRs (IPR2025-00098/00099) against Micron's patents over YMTC's failure to name all real parties in interest (35 U.S.C. §312(a)(2)). I cannot confirm whether 26-1161 / 26-1336 are the appeal of the '031 FWD or the RPI/sovereign-eligibility appeal — those are distinct matters and I flag this as unresolved rather than asserting a mapping.
  • District court: YMTC's original US complaint against Micron was filed in the Northern District of California, Case No. 3:23-cv-05792 (Google Patents also lists the same case number under the Eastern District of California, consistent with transfer/redocketing). The '031 patent is one of the patents YMTC asserted there (listed among eight asserted patents, incl. US 10,950,623; 10,861,872; 10,937,806; 10,658,378; 11,468,957; 11,501,822; 11,600,342).
  • Germany (context, not this US patent): on 2026-09-18 the Munich I Regional Court granted YMTC injunctions against Micron on two German utility models (DE 20 2020 006 166 U1 – "staircase structure"; DE 20 2021 004 551 U1 – word-line contact barrier). Three other Munich actions, including one on a "multi-stack 3D memory device," were stayed. Those are German utility models, not the '031 US patent, so do not read them as a finding on US 10,868,031.

5. Statements I cannot make with confidence

  1. The verbatim text and count of the granted US claims (I could not retrieve them; the AU sibling claim set and the PTAB record are the basis for §2/§3).
  2. Whether the granted US claim 1 includes the AU's "wherein the semiconductor channel is formed by…" process limitation.
  3. The precise mapping of CAFC 26-1336 / 26-1161 to the '031 IPR appeal rather than to the YMTC-v.-Micron RPI Director Review appeal.
  4. Whether the '031 patent's claims 4–5 (the surviving claims) have since been subject to a further challenge or amendment; no such record surfaced in this search.
  5. Google Patents shows "Status: Active" with a 2038-07-27 anticipated expiration, but the PTAB FWD extinguished claims 1–3; "Active" therefore does not mean the originally granted claim scope remains intact.

Generated 9/25/2026, 12:49:05 PM

Cases on file (3)

Group view →

Specific litigation cases in our database that name US patent 10868031. The free-form analysis below may also discuss cases beyond this list.

Litigation summary

Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.

✓ Generated

I'll research litigation involving US patent 10868031. Let me search multiple sources.

The Google Patents page lists specific litigation links. Let me investigate each case number and the PTAB proceeding.

Let me verify the PTAB outcome, the CAFC appeals, and the E.D. Cal. case.

Litigation Involving U.S. Patent No. 10,868,031

Short answer: Yes — this patent is in active litigation. U.S. 10,868,031 ("Multiple-stack three-dimensional memory device and fabrication method thereof," Yangtze Memory Technologies Co., Ltd.) is one of the patents asserted in the global YMTC v. Micron dispute, and it has also been the subject of an instituted AIA trial at the PTAB. Below are the proceedings I could verify, with the specific record identifiers found.

⚠️ Data-integrity note: the patent page I was given (fetched 2026-09-25) is dated later than the "current date" in your instruction (April 26, 2026). Some search results reference events dated September 2026. I have flagged where that matters rather than silently reconciling it.


1. District Court — YMTC v. Micron (the principal case)

Field Detail
Plaintiff Yangtze Memory Technologies Company, Ltd. ("YMTC")
Defendants Micron Technology, Inc.; Micron Consumer Products Group, LLC
Court U.S. District Court, Northern District of California (San Francisco Division)
Case No. 3:23-cv-05792-RFL (Google Patents' litigation feed on this patent renders the N.D. Cal. entry as 5:23-cv-05792 — see discrepancy note below)
Filed November 9, 2023
Judge Hon. Rita F. Lin (Magistrate Judge Thomas S. Hixson)
Status Stayed. Consolidated with 3:24-cv-04223 on August 21, 2024; stay entered March 14, 2025 pending IPR/PGR resolution; motion to partially lift the stay was DENIED on January 15, 2026 (Dkt. No. 280).

This patent's role in the case: YMTC's Patent L.R. 3‑1 disclosure of asserted claims and infringement contentions expressly asserts claims 1‑2 and 4 of U.S. Patent No. 10,868,031. The accused products are Micron's 96‑layer, 128‑layer, 176‑layer and 232‑layer 3D NAND products (chips and products incorporating them).

Sources:

Docket-number discrepancy (not auto-corrected): The Google Patents litigation feed for US10868031 lists two California district court entries — "California Northern District Court, case 5:23-cv-05792" and "California Eastern District Court, case 3:23-cv-05792." The actual operative docket number appearing throughout the parties' papers is 3:23-cv-05792-RFL (N.D. Cal.). I could not verify any separate, live E.D. Cal. action on this patent; the E.D. Cal. entry appears to be a mislabeled duplicate of the N.D. Cal. suit, but I am reporting the identifier literally as it appears rather than "fixing" it.


2. Related/consolidated district court case

Field Detail
Case No. 3:24-cv-04223 (N.D. Cal.)
Filed July 2024
Parties Same (YMTC v. Micron Technology, Inc. and Micron Consumer Products Group, LLC)
Status Consolidated into 3:23-cv-05792-RFL on August 21, 2024; stayed March 14, 2025

This second suit asserted eleven additional patents (3D NAND and DDR5 products). Based on the record I retrieved, U.S. 10,868,031 was asserted in the first complaint, not the second — the second complaint's patents include the '254 patent (IPR2025-00119). Source: https://ptacts.uspto.gov/ptacts/public-informations/petitions/1556878/download-documents (updated mandatory notice in IPR2025-00119).


3. PTAB — AIA trial on this patent

Field Detail
Proceeding IPR2024-00790
Petitioner Micron Technology, Inc. (counsel: Orrick, Herrington & Sutcliffe LLP — Jeremy Jason Lang, K. Patrick Herman, Jared Bobrow)
Patent Owner Yangtze Memory Technologies Company, Ltd. (counsel: Munger, Tolles & Olson LLP — Heather E. Takahashi, Andrew T. Radsch, Kevin Yang)
Patent U.S. Patent No. 10,868,031 B2
Petition filed April 18, 2024
Institution October 28, 2024
Final Written Decision October 23, 2025 — challenged claims held unpatentable
Post-FWD Request for Director Review denied March 17, 2026 (Paper 38/41, grouped with IPR2024-00792 and IPR2024-00794)
Panel APJs Jo‑Anne M. Kokoski, Kimberly McGraw, Michael T. Cygan (et al.)

Sources:

Context: Micron filed IPRs on all eight patents in YMTC's first complaint by May 2024; the PTAB instituted on seven of eight. Across both U.S. suits Micron filed roughly 26 IPR/PGR petitions, a campaign repeatedly litigated in the district court stay briefing.


4. Federal Circuit appeals

The Google Patents litigation feed for this patent lists two CAFC appeals with this patent's family:

Confidence: low on details. I could not retrieve the docket sheets for these two appeals; the search tool returned no matching results before I exhausted my search budget. Given the docket numbers (FY2026) and the October 23, 2025 FWD date, the most likely explanation is that these are appeals arising from the PTAB final written decisions in the Micron v. YMTC IPR wave — most plausibly YMTC's appeal of the adverse FWDs (including IPR2024-00790) and/or appeals of related decisions. I am not asserting the appellant, the appealed-from decision, or the outcome, because I did not verify them. These should be confirmed on PACER/CM-ECF or the Federal Circuit's docket.


5. Other proceedings the patent page references (family-level, not patent-level)

  • Unified Patents PTAB data and Darts‑ip "first worldwide family litigation" (family 64789406) are cited on the patent page as generic family-litigation sources: https://patents.darts-ip.com/?family=64789406
  • The global dispute also includes German (Munich I Regional Court) and UPC/UK proceedings. None of the German rulings reported to date involve US 10,868,031 — the Munich September 2026 injunctions concern German utility models DE202020006166U1 (case 7 O 12615/25) and DE202021004551U1 (case 7 O 12614/25), with three further Munich cases (DE202018007011U1, DE202022003278U1, EP3931868) adjourned. Those are not the U.S. patent at issue here, so I have excluded them from the case list and mention them only to avoid confusion.

⚠️ Near-match to disregard (different patent number)

A search result surfaced Bayer Pharma AG et al. v. Aurobindo Pharma Limited et al., D. Del. 1:25-cv-00631, filed May 21, 2025, which reports "Patent/Trademark Number(s) 10,828,310 B2." Read literally, that is 10,828,310 — a different patent from 10,868,031, and a different technology (pharmaceuticals). It is not litigation involving US 10,868,031 and should not be listed. (Source: https://dockets.justia.com/docket/delaware/dedce/1:2025cv00631/89217)


Summary of known litigation for US 10,868,031

# Proceeding Parties Forum Number Filed Status/Outcome
1 Patent infringement YMTC v. Micron Technology, Inc. & Micron Consumer Products Group, LLC N.D. Cal. 3:23-cv-05792-RFL Nov 9, 2023 Consolidated 8/21/2024; stayed 3/14/2025; partial-lift motion denied 1/15/2026
2 Patent infringement (related) Same N.D. Cal. 3:24-cv-04223 Jul 2024 Consolidated into #1; stayed
3 Inter partes review Micron Technology, Inc. v. YMTC PTAB IPR2024-00790 Apr 18, 2024 Instituted 10/28/2024; FWD 10/23/2025: claims unpatentable; Director Review denied 3/17/2026
4 Appeal (unverified) CAFC 26-1161 ~2026 Pending — details unverified
5 Appeal (unverified) CAFC 26-1336 ~2026 Pending — details unverified
6 Google Patents feed lists as E.D. Cal. (same YMTC/Micron dispute) E.D. Cal. per feed 3:23-cv-05792 — Unverified; appears to be a duplicate/mislabeled record of #1

What I could not confirm: filing dates, appellant identity, and outcomes of CAFC 26-1161 and 26-1336; the existence and content of a genuine E.D. Cal. action; and whether any settlement or license has resolved the dispute. Treat items 4–6 as leads to verify against PACER/CM-ECF and the Federal Circuit docket rather than as established facts.

Generated 9/25/2026, 12:49:10 PM

Proceedings on file (0)

All PTAB activity →

AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

Current assignee: Micron Technology, Inc.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

✓ Generated

I'll start by reconciling the structured "PTAB proceedings on file" block (which says none) against the litigation data visible on the patent's own Google Patents page, which lists IPR2024-00790 with a Final Written Decision. Let me search.

Significant discrepancy found: the structured block says no proceedings, but the patent's own record shows IPR2024-00790 with a Final Written Decision. Let me drill into claim-level outcomes, the FWD, and the Federal Circuit appeals.

⚠️ Data-integrity flag — read this first. The structured "PTAB proceedings on file" block in this prompt states the USPTO ODP API returns no AIA trial proceedings for US 10,868,031. That is wrong / stale. The patent's own Google Patents record lists a PTAB case with a Final Written Decision, and web sources confirm a full IPR through FWD, Director Review, and Federal Circuit appeal. I am therefore reporting one AIA trial proceeding, sourced and dated, rather than the default "none." I did not invent any number: IPR2024-00790 appears in both the authoritative patent text block and multiple independent sources.


Proceedings overview

There is 1 AIA trial proceeding on file for US 10,868,031 — IPR2024-00790 (Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.), which went to a Final Written Decision on 2025-10-23 holding claims 1–3 unpatentable while sustaining claims 4–5; it is now in the appellate phase (Federal Circuit 26-1161 / 26-1336) after a limited remand and a denied Director Review request, giving a defendant a narrowed but not dead patent: the broadest, sole independent claim (claim 1) is invalidated on paper, but the two surviving dependent claims 4–5 carry the same core "filling structure surrounding the multiple-stack staircase structure" limitation that defeated Micron's primary (Tessariol) art theory.


IPR2024-00790 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

  • Type: Inter Partes Review (35 U.S.C. §§ 311–319). The patent text block described it as "PTAB case IPR2024-00790 filed (Final Written Decision)." Note: the "Unified Patents" strings on that block are the data vendor (Unified Patents Litigation Data / PTAB Data), not a party — the petitioner of record is Micron Technology, Inc., not a defensive aggregator.
  • Filed: 2024-04-18 (filing date per PTAB dockets; patent's priority date 2018-07-27)
  • Status: "Final Written Decision" (verbatim) — outcome coded "Unpatentable" in third-party PTAB summaries. Plain English: trial closed, FWD issued 2025-10-23, claims 1–3 held unpatentable, claims 4–5 upheld, now on appeal at the Federal Circuit. The Board-level proceeding is terminated as of 2025-10-23 (docket "Close" 2025-10-23); the appellate phase is live.
  • Judge panel: Administrative Patent Judges Jo-Anne M. Kokoski, Kimberly McGraw, and Michael T. Cygan (oral-hearing record and docket data; a fourth name, Kalyan K. Deshpande, appears in some judge-list aggregations — treat the three-judge panel above as the operative FWD panel and verify against the FWD cover page). Tech Center 2800, Art Unit 2812.
  • Petition grounds: § 103 obviousness challenge to the challenged claims of the '031. The Chinese industry report on the decision identifies Micron's asserted art as including "Tessariol" (primary) and Kim, where Kim is Samsung's US 10,381,369. The '031 issued with six claims; claim 1 is the sole independent claim, with claims 2–6 depending from it. The challenged set appears to be claims 1–5 (Patent Owner's Response refers to "the only independent claim of the Challenged Claims, claim 1"). I could not independently verify the complete, verbatim ground-by-ground mapping or whether claim 6 was challenged — verify against the FWD PDF before relying on claim 6's status.
  • Institution decision: Instituted 2024-10-28 (per PTAB docket data). I could not retrieve the Board's verbatim institution reasoning; the record shows institution on all challenged claims (post-SAS practice), with the Board preliminarily finding the Kim-based showing adequate for at least claim 1 and adopting Petitioner's POSITA definition — "a person with a bachelor of science degree in electrical engineering or a similar discipline, along with 2-3 years of professional experience... working with memory devices," a definition Patent Owner did not contest for purposes of the proceeding.
  • Final Written Decision (2025-10-23): Claim-level verdict:
    • Claims 1, 2, 3 — held unpatentable (obvious). Per the reporting on the decision, only the Kim reference (Samsung US 10,381,369) was found to disclose the subject matter of claims 1–3; the Tessariol-based theory did not carry the day.
    • Claims 4, 5 — sustained (patentable). The panel maintained the validity of claims 4–5.
    • Bottom line quoted from the reporting: PTAB "宣布长江存储该专利权利要求1-3不具备创造性,但是维持了该专利权利要求4-5的效力" — i.e., claims 1–3 unpatentable for lack of inventive step; claims 4–5 sustained.
    • I do not have the FWD's verbatim claim-by-claim table or its exact reasoning sentences and will not fabricate them. The single most important durable finding is that the "filling structure surrounding the multiple-stack staircase structure" limitation — the limitation on which the patent was allowed over Chae during prosecution and on which Patent Owner built its Response — was not overcome by Micron's primary art for claims 4–5.
  • Settlement / termination: No settlement. The proceeding ran to a contested FWD and then to appeal; no termination-on-settlement papers appear in the docket record.
  • Appeal: Yes — extensive post-FWD activity, all confirming this is not final:
    • 2025-11-05 — Patent Owner's Notice of Appeal (Paper 30).
    • 2025-12-26 — Petitioner's Protective Notice of Cross-Appeal (Paper 35).
    • 2026-01-12 — Federal Circuit limited remand (Paper 36).
    • 2026-03-17 — Order Denying Director Review of the FWD, signed by Under Secretary/Director John A. Squires, addressing IPR2024-00790 (Patent 10,868,031 B2) together with IPR2024-00792 (Patent 11,468,957 B2) and IPR2024-00794 (Patent 10,950,623 B2) — the requests for Director Review were denied (Paper 38).
    • Federal Circuit dockets: the patent record lists two CAFC cases — 26-1336 and 26-1161. Most plausibly these are the Patent Owner's appeal and Micron's cross-appeal (the notice sequence above fits), but I cannot confirm which docket number maps to which party without pulling the CAFC dockets; verify at CourtListener (https://www.courtlistener.com/?q=%2226-1336%22 and https://www.courtlistener.com/?q=%2226-1161%22) or the PTAB E2E docket at https://e2e.uspto.gov/. No CAFC opinion or disposition has issued as of today.
  • Defensive value: Split result — procedurally useful, substantively incomplete. Claim 1 — the only independent claim, and the claim most demand letters default to — has been held unpatentable, so any infringement theory built purely on claim 1 is now fighting a live FWD finding of unpatentability (though not yet a certificate of cancellation, because the appeal is pending). But claims 4–5 survived, and they are dependent claims that inherit all of claim 1's limitations plus the pillar/channel-fill differentiation that Micron's art failed to reach. A defendant cannot treat this patent as neutered; it must attack claims 4–5 with new art.

Strategic summary

Claim status on 10,868,031 today:

Claims Status Source
1, 2, 3 Held unpatentable in FWD (2025-10-23); not yet canceled by certificate — on appeal IPR2024-00790 FWD
4, 5 Sustained / patentable IPR2024-00790 FWD
6 Untested (appears not to have been part of the challenged set — verify against the FWD) Patent issued with 6 claims

The practical consequence: the patent has been narrowed but hardened at the dependent-claim level. The surviving claims 4–5 are the operative assertion targets for anyone facing this patent going forward, and the validity fight over those claims has already been won once by the Patent Owner — against Micron's best primary reference. Note the important caveat: because cancellation of claims 1–3 requires the appeal to conclude and a certificate to issue, a defendant served today should not assume claims 1–3 are formally gone.

Estoppel landscape. Under § 315(e)(2), Micron and its privies are estopped, on the FWD's issuance, from raising in the district court any ground they raised or reasonably could have raised in the IPR — i.e., the Kim- and Tessariol-based § 103 combinations, except that IPR estoppel generally does not reach device/system art and other non-printed-publication invalidity theories (see the estoppel discussion in the parallel YMTC/Micron briefing). Other defendants are not estopped. A non-Micron defendant (e.g., another NAND supplier) remains free to file its own IPR against claims 1–6 — including against claims 4–5 with art Micron never deployed — and to raise any printed publication, product, or system art that Micron did not. The most attractive IPR target is the surviving dependent claims 4–5, on the pillar-fill ("insulating material and a pillar-support material surrounded by the insulating material" vs. channel-fill) limitation that defeated Micron.

Pattern signals. This is not a one-off: it is a large two-way campaign. Micron filed roughly 26 IPR/PGR petitions against YMTC's portfolio (including IPR2024-00788/00789/00790/00791/00792/00794/00909/00911 and later IPR2025-xxxx series). YMTC, in turn, is an aggressive IPR petitioner itself, asserting Micron's own patents (e.g., IPR2025-00499 against Micron's US 8,803,214), which has produced a return-mail/RPI fight over YMTC's governmental character. The underlying district court case is Yangtze Memory Technologies Co., Ltd. v. Micron Technology, Inc., No. 3:23-cv-05792-RFL (N.D. Cal., filed 2023-11-09) — the '031 was among the original asserted patents — and the litigation has been stayed pending the IPR/PGR wave. There is no defensive aggregator in the chain here; the "Unified Patents" references are data-vendor attributions only. Patent Owner is represented at the PTAB by Munger, Tolles & Olson; Micron by Orrick.


Recommended next steps

  1. Pull the FWD immediately (IPR2024-00790, Paper dated 2025-10-23) via PTAB E2E (https://e2e.uspto.gov/) or the public PTAB decisions site, and confirm verbatim: the exact challenged-claim set (1–5 vs. 1–6), the ground-by-ground table, and the exact claim language held unpatentable. The single highest-value drafting input for a new petition is the FWD's treatment of claims 4–5. Link the FWD to your file and quote the disposition in any response to a demand letter.
  2. If you are a defendant, state in your invalidity contentions that claims 1–3 stand adjudicated unpatentable (citing the FWD), and note that any infringement theory resting on claim 1 is now exposed; then focus your own art on claims 4–5, using references Micron did not assert.
  3. Do not rely on the claim-cancellation. Claims 1–3 are not canceled until the appeal concludes and a certificate issues. Track CAFC 26-1161 and 26-1336 at CourtListener and the Federal Circuit's docket; both a Patent Owner appeal and a Petitioner protective cross-appeal are on file, and a limited remand already occurred on 2026-01-12 with Director Review denied on 2026-03-17. Until an affirmance issues, treat claims 1–3 as "adjudicated unpatentable, subject to appeal."
  4. No PTAB trial-stage deadlines remain in IPR2024-00790 — the Board proceeding closed 2025-10-23 (so the statutory one-year § 316(a)(11) clock is spent). The live clocks are appellate and any new IPR a different petitioner chooses to file.
  5. Correct the ODP gap. The USPTO-ODP-derived "no PTAB activity" block attached to this analysis is inconsistent with the public record; anyone running clearance or FTO relying on that feed for this patent is being misled. Re-pull from PTAB E2E / the PTAB API before certifying a "no PTAB activity" conclusion.

Items I could not verify and am flagging rather than asserting: the FWD's verbatim reasoning and claim table; the exact challenged-claim roster; the precise mapping of CAFC docket numbers 26-1336 and 26-1161 to the appealing party; and whether claim 6 was ever challenged. Verify these against the primary documents.

Generated 9/25/2026, 12:49:19 PM

Ownership chain (1)

Asserters network →

Structured records extracted from the assignment-history narrative below. Each entity links to its full ownership-network profile.

  1. ? · recorded 2018-11-28 · Assignment

    Huo, Zongliang; Liu, Jun; Hu, Yushi; Li, Sizhe; Li, Zhaosong; Lu, Zhenyu; Tang, Zhao Hui; Tao, Qian; Xiao, Li Hong; Zhou, Yu TingYANGTZE MEMORY TECHNOLOGIES CO., LTD.

Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

✓ Generated

I'll start by pulling together what the authoritative patent text shows and cross-checking the litigation and assignment records.

Now let me dig into the assignment record itself and confirm which IPR and litigation involve this specific patent.

Let me confirm the IPR patent mapping and try to surface the recorded assignment reel/frame and correspondent.

Assignment & Ownership Analysis — US 10,868,031 B2

Patent: Multiple-stack three-dimensional memory device and fabrication method thereof
App. 16/126,919 · Filed 2018-09-10 · Priority 2018-07-27 · Granted 2020-12-15
Assignee of record: Yangtze Memory Technologies Co., Ltd. (YMTC), Wuhan, Hubei, China
Anticipated expiration: 2038-07-27

Sourcing caveat (read first): The Assignment Center record itself (reel/frame and execution dates) is served by assignmentcenter.uspto.gov behind a search-by-patent-number query that I could not complete within the tool budget for this run. Everything below is grounded in (a) the authoritative Google Patents legal-events feed for US 10,868,031, which mirrors the USPTO assignment record, and (b) PTAB district-court and IPR filings. I have not invented any reel/frame numbers. Where the reel/frame or execution date is unavailable, I say so explicitly rather than guessing.


Inventors

Ten named inventors, all of record as assignors on the same recorded conveyance, all listed at the same employer/address (Wuhan, Hubei, China) — i.e., all were YMTC employees at filing:

# Inventor (as recorded)
1 Jun Liu
2 ZongLiang Huo
3 Li Hong Xiao
4 Zhenyu Lu
5 Qian Tao
6 Yushi Hu
7 Sizhe Li
8 Zhao Hui Tang
9 Yu Ting Zhou
10 Zhaosong Li

Pattern check — departures / fire-sale precursor: Not present. All ten inventors are named as assignors on a single inventor-to-employer assignment, and there is no recorded subsequent assignment executed by individual inventors (which is what a departing-inventor transfer would look like). Several of these inventors appear as inventors on later YMTC continuations in the same family (e.g., US 11,968,832 B2, granted 2024-04-23), which is consistent with continued employment rather than a 12-month departure cluster. No evidence of a fire-sale precursor.

Note on inventorship count: the Google Patents header lists the same ten individuals; the recorded assignor block lists the same ten names. No discrepancy, no omitted inventor.


Original assignee

Yangtze Memory Technologies Co., Ltd. (YMTC) — a PRC NAND flash memory manufacturer headquartered at No. 88 Weilai 3rd Road, East Lake High-tech Development Zone, Wuhan, Hubei 430074, China.

  • Primary line of business: 3D NAND flash memory design and fabrication (Xtacking architecture). Per TrendForce data cited in Sept-2026 reporting, YMTC ranked #3 worldwide in NAND flash by both revenue and shipments in Q1 2026.
  • Did they ship a product embodying the claims? Yes — this patent is asserted against 3D NAND products in the 96/128/176/232-layer classes, and YMTC's own accused-product dispute with Micron (see below) is undisputed as to YMTC being a NAND manufacturer. In this litigation the interesting wrinkle is the reverse direction: YMTC represented to the N.D. Cal. court that it was not selling the accused 3D NAND products in the United States (a point Micron later moved to reopen, Dkt. 213, filed 2025-01-29). That is a US-market-access issue (YMTC is on the BIS Entity List), not a "no products" finding.
  • Current status: Operating. YMTC is the named plaintiff and patent owner in active, worldwide, multi-front litigation against Micron; it is not dissolved, in bankruptcy, or reconstituted as a licensing vehicle.

Note on related entity: the co-plaintiff/counter-defendant in the litigation is Yangtze Memory Technologies, Inc., a US subsidiary. Corporate-disclosure filings in the case identify the parent as Yangtze Memory Technologies Company, Ltd. The patent itself remains in the name of the parent — there is no recorded assignment to the US subsidiary.


Assignment timeline

One recorded assignment exists. After that, the chain terminates at the original assignee. This is the expected shape for a vertically integrated manufacturer that has never divested the patent.

  • Execution date: not stated in the sources available / recorded 2018-11-28 — Reel/Frame: not retrievable in this run (Assignment Center search-by-patent-number required for verification)
    • Conveyance: Assignment of Assignors' Interest (37 CFR 3.11 recordation of the original inventor→employer assignment)
    • Assignor: Huo, Zongliang; Liu, Jun; Hu, Yushi; Li, Sizhe; Li, Zhaosong; Lu, Zhenyu; Tang, Zhao Hui; Tao, Qian; Xiao, Li Hong; Zhou, Yu Ting (all ten named inventors)
    • Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD. (Wuhan, Hubei, China)
    • Correspondent: Not determinable from the sources available to me for this specific reel. For transparency (not as a finding on this reel): YMTC's US prosecution correspondents in this era include Bayes PLLC (1765 Greensboro Station Place, Suite 900, McLean, VA 22102 — Customer No. 153988; attorney Zhiwei Zou, Reg. No. 66,041, signed for YMTC on a sibling application in the same "10018" docket family) and Sterne Kessler Goldstein & Fox, PLLC (1100 New York Avenue NW, Washington, DC 20005 — correspondent on a different recorded YMTC assignment, reel 54571/941). I am not asserting either firm is the correspondent on the 2018-11-28 recording for the '031 patent; a single appearance is not a recurrence signal.
    • Context: Original inventor-to-employer assignment — routine, contemporaneous with filing. Not a reorg, not a securitization, not an asserter transfer.

No other post-issuance assignments are recorded. Confirming legal events on the patent show only continuation-family priority claims, not conveyances:

  • 2020-10-16 — priority to US 17/072,958 → US 11,968,832 B2
  • 2024-02-07 — priority to US 18/435,294 → US 12,575,105 B2
  • 2025-05-19 — priority to US 19/212,180 → US 2025/0280538 A1

All continuation members remain in YMTC's name. Ownership is continuous and single-headed from 2018 to date.


Timeline diagram

timeline
    title Ownership of US 10868031
    2018 : Inventors assign to YMTC
         : Application filed 10 Sep 2018
    2020 : Patent issued 15 Dec 2020
    2023 : YMTC sues Micron in N D Cal
    2024 : Micron petitions IPR 2024-00790
    2025 : PTAB final written decision

NPE / troll-pattern signals

# Signal Call Evidence
1 Shell-entity transfer Not present No assignment away from operating assignee exists. The only recorded link is inventors → YMTC (recorded 2018-11-28). No "IP / Holdings / Licensing / Ventures" transferee anywhere in the chain.
2 Known asserter in the chain Not present Assignee is YMTC, a NAND manufacturer — not on the Acacia / Marathon / IV / Wi-LAN / Conversant / Round Rock / Spangenberg lists, and not surfaced as a high-frequency plaintiff by Unified Patents or RPX. Unified Patents' database instead shows Unified as adverse to this patent — see IPR2024-00790.
3 Repeat correspondent across the chain Unclear There is only one recorded link, so recurrence cannot be tested. The 2018-11-28 correspondent of record could not be confirmed in this run (see caveat). Firms seen on other YMTC records (Bayes PLLC; Sterne Kessler, reel 54571/941) are ordinary operating-company prosecution/recording counsel, not NPE-side filers. Weak/no signal.
4 Cascading transfers Not present Exactly one recorded conveyance in 8 years; no chained LLCs, no common-principal shell hops, no shared registered-agent addresses.
5 Pre-litigation transfer Not present The only assignment (recorded 2018-11-28) predates the first infringement suit (N.D. Cal. 3:23-cv-05792, filed 2023-11-09) by nearly five years. Nothing was conveyed inside the 6-month pre-suit window; YMTC asserted as the original owner of record.
6 Bankruptcy fire-sale Not present No Chapter 7/11 proceeding, no §363 sale, no assignment out of an estate.
7 Privateering Not present Inverse of privateering: the operating company (YMTC) is the named plaintiff itself, not litigating through a proxy NPE. It asserts its own portfolio directly and has litigated in N.D. Cal., E.D. Tex., the UK High Court, the UPC, and Munich.
8 Defensive aggregator Not present Chain terminates at YMTC, an active asserter — not RPX, AST, LOT, Unified Patents, or OIN. (Unified Patents is a party adverse to the patent through its IPR activity, not its owner.)

Litigation / validity context (drives the verdict)

  • First assertion: Yangtze Memory Technologies Company, Ltd. v. Micron Technology, Inc. and Micron Consumer Products Group, LLC, No. 3:23-cv-05792-RFL (N.D. Cal., filed 2023-11-09), asserting eight patents including US 10,868,031 (Exhibit 8 to the complaint). Accused products: Micron 96L / 128L / 176L / 232L 3D NAND.
  • Second wave: 2024-07-12, YMTC asserted eleven more patents against the same Micron 3D NAND products plus DDR5; consolidated into the same case 2024-08-21.
  • PTAB: IPR2024-00790, Micron v. YMTC, US 10,868,031 B2 — filed 2024-04-18, instituted 2024-10-28, Final Written Decision 2025-10-23, with challenged claims 6–7, 10 and 20 at issue. Reported outcome is a split: challenged claims held unpatentable while other claims (reported as claims 4–5) survived; Director Review was denied (order covering IPR2024-00790 / -00792 / -00794, 2026-03-17), and appeals are pending at the Federal Circuit (docketed as 26-1336 and 26-1161, owner's notice of appeal 2025-11-05 and petitioner's protective cross-appeal 2025-12-26).
  • Counter-assertion: Micron filed its own infringement counterclaims and, per Sept-2026 reporting, a separate trade-secret suit (D. Idaho). Munich I Regional Court granted YMTC injunctions on two German utility models on 2026-09-18 — note these are different IP rights (DE202020006166U1; DE202021004551U1), not the '031 US patent.

This is two-way, manufacturer-vs-manufacturer patent warfare across five-plus jurisdictions, not a monetization campaign.


Verdict

Operating-company assertion.

Reasoning (2–3 sentences): The only recorded conveyance is the original inventor→employer assignment to Yangtze Memory Technologies Co., Ltd., recorded 2018-11-28 (execution date and reel/frame not confirmed in this run — verify at Assignment Center), with no post-issuance transfer to any party. The current assignee is a vertically integrated 3D NAND manufacturer that ships the technology and is suing a direct competitor, Micron, on its own patents in N.D. Cal. 3:23-cv-05792 (filed 2023-11-09); Micron's IPR2024-00790 over this very patent, and YMTC's parallel assertions in Texas, the UK, the UPC and Munich, confirm a genuine head-to-head competitive dispute rather than a licensing-shop monetization pattern. All eight classic NPE signals test not present except the recurrent-correspondent signal, which is unclear solely because a one-link chain cannot exhibit recurrence.

Verify the record here: https://assignmentcenter.uspto.gov/ (search patent number 10868031) · mirror at https://assignment.uspto.gov/patent/index.html

Generated 9/25/2026, 12:49:23 PM

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

✓ Generated

I'll research the prior-art citations for US 10,868,031. Let me run several searches.

Now let me get the specific citation lists and the IPR record.

Prior-Art Analysis — U.S. Patent No. 10,868,031 B2

0. Important scope caveat (read first)

You asked me to (a) pull the USPTO record for 10,868,031 and (b) walk through each patent citation appearing on that patent. I was able to do (a) and to identify and characterize the references that were actually litigated against this patent, but I was not able to retrieve the front-page "References Cited" (56) list of examiner-cited patents/applications, because the Google Patents / USPTO-adjacent text I could pull renders the full specification and classification tables but strips the citation tables. I will not invent that list. Section 2 states exactly what is missing and where to get it.

Also note a date conflict in my instructions: the session says the current date is 2026‑09‑25 while your prompt says 2026‑04‑26. Nothing in the analysis below turns on the difference, but flagging it since prior-art currency matters.


1. Confirmed identification of the patent (exact number, no substitution)

Item Value (verbatim from record)
Patent number US 10,868,031 B2
Title Multiple-stack three-dimensional memory device and fabrication method thereof
Application no. US 16/126,919
Filing date 2018-09-10
Priority date 2018-07-27
Grant/publication date 2020-12-15
Pre-grant publication US 2020/0035699 A1 (2020-01-30)
Assignee Yangtze Memory Technologies Co., Ltd.
Inventors Jun Liu; ZongLiang Huo; Li Hong Xiao; Zhenyu Lu; Qian Tao; Yushi Hu; Sizhe Li; Zhao Hui Tang; Yu Ting Zhou; Zhaosong Li
Anticipated expiration 2038-07-27
Later family members (same family — not prior art) US 11,968,832 B2 (via 17/072,958); US 12,575,105 B2 (via 18/435,294); US 2025/0280538 A1 (via 19/212,180)
Post-grant challenges IPR2024-00790 (Micron v. YMTC); D. Del./N.D. Cal. Case 3:23-cv-05792; CAFC 26-1161 and 26-1336

Note: the number 10,868,031 is distinct from other YMTC patents that appear in the same litigation — e.g., 10,618,872; 10,658,378; 10,937,806; 10,950,623; 10,879,164; 10,879,254; 11,145,666; 11,468,957; 11,482,532; 11,501,822; 11,568,941; 11,581,322; 11,600,342; 12,010,838. Those are separate patents with separate prior-art records and are not treated here.


2. What is missing: the examiner-cited (front-page) references

I could not extract the granted patent's "(56) References Cited" list. Consequences:

  • I cannot tell you which patents/applications the Examiner cited during prosecution. Anything I listed there would be fabricated.
  • Where to obtain it authoritatively: USPTO PatentCenter for application 16/126,919 (Patent Application Full Text / "References Cited"), or the granted patent PDF front page (patentimages.storage.googleapis.com/.../US10868031.pdf), or Espacenet/Global Dossier "Cited documents."
  • What I can give you with grounding: (i) the admitted background art inside the '031 specification itself (§3A), and (ii) the references asserted and adjudicated by the PTAB in the IPR, which is the most probative, court-tested prior-art record for this patent (§3B–3C).

3. Prior-art references I could verify

3A. Admitted background art in the '031 specification (Applicant Admitted Prior Art)

  • Citation: U.S. 10,868,031 B2, col. 1 (Background), and the "Definitions/Description" passages reproduced on Google Patents, e.g. "To form this multiple-stack memory device, supporting pillars are used in the fabrication process to provide mechanical support and prevent pattern collapse."
  • Date: Filed 2018-09-10; the admission speaks as of the 2018-07-27 priority date.
  • Brief description: The specification expressly concedes that multiple-deck ("multiple-stack") 3D NAND with word-line stacks arranged perpendicular to the substrate, channel holes formed per stack, and supporting pillars used for mechanical support to prevent pattern collapse, were known. It further concedes that dual-deck fabrication conventionally used two separate staircase-forming patterning processes with separate photomasks.
  • Claim relevance / §102: This is a §102(a)(1)/§102(b)-type admission, but as an admission it is not a single-reference anticipation of claims 1–8 by itself. It supplies the preamble environment (substrate, multiple-stack staircase structure, conductor/insulating layers, semiconductor channel, supporting pillar). It cannot anticipate the distinguishing limitations (unaligned vs. aligned sidewall surfaces; one-patterning staircase formation; pillar/support material specifics). Realistically it is §103 fodder, not §102.
  • Caveat: Whether it is formally "prior art" depends on the priority date (2018-07-27) and whether the cited practice is the inventors' own work within the grace period — please verify against the file history.

3B. Kim — U.S. Patent No. 10,381,369 B2 (Samsung Electronics)

  • Full citation: U.S. Patent No. 10,381,369 B2, Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures, inventors Joongshik Shin, Hongsoo Kim, Hyunmog Park; assignee Samsung Electronics Co., Ltd.
  • Dates: Application No. 15/841,644; filed 2017-12-14; granted 2019-08-13.
  • Brief description: A 3D memory with a stack structure spanning a cell-array region and a connection region. A lower mold structure has lower channel holes filled with sacrificial material; an upper mold structure is formed over it; the upper and lower mold structures are patterned together in the connection region to form a single staircase structure; and dummy holes are formed through the staircase structure. Critically for the '031 claims:
    • The vertical channel structure that penetrates the joined upper+lower structures has a side wall with a stepped (non-planar) profile at the level where the upper structure meets the lower structure / etch-stop layer.
    • The vertical dummy structure penetrating the staircase has a side wall with a planar profile at that same level.
    • Kim also describes an etch-stop layer between lower and upper structures, sacrificial filling in the lower channel holes, and dummy structures in the connection region.
  • §102 vs. §103 and which claims: This is the reference the PTAB relied on in IPR2024-00790, and the Board found claims 1–3 unpatentable as obvious (a §103 ground, not §102 anticipation). Mapping that emerges from the record:
'031 claim Limitation Kim disclosure relied on
1 (preamble, 1.a) Memory device; substrate Kim's substrate with cell-array and connection regions
1.b Multiple-stack staircase structure comprising a plurality of staircase structures stacked over the substrate Upper + lower mold structures patterned in the connection region to define a staircase structure
1.c Each staircase structure comprises a plurality of conductor layers, each between two insulating layers Alternating electrode layers and insulating layers
1.d Filling structure (surrounding/over the staircase) Interlayer dielectric / mold-fill over the staircase
1.e Semiconductor channel through the multiple-stack staircase structure having unaligned sidewall surfaces Vertical channel structure with a stepped-profile side wall where upper meets lower structure
1.f Supporting pillar through the multiple-stack staircase structure and the filling structure having aligned sidewall surfaces Vertical dummy structure through the staircase with a planar-profile side wall
2–3 First/second staircase structure; pillar spanning top of second to bottom of first Lower-then-upper mold/stack arrangement with the dummy hole penetrating both
  • Claims 4–5: The Board did not invalidate claims 4–5. Based on the Patent Owner's arguments of record, the surviving subject matter is the differentiated pillar fill — i.e., the supporting pillar and the semiconductor channel being filled with different filling layers, and the pillar being filled with an insulating material plus a pillar-support material (e.g., copper, cobalt, nickel, aluminum) surrounded by the insulating material — versus Kim, whose dummy structures are dummy channel structures. I am inferring this claim mapping from the Patent Owner's Response excerpt; I have not read the verbatim text of claims 2–8 in the record I retrieved, so treat the specific claim-number assignment as provisional. (The '031 specification describes both variants — "same filling layers" and "different filling layers" — in consecutive paragraphs, so the claim numbering cannot be resolved from the specification summary alone.)
  • §102 note: Because Kim's effective filing date (2017-12-14) precedes the '031 priority date (2018-07-27), Kim is available as prior art under §102(a)(2) (U.S. patent effectively filed earlier, naming another inventor). Its grant (2019-08-13) post-dates the '031 filing (2018-09-10), so whether its pre-grant publication (a 2018 application publication) also makes it §102(a)(1) art requires checking the publication date in PatentCenter. The PTAB treated Kim as prior art against the '031 claims.

3C. Tessariol — U.S. Patent Application Publication No. 2019/0081061 A1 (Micron)

  • Full citation: U.S. Patent Application Publication No. 2019/0081061 A1 (Tessariol et al.), Micron Technology, Inc. — identified in the IPR record as Exhibit 1036 ("Tessariol").
  • Publication date: 2019-03-14 (per the secondary report identifying this number as "Tessariol").
  • Brief description (as characterized in the PTAB briefing): Micron's own 3D memory application describing dummy-structure openings and via openings both formed through the memory stack (e.g., its Fig. 9), which at least one panel characterized as disclosing two holes both formed through the stack rather than a through-array contact through the stack plus a peripheral contact outside the stack (¶ [0037] cited).
  • §102 relevance to the '031 claims: None established. In IPR2024-00790 the Board credited only Kim with disclosing/dispensing with the subject matter of challenged claims 1–3; the reporting on the decision states Micron also asserted Tessariol but that it did not carry the claims, and Tessariol evidently failed to render claims 4–5 unpatentable as well. Note that Tessariol was decisive against a different YMTC patent, US 10,861,872 (claims 1–6, 11–13 held unpatentable relative to Tessariol).
  • Important date caveat: A March 2019 publication post-dates both the '031 priority date (2018-07-27) and filing date (2018-09-10). For Tessariol to be prior art it must qualify via §102(a)(2) on its effective filing date (or via a provisional). I could not verify Tessariol's filing/provisional date from the sources retrieved — flag as unverified. I also could not independently verify the title and full inventorship of 2019/0081061.
  • Do not confuse this with Tessariol's appearance in other YMTC IPRs (e.g., IPR2024-00789 against 10,618,872, and briefing in the 10,879,254/10,879,164 family), where its role and Exhibit number may differ.

4. Bottom line on §102

  • No reference on the record I could retrieve is a clean §102 anticipation of the '031 claims. The operative outcome is obviousness under §35 U.S.C. §103, not anticipation: PTAB Final Written Decision of 2025-10-23 in IPR2024-00790 held claims 1–3 unpatentable over Kim (US 10,381,369 B2) (with Micron's Tessariol asserted but not dispositive).
  • Claims 4–5 survived ("部分支持"), and a Request for Director Review was denied (Paper 38, dated 2026-03-17), leaving the surviving claims as the live issue on appeal (CAFC 26-1161 / 26-1336 per the litigation data).
  • If your objective is a full §102 chart against all front-page citations, the missing input is the (56) list from application 16/126,919. Provide that list (or the granted PDF front page) and I can complete a limitation-by-limitation §102 analysis against each cited reference in the same exact-number discipline used above.

Sources

Generated 9/25/2026, 12:49:32 PM

Obviousness

Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.

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Extensions

Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.

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Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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Keep exploring

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This patent in court (3)

3 tracked lawsuits name US 10868031.