US 10140028

Here's a concise summary of US patent 10140028:

US Patent 10140028

• Title: Clock mode determination in a memory system
• Current Assignee: Mosaid Technologies Inc
• Inventors: Peter B. Gillingham, Graham Allan
• Filing Date: April 19, 2018 (based on Application number US15/957,120)
• Issue Date: November 27, 2018
• Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

CAFC 2026 Dockets:
A search of CAFC 2026 dockets for patent number US10140028 did not return any specific results in the provided snippets. Therefore, there is no authoritative information about litigation involving this patent in the CAFC dockets for 2026 at this time.

Plain-Language Overview of Independent Claims:

• Claim 1: Semiconductor Device (Based on "First Aspect")
  A semiconductor device designed to receive both a clock signal and input data. It features a configurable input circuit that can operate in two modes:

  1. First Mode: For high-speed operation where the clock signal edges and input data edges arrive at the same time (coincident). In this mode, the circuit generates shifted clock edges to precisely sample the input data within its valid window.
  2. Second Mode: For lower-speed operation where the clock signal edges and input data edges are not coincident. The circuit directly uses these non-coincident edges to sample the input data.
     The device also includes an input pin (a reference voltage pin) that sets which of these two modes the configurable input circuit operates in. If this pin receives a low or high power supply voltage, it sets the second mode. If it receives a reference voltage level (typically between the low and high power supply levels), it sets the first mode and is used by the circuit to sense the logic levels of the incoming data.

• Claim 10: Configurable Memory Device (Based on "Second Aspect")
  A memory device that can be configured to operate in different clock modes, including:

  1. A mode setter that reads the voltage level of a dedicated reference voltage input port. Based on this voltage level, it produces a "mode selection signal."
  2. A clock switch connected to a clock input port. This switch can receive either parallel complementary clock signals (clocks arriving at all memory devices simultaneously) or serial complementary clock signals (clocks passed from one memory device to the next). In response to the mode selection signal, the clock switch generates internal clock signals that match the received parallel or serial clocks.
  3. A configurable data input/output buffer connected to a data input port and the reference voltage input port. If the mode selection signal indicates the serial clock mode, this buffer uses the reference voltage to determine the logic levels of the incoming data.

• Claim 16: Method for Configuring a Clock Operating Mode (Based on "Third Aspect")
  A method for setting up a memory device's clock operating mode, where the memory device receives a reference voltage for sensing data. The method involves:

  1. Setting the level of the reference voltage.
  2. Comparing this reference voltage to a predetermined internal reference voltage. This comparison generates a "mode selection signal" that reflects the outcome.
  3. Based on this mode selection signal, configuring the memory device's clock input buffer to receive either parallel complementary clock signals or serial complementary clock signals.

• Claim 20: Configurable Memory System (Based on "Fourth Aspect")
  A memory system that can be configured to operate with either parallel or serial clock signals. This system includes:

  1. A memory controller.
  2. At least one serially connected memory device. Each memory device has:
     • Clock input ports to receive either the parallel or serial clock signals.
     • A reference voltage input port that receives a reference voltage set to either a specific predetermined level or a power supply level.
     • A mode setter that compares this received reference voltage to a predetermined voltage level and generates a "mode selection signal" based on the comparison.
     • A clock switch circuit connected to the clock input ports. In response to the mode selection signal, this circuit generates internal complementary clock signals that correspond to either the parallel clock signals or the serial complementary clock signals it receives.

Here is a list of known litigation involving US patent 10140028:

1. District Court Litigation

   • Plaintiff(s): Mosaid Technologies Inc.
   • Defendant(s): Infineon Technologies AG, Infineon Technologies Americas Corp.
   • Jurisdiction: U.S. District Court for the Western District of Texas
   • Case Number: 1:25-cv-00436
   • Filing Date: March 25, 2025
   • Current Status: Open; Patent Infringement. Mosaid Technologies Inc. served Infineon Technologies Inc. on March 28, 2025. Infineon Technologies Americas Corp. filed an answer and counterclaim. The case has been reassigned to Judge Alan D. Albright.

2. PTAB Litigation

   • Petitioner(s): Unified Patents (implied from Google Patents listing and general Unified Patents activity in IPRs).
   • Patent Owner: Mosaid Technologies Inc. (as the current assignee of US10140028).
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01456
   • Filing Date: Filed in 2025 (specific date not publicly available)
   • Current Status: Not Instituted - Procedural.

Proceedings overview

One Inter Partes Review (IPR) proceeding has been filed against US Patent 10,140,028. This IPR was denied institution, meaning no claims were ever reviewed on the merits by the Patent Trial and Appeal Board (PTAB). This outcome strengthens the patent's defensive posture, as it has survived an IPR challenge at the institution stage.

IPR2025-01456 — Infineon Technologies Americas Corp. et al. v. Mosaid Technologies Inc.

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Discretionary Denial – The PTAB declined to institute the inter partes review.
• Judge panel: Not publicly available due to discretionary denial.
• Petition grounds: Specific claims, prior art, and statutory bases (§ 102 / § 103) are not detailed in the public record for a discretionary denial where no institution decision on the merits was issued.
• Institution decision: Denied. The PTAB issued a "Discretionary Denial" on 2026-04-17. The specific reasoning for the discretionary denial is not immediately available in public snippets but typically involves factors such as parallel district court litigation, advanced stage of litigation, or inefficient use of Board resources.
• Final Written Decision (if issued): Not applicable. A Final Written Decision is only issued if the IPR is instituted.
• Settlement / termination: Not applicable. The proceeding terminated at the institution stage by discretionary denial.
• Appeal: No appeal to the Federal Circuit regarding a Final Written Decision, as none was issued.
• Defensive value: This proceeding indicates that Infineon Technologies Americas Corp. et al. attempted to challenge the patent at the PTAB but were unsuccessful at the institution stage. For a defendant facing assertion of this patent, this means that the patent has not been weakened by a PTAB ruling, and any IPR-based defense using the same grounds as Infineon would need to overcome the PTAB's reasoning for discretionary denial.

Strategic summary

No claims of US10140028 have been canceled or sustained by the PTAB. The patent has been subjected to one Inter Partes Review, IPR2025-01456, which resulted in a discretionary denial of institution. This means that the PTAB did not proceed to a full review of the patentability of the challenged claims. Consequently, all claims of US10140028 remain untested by a PTAB Final Written Decision on the merits.

Regarding the estoppel landscape, since IPR2025-01456 was denied institution, the statutory estoppel provisions of 35 U.S.C. § 315(e)(2), which apply to grounds raised and claims found unpatentable in a Final Written Decision, do not come into play. However, the petitioner (Infineon Technologies Americas Corp. et al.) and their privies may face a common law or analogous preclusion from asserting the same specific invalidity grounds in district court that were presented in the IPR petition and denied institution. For other potential defendants, all prior art grounds remain available for challenge, subject to the usual statutory and regulatory requirements for filing an IPR petition. There are no clear pattern signals from a single, non-instituted IPR to suggest aggressive PTAB appeals by the patent owner or multiple filings by the same petitioner.

Recommended next steps

• Since IPR2025-01456 resulted in a discretionary denial, there is no Final Written Decision to link to for claim invalidation. The PTAB's decision to deny institution can be found in the USPTO's PTAB E2E system. For IPR2025-01456, the status is "Not Instituted - Procedural". A defendant should review the specific order for discretionary denial to understand the Board's reasoning, as this could inform future invalidity strategies.
• Currently, there are no active PTAB proceedings on file for US10140028 that are proceeding to trial.

Inventors

• Peter B. Gillingham: While specific employer at the time of the earliest priority date (2007-02-16) is not explicitly stated in the patent, the initial applicant for US10140028 was Conversant Intellectual Property Management Inc., which is the rebranded name of Mosaid Technologies Inc.. Mosaid Technologies Inc. historically developed and licensed semiconductor memory technology. It is highly probable that Peter B. Gillingham was employed by Mosaid Technologies Inc. or a related entity.
• Graham Allan: Similarly, it is highly probable that Graham Allan was employed by Mosaid Technologies Inc. or a related entity at the time of the earliest priority date.

Original assignee

The entity named on the issued patent (US10140028B2, granted 2018-11-27) was CPPIB Credit Investments Inc. The patent application (US15/957,120) was filed by Conversant Intellectual Property Management Inc. on 2018-04-19, but then assigned to CPPIB Credit Investments Inc. on 2018-08-22 before grant.

CPPIB Credit Investments Inc. is a wholly-owned subsidiary of the Canada Pension Plan Investment Board (CPPIB), a Canadian asset management organization. Their primary line of business is providing financing solutions, including private debt, loans, and intellectual property-backed investments. They do not ship products embodying the claims of this patent. CPPIB Credit Investments Inc. is currently operating as part of CPPIB.

Assignment timeline

Note: The provided source (Google Patents full text) does not include Reel/Frame numbers, specific conveyance types beyond "Assigned to," or correspondent information. Therefore, these details cannot be provided as requested.

• 2018-08-22 (executed) / recorded N/A — Reel N/A
  • Conveyance: Assignment (implied)
  • Assignor: Conversant Intellectual Property Management Inc
  • Assignee: CPPIB CREDIT INVESTMENTS, INC.
  • Correspondent: N/A
  • Context: Securitization or financing arrangement, as CPPIB Credit Investments is a financial entity involved in intellectual property-backed investments.
• 2020-11-06 (executed) / recorded N/A — Reel N/A
  • Conveyance: Assignment (implied)
  • Assignor: CPPIB CREDIT INVESTMENTS INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: N/A
  • Context: Re-assignment back to the original applicant, potentially after a financing agreement concluded or was restructured.
• 2021-06-16 (executed) / recorded N/A — Reel N/A
  • Conveyance: Assignment / Change of Name (implied)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: N/A
  • Context: Corporate name change from Conversant Intellectual Property Management Inc. back to MOSAID Technologies Incorporated.

Timeline diagram

timeline
    title Ownership of US 10140028
    2007 : Priority date
    2018 : Filed by Conversant IP Mgmt Inc
         : Assigned to CPPIB Credit
    2018 : Patent Issued
    2020 : Assigned to Conversant IP Mgmt
    2021 : Assigned to Mosaid Technologies (Name Change)

NPE / troll-pattern signals

1. Shell-entity transfer — Present.

   • Conversant Intellectual Property Management Inc. (original applicant and later assignee) and Mosaid Technologies Inc. (current assignee, former name of Conversant) are explicitly identified as intellectual property management and patent licensing companies, not product-shipping entities in the context of the patented technology. Their primary business involves acquiring and licensing patent portfolios.
   • CPPIB CREDIT INVESTMENTS, INC. (assignee at grant) is a financial entity that makes "intellectual property-backed investments," not a product-shipping company.
   • Supporting Dates/Events:
     • 2018-04-19: Application filed by Conversant Intellectual Property Management Inc.
     • 2018-08-22: Assigned to CPPIB CREDIT INVESTMENTS, INC.
     • 2020-11-06: Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
     • 2021-06-16: Assigned to MOSAID TECHNOLOGIES INCORPORATED (Change of Name).
       These events show a clear pattern of ownership by entities whose core business is IP management, licensing, or financial investment in IP, rather than manufacturing or selling products embodying the patent.

2. Known asserter in the chain — Present.

   • Mosaid Technologies Inc. (and its former name, Conversant Intellectual Property Management Inc.) is a well-known NPE/patent assertion entity. It is listed on NPE tracking sites and has a history of patent litigation.
   • Supporting Dates/Events:
     • 2018-04-19: Application filed by Conversant Intellectual Property Management Inc.
     • 2020-11-06: Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
     • 2021-06-16: Assigned to MOSAID TECHNOLOGIES INCORPORATED.

3. Repeat correspondent across the chain — Unclear.

   • The provided Google Patents data does not include correspondent information (attorney name, firm, address) for any of the recorded assignments.

4. Cascading transfers — Not present.

   • While there are multiple transfers, they are spaced over 1-2 years, not in rapid succession within <24 months (e.g., 2018, 2020, 2021). The 2021 transfer is also a name change, not a transfer to a distinct third-party.

5. Pre-litigation transfer — Unclear.

   • Information about specific litigation naming this patent (US10140028) is not provided in the full patent text or easily discoverable in the snippets, making it impossible to determine if any assignment preceded litigation by less than 6 months. While Mosaid/Conversant is a litigious entity, this specific signal cannot be confirmed without litigation data for this patent.

6. Bankruptcy fire-sale — Not present.

   • There is no indication that any of the assignors (Conversant, CPPIB) filed for bankruptcy. Mosaid went private in 2011, which is not a bankruptcy.

7. Privateering — Unclear.

   • While Mosaid/Conversant is an IP management company that acquires portfolios, the specific context of this patent's acquisition does not explicitly state it was transferred on behalf of an operating company against competitors. The initial application was filed by Conversant itself, suggesting it was part of their internally managed or acquired-for-assertion portfolio, not necessarily a privateering arrangement by another operating company.

8. Defensive aggregator (anti-NPE) — Not present.

   • The current assignee, Mosaid Technologies Inc., is a known patent asserter, not a defensive aggregator. RPX is mentioned in connection with Conversant in a licensing transaction related to a different portfolio in 2020, but RPX is not an assignee in the chain for US10140028.

Verdict

NPE — high confidence

This verdict is driven by several strong signals. The current and past assignees, Mosaid Technologies Inc. (operating as Conversant Intellectual Property Management Inc. during parts of the chain), are well-documented patent assertion entities whose primary business is IP management and licensing, not product sales related to the patented technology. The assignment to CPPIB Credit Investments Inc. (2018-08-22) before patent grant further supports a financial/IP-backed investment pattern, typical in NPE strategies. The chain of ownership is entirely composed of entities focused on IP monetization rather than technology development and sales, culminating in a known NPE.

For verification, see the USPTO Assignment Search for patent number 10140028: https://assignmentcenter.uspto.gov/

Prior Art Analysis for US Patent 10,140,028: Clock Mode Determination in a Memory System

U.S. Patent 10,140,028, titled "Clock mode determination in a memory system," describes a configurable memory device that can operate with either parallel or serial clock signals, where the operating mode is set by sensing a reference voltage. The patent emphasizes the ability for a single memory component to function in both high-performance source-synchronous clocking configurations and lower-performance parallel clocking configurations.

The most relevant prior art references cited within US10140028, as identified from its "CROSS REFERENCE TO RELATED APPLICATIONS" and "BACKGROUND" sections, are analyzed below for their potential anticipation of claims under 35 U.S.C. § 102.

Identified Prior Art References:

1. U.S. Provisional Patent Application Ser. No. 60/902,003

   • Full Citation: U.S. Provisional Patent Application Ser. No. 60/902,003, filed on February 16, 2007.
   • Publication/Filing Date: February 16, 2007 (Filing Date).
   • Brief Description: This provisional application is the priority document for the patent family, meaning it describes the foundational concepts of the invention. While not explicitly detailed as a separate prior art disclosure within the provided text beyond its priority claim, it is fundamental to the lineage of the '028 patent.
   • Potential Anticipation: As the direct provisional application from which US10140028 claims benefit, it is not typically considered anticipatory against US10140028 in the usual sense of 35 U.S.C. § 102, but rather establishes the effective filing date for the subject matter disclosed within it. Therefore, it would potentially anticipate claims 1-20 and 21-27 if they fully align with the disclosure of the provisional application.

2. U.S. Patent Application Ser. No. 12/032,249 (Issued as U.S. Pat. No. 7,885,140)

   • Full Citation: U.S. patent application Ser. No. 12/032,249, filed on February 15, 2008, now issued as U.S. Pat. No. 7,885,140 on February 8, 2011.
   • Publication/Filing Date: February 15, 2008 (Filing Date); February 8, 2011 (Publication/Issue Date).
   • Brief Description: This is the parent non-provisional application from which US10140028 directly claims continuation. It likely discloses the core concepts of "Clock mode determination in a memory system," including the configurable memory device with a mode setter, clock switch, and configurable data input/output buffer, where the mode is selected by sensing a reference voltage. It describes memory systems configurable to operate with parallel or serial clock signals.
   • Potential Anticipation: Given that US10140028 is a continuation of this application, the subject matter of US10140028 is largely derived from and likely present in US7885140. Therefore, US7885140 would potentially anticipate most, if not all, of claims 1-20 (semiconductor device and configurable memory device claims) and claims 21-27 (method claims for configuring a clock operating mode, and memory system claims).

3. U.S. Patent Application Ser. No. 11/843,440

   • Full Citation: U.S. patent application Ser. No. 11/843,440.
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but implied to be prior to February 16, 2007, as it's mentioned as "commonly owned U.S. patent application Ser. No. 11/843,440" in the context of serial memory systems being modular.
   • Brief Description: This application describes a serial memory system that can be modular, allowing additional memory devices to be added to expand total memory capacity. It focuses on the general concept of modularity in serial memory systems.
   • Potential Anticipation: This reference primarily addresses the modularity and expandability of serial memory systems. It might potentially anticipate aspects of claims 21-27 related to a "memory system" (Claim 21, 27) that is serially connected, but it does not appear to directly address the core inventive concept of clock mode determination based on a reference voltage or the configurable input circuits for different clocking schemes as broadly detailed in claims 1-20. Therefore, its anticipation is likely limited to the general architecture of a serial memory system rather than the specific clock mode configuration.

4. U.S. Patent Application Ser. No. 11/324,023

   • Full Citation: U.S. patent application Ser. No. 11/324,023.
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned as prior art describing functions of a serial interface and control logic block.
   • Brief Description: This application describes various functions of a serial interface and control logic block (e.g., setting device identifier numbers, passing data, decoding commands for native operations) within a memory device that receives commands serially.
   • Potential Anticipation: This reference focuses on the functionality of the serial interface and control logic block. It potentially anticipates aspects related to the "serial input/output interface" (Claim 21) of a memory device and the general command handling within a serial memory system. However, similar to the above, it does not appear to directly disclose the clock mode determination based on VREF or the configurable input circuits for different clock signal formats. Its anticipation would likely be limited to the broader context of serial memory device operation rather than the specific clocking mode configuration.

5. U.S. Provisional Patent Application No. 60/868,773

   • Full Citation: U.S. Provisional Patent Application No. 60/868,773, filed December 6, 2006.
   • Publication/Filing Date: December 6, 2006 (Filing Date).
   • Brief Description: This provisional application discloses a configuration having memory devices of mixed types within a memory system.
   • Potential Anticipation: This reference deals with memory systems having mixed types of memory devices. While it relates to memory system configurations, it does not appear to directly teach or suggest the clock mode determination based on a reference voltage or the configurable input circuits as claimed in US10140028. Its relevance would be to the overall memory system architecture, not the specific clocking mode features.

6. U.S. Patent Application Ser. No. 11/771,023 (titled "ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE")

   • Full Citation: U.S. patent application Ser. No. 11/771,023, titled "ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers and addressing for serially connected memory devices.
   • Brief Description: This application describes methods for address assignment and type recognition for serially interconnected memory devices, particularly in systems with mixed memory device types.
   • Potential Anticipation: This reference pertains to addressing and identification within serially connected memory devices. It informs the general operational environment of the memory system but does not directly disclose the specific clock mode determination mechanism of US10140028. Its anticipation, if any, would be to the system-level aspects of serial connectivity and device identification.

7. U.S. Patent Application Ser. No. 11/622,828 (titled "APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE")

   • Full Citation: U.S. patent application Ser. No. 11/622,828, titled "APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
   • Brief Description: This application describes apparatus and methods for producing identification (ID) numbers for interconnected devices of mixed types.
   • Potential Anticipation: Similar to U.S. Patent Application Ser. No. 11/771,023, this reference focuses on device identification. It provides context for the addressing scheme in a serial memory system but does not directly address the clock mode configuration of US10140028.

8. U.S. Patent Application Ser. No. 11/750,649 (titled "APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES")

   • Full Citation: U.S. patent application Ser. No. 11/750,649, titled "APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
   • Brief Description: This application describes methods for establishing device identifiers for serially interconnected devices.
   • Potential Anticipation: This reference is also focused on device identification in serially interconnected systems. Its relevance to US10140028 is in the general system architecture rather than the specific clock mode configuration.

9. U.S. Patent Application Ser. No. 11/692,452 (titled "APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE")

   • Full Citation: U.S. patent application Ser. No. 11/692,452, titled "APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
   • Brief Description: This application describes apparatus and methods for producing device identifiers for serially interconnected devices of mixed types.
   • Potential Anticipation: Another reference primarily concerned with device identification in mixed-type serially interconnected systems, it contributes to the general background but does not directly anticipate the clock mode determination.

10. U.S. Patent Application Ser. No. 11/692,446 (titled "APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION")

    • Full Citation: U.S. patent application Ser. No. 11/692,446, titled "APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION."
    • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
    • Brief Description: This application describes apparatus and methods for producing identifiers regardless of mixed device type in a serial interconnection.
    • Potential Anticipation: This reference, like the preceding ones, focuses on device identification in serially connected systems, contributing to the general system context but not the specific clock mode features of US10140028.

11. U.S. Patent Application Ser. No. 11/692,326 (titled "APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES")

    • Full Citation: U.S. patent application Ser. No. 11/692,326, titled "APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES."
    • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
    • Brief Description: This application describes apparatus and methods for identifying device types of serially interconnected devices.
    • Potential Anticipation: Similar to the previous few references, this one is concerned with device type identification in serially connected memory systems, offering background on system configuration rather than the core invention of clock mode determination.

Summary of Anticipation:

The primary and most direct prior art for US10140028 appears to be its own parent application, U.S. Pat. No. 7,885,140 (derived from Ser. No. 12/032,249), and its provisional application, Ser. No. 60/902,003. As a continuation, US10140028 is expected to claim subject matter disclosed in these earlier applications, and thus, they would largely anticipate the claims of US10140028 if the scope of the claims is not sufficiently distinguished by new features or combinations.

The other cited patent applications (Ser. Nos. 11/843,440, 11/324,023, 60/868,773, 11/771,023, 11/622,828, 11/750,649, 11/692,452, 11/692,446, and 11/692,326) appear to provide broader context regarding serial memory systems, device addressing, and mixed device types. While foundational to the environment in which US10140028 operates, they do not appear to directly anticipate the specific mechanism of "clock mode determination in a memory system" through sensing a reference voltage and configuring input circuits accordingly, as defined in claims 1-20 and 21-27. Their potential anticipation would be limited to generic elements of a serial memory system.

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The US10140028 patent explicitly describes the relevant prior art and the problem it aims to solve, providing a strong basis for an obviousness analysis.

Prior Art References for Combination:

1. Prior Art Flash Memory System 10 (FIG. 1 of US10140028): This reference describes a multi-drop memory system where memory devices 16 are connected in parallel to a channel 18, and a clock signal CLK is provided in parallel to each device. The patent notes its limitations, including signal integrity issues, increased power consumption at higher frequencies, and scalability limits.
2. Serial Memory System 20 (FIG. 2A of US10140028): This reference describes a serial memory system where memory devices (24, 26, 28, 30) are connected in series, but the clock signal CLK is still provided in parallel to all memory devices from a memory controller 22. This system uses "low voltage CMOS unterminated full swing signaling" (LVTTL) and operates at a "relatively relaxed clock frequency." This mode typically does not require a specific reference voltage (VREF) for data sensing, or VREF might be tied to a power supply rail (VDD or VSS).
3. Serial Memory System 40 (FIG. 2B of US10140028): This reference describes a serial memory system where memory devices (44, 46, 48, 50) are connected in series, and the clock signal CLK is provided serially from one memory device to another from an alternate memory controller 42. This "source synchronous" clock signal allows for "high frequencies" and "greater speed." This system uses "high speed transceiver logic (HSTL) signaling," which requires "a reference voltage that is used for determining a logic state of the incoming data signals." High-speed source-synchronous operation often necessitates clock synthesizers (e.g., Delay Locked Loops (DLLs) or Phase Locked Loops (PLLs)) to generate shifted clock edges for precise data sampling.

Motivation to Combine these References:

The US10140028 patent explicitly articulates the problem that provides the motivation for a person having ordinary skill in the art (PHOSITA) to combine the features of the aforementioned prior art systems. The patent states: "it may not be cost effective to replace existing slower speed serial memory systems with the high speed memory systems. Therefore, both types of memory devices would have to be available for upgrading or assembling of both types of serial memory systems." It further clarifies, "persons skilled in the art will understand that it is not cost effective to manufacture two different types of memory devices, where one type is configured for interfacing with memory controller 22 while another type is configured for interfacing with memory controller 42."

Thus, the clear motivation for a PHOSITA would be to design a single, configurable memory device that can operate interchangeably in both the slower, parallel-clocked serial memory systems (like FIG. 2A, using LVTTL) and the faster, source-synchronous serial-clocked memory systems (like FIG. 2B, using HSTL). Such a device would reduce manufacturing costs, simplify inventory, and offer greater flexibility for system designers.

Obviousness Analysis of the Independent Claims:

Claim 1: Semiconductor Device

Claim 1 describes a semiconductor device with a configurable input circuit operable in a first mode (for coincident clock/data edges, providing shifted clock edges for sampling) and a second mode (for non-coincident clock/data edges, sampling directly). The mode is set by an input pin (a reference voltage pin) which is set to a low/high power supply level for the second mode and a reference voltage level (between supply levels) for the first mode, the latter also being used to sense logic levels of input data.

• First Mode Operation: The requirements of the "first mode" (coincident edges, shifted clock edges for sampling) are directly addressed by the high-speed, source-synchronous serial memory system of FIG. 2B. Such systems, particularly those using HSTL signaling, have coincident clock and data edges and necessitate clock synthesizers (DLLs or PLLs) to generate precisely shifted internal clock phases to reliably sample data within narrow valid windows. The patent explicitly notes that "Each memory device will include a clock synthesizer, such as a DLL or a PLL for generating phases of the received clocks. Certain phases will be used to center the clock edges within the input data valid window internally to ensure reliable operation."
• Second Mode Operation: The requirements of the "second mode" (non-coincident edges, direct sampling) are met by the parallel-clocked serial memory system of FIG. 2A, which uses LVTTL signaling at "relaxed clock frequency." In such environments, clock and data edges are typically not source-synchronous, and simpler direct sampling with received clock edges is sufficient.
• Configurable Input Pin (VREF): The inventive aspect lies in using the VREF pin for dual functionality: mode selection and data reference. The HSTL signaling format described in FIG. 2B explicitly requires a "reference voltage that is used for determining a logic state of the incoming data signals." Conversely, for LVTTL signaling as used in FIG. 2A, a VREF voltage is typically "not required," and the VREF pin "can be set to either VDD or VSS."
  A PHOSITA, motivated by the stated need for a single, cost-effective device, would find it obvious to leverage an existing, required pin (VREF for HSTL) to also serve as the mode selection input. By tying VREF to a mid-supply level (e.g., VDD/2) for the high-speed HSTL/serial mode and to a power rail (VDD or VSS) for the lower-speed LVTTL/parallel mode, the device could automatically configure itself. This approach efficiently utilizes existing hardware and minimizes pin count, which is a common design goal in semiconductor packaging to reduce cost.

Claim 10: Configurable Memory Device

Claim 10 describes a configurable memory device including a mode setter, a clock switch, and a configurable data input/output buffer.

• Mode Setter: The mode setter senses the VREF voltage level and generates a mode selection signal. This is an obvious implementation of the mode selection mechanism described for Claim 1. Standard circuit elements such as voltage dividers and comparators (e.g., elements 506, 508, 512 in FIG. 6) are well-known building blocks for sensing voltage levels and generating logic signals. The addition of a delay circuit (e.g., counter 514 in FIG. 6) to allow voltages to stabilize and then disable the sensing circuit for power saving is also a conventional and obvious optimization in low-power design.
• Clock Switch: The clock switch receives either parallel or serial complementary clock signals and generates internal clock signals based on the mode selection signal. FIG. 8A explicitly shows a clock switch circuit 402 with a comparator 700 for serial clocks and buffers 702, 704 for parallel clocks, selectively enabled by the MODE signal. It also includes a PLL 706 for generating shifted clock phases in the serial mode, which can be disabled in the parallel mode to reduce power consumption. A PHOSITA would find it obvious to employ such known switching mechanisms and clock generation/management circuits to adapt to different clocking schemes based on the detected mode, especially given the explicit differences in clocking between FIG. 2A and FIG. 2B.
• Configurable Data Input/Output Buffer: This buffer is coupled to the data input port and VREF port and senses data relative to VREF in response to the serial mode (second logic state in Claim 10). FIG. 8A's data input buffer 412 shows a comparator 720 with VREF for HSTL data sensing and a buffer 722 for LVTTL data, with selection controlled by the MODE signal. This directly implements the known signaling requirements for HSTL (from FIG. 2B) and LVTTL (from FIG. 2A). The selective enabling of these known input buffer types based on the mode signal would be obvious for a PHOSITA aiming to support both signaling formats.

Claim 16: Method for Configuring a Clock Operating Mode

Claim 16 describes a method including setting a reference voltage level, comparing it to a preset reference voltage to generate a mode selection signal, and configuring a clock input buffer based on the mode selection signal. These method steps directly correspond to the functions of the hardware elements described in Claim 10. If the configurable hardware itself is obvious, then the method of operating that hardware in the described manner, using known techniques for voltage sensing, mode signal generation, and selective circuit activation, would also be obvious to a PHOSITA. The details of latching the mode signal, disabling unused circuits after a delay for power saving (determined by counting clock edges), and selectively enabling comparators or buffers, are all conventional design practices for configurable devices.

Claim 20: Configurable Memory System

Claim 20 describes a memory system comprising a memory controller and at least one serially connected memory device, where the device has clock input ports, a VREF input port, a mode setter, and a clock switch circuit. The mode setter compares VREF to a predetermined level and generates a mode selection signal, and the clock switch generates internal clocks based on this signal.

If the configurable memory device itself (as detailed in Claim 10) is deemed obvious, then incorporating such devices into a system where a memory controller provides either parallel (as in FIG. 2A) or serial (as in FIG. 2B) clock signals and sets the VREF level accordingly would be an obvious system-level integration. The patent explicitly states that the "memory controller can control" VREF or an "alternate circuit" can do so. A PHOSITA, equipped with the configurable memory device, would naturally design the memory system to utilize the device's configurable features, thereby realizing the stated goal of a versatile system.

In conclusion, the problem identified by US10140028 (the cost-ineffectiveness of manufacturing two different types of memory devices for different serial memory systems) provides a clear and explicit motivation for a PHOSITA to combine the known operational characteristics of the serial memory systems described in FIG. 2A (parallel-distributed clock, LVTTL) and FIG. 2B (source-synchronous serial clock, HSTL, VREF for sensing, DLL/PLL for timing). The implementation of this combination using a dual-purpose VREF pin for mode selection and data sensing, along with conventional circuit components for mode detection, clock switching, and data buffering, would have been obvious to a PHOSITA at the time of the invention.