US 10140028

Here's a concise summary of US patent 10140028:

US Patent 10140028

• Title: Clock mode determination in a memory system
• Current Assignee: Mosaid Technologies Inc
• Inventors: Peter B. Gillingham, Graham Allan
• Filing Date: April 19, 2018 (based on Application number US15/957,120)
• Issue Date: November 27, 2018
• Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

CAFC 2026 Dockets:
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Plain-Language Overview of Independent Claims:

• Claim 1: Semiconductor Device (Based on "First Aspect")
  A semiconductor device designed to receive both a clock signal and input data. It features a configurable input circuit that can operate in two modes:

  1. First Mode: For high-speed operation where the clock signal edges and input data edges arrive at the same time (coincident). In this mode, the circuit generates shifted clock edges to precisely sample the input data within its valid window.
  2. Second Mode: For lower-speed operation where the clock signal edges and input data edges are not coincident. The circuit directly uses these non-coincident edges to sample the input data.
     The device also includes an input pin (a reference voltage pin) that sets which of these two modes the configurable input circuit operates in. If this pin receives a low or high power supply voltage, it sets the second mode. If it receives a reference voltage level (typically between the low and high power supply levels), it sets the first mode and is used by the circuit to sense the logic levels of the incoming data.

• Claim 10: Configurable Memory Device (Based on "Second Aspect")
  A memory device that can be configured to operate in different clock modes, including:

  1. A mode setter that reads the voltage level of a dedicated reference voltage input port. Based on this voltage level, it produces a "mode selection signal."
  2. A clock switch connected to a clock input port. This switch can receive either parallel complementary clock signals (clocks arriving at all memory devices simultaneously) or serial complementary clock signals (clocks passed from one memory device to the next). In response to the mode selection signal, the clock switch generates internal clock signals that match the received parallel or serial clocks.
  3. A configurable data input/output buffer connected to a data input port and the reference voltage input port. If the mode selection signal indicates the serial clock mode, this buffer uses the reference voltage to determine the logic levels of the incoming data.

• Claim 16: Method for Configuring a Clock Operating Mode (Based on "Third Aspect")
  A method for setting up a memory device's clock operating mode, where the memory device receives a reference voltage for sensing data. The method involves:

  1. Setting the level of the reference voltage.
  2. Comparing this reference voltage to a predetermined internal reference voltage. This comparison generates a "mode selection signal" that reflects the outcome.
  3. Based on this mode selection signal, configuring the memory device's clock input buffer to receive either parallel complementary clock signals or serial complementary clock signals.

• Claim 20: Configurable Memory System (Based on "Fourth Aspect")
  A memory system that can be configured to operate with either parallel or serial clock signals. This system includes:

  1. A memory controller.
  2. At least one serially connected memory device. Each memory device has:
     • Clock input ports to receive either the parallel or serial clock signals.
     • A reference voltage input port that receives a reference voltage set to either a specific predetermined level or a power supply level.
     • A mode setter that compares this received reference voltage to a predetermined voltage level and generates a "mode selection signal" based on the comparison.
     • A clock switch circuit connected to the clock input ports. In response to the mode selection signal, this circuit generates internal complementary clock signals that correspond to either the parallel clock signals or the serial complementary clock signals it receives.