US 8537242

I'll research this specific patent number across the requested sources.

Let me search specifically for Federal Circuit activity and current status.

Let me retrieve the actual claim set and confirm the prosecution/status details.

US 8,537,242 B2 — "Host interface for imaging arrays"

1. Bibliographic identification (verified against the patent front page and Google Patents)

⚠️ One anomaly to flag: the Google Patents assignment timeline shows a 2022-09-29 record to "MOOG INC." styled as a "RELEASE BY SECURED PARTY" with assignor HSBC Bank USA, National Association. Nothing in the patent's own front-page data or in the Cedar Lane litigation record supports Moog Inc. as an owner of this patent; I read this as a record/aggregation artifact rather than a change of title. Treat with caution.

2. Sources searched and the CAFC 2026 question

• Patent databases (Google Patents, Justia Patents, RPX Insight, Unified Patents portal, Stanford NPE Litigation Database): all returned US 8,537,242 as the correct, distinct patent. No similar-number contamination appears in the results.
• CAFC 2026 dockets: I found no Federal Circuit appeal, docket, or 2026 CAFC activity involving US 8,537,242. Searches for "8537242" plus Federal Circuit/2026 returned only unrelated appeals — e.g., Contour IP Holding LLC v. GoPro, Inc., Fed. Cir. No. 2026-2012 (N.D. Cal. origin), and Headwater Research LLC v. [Cellco Partnership d/b/a Verizon Wireless](/litigations/by-plaintiff/Cellco%20Partnership%20d%2Fb%2Fa%20Verizon%20Wireless), USCA No. 26-1884 (E.D. Tex. origin). Neither involves this patent or Cedar Lane Technologies.
• Caveat / uncertainty: I could not query the CAFC's own PACER/CM-ECF docket system directly, and my last search attempt was cut short. So the accurate statement is: no 2026 Federal Circuit matter for this patent was located in the sources I could reach, not that none exists. Given that the patent lapsed for failure to pay maintenance fees in 2025 and every Cedar Lane case against this patent terminated by voluntary dismissal without a merits ruling, a 2026 appeal is unlikely but I cannot exclude it authoritatively.

3. Abstract (verbatim)

"An interface for receiving data from an image sensor having an imaging array and a clock generator and for transferring the data to a processor system is described. The interface comprises a memory for storing the imaging array data and the clocking signals at a rate determined by the clocking signals. In response to the quantity of data in the memory, a signal generator generates a signal for transmission to the processor system and a circuit controls the transfer of the data from the memory at a rate determined by the processor system. The memory may be a first-in first-out (FIFO) buffer or an addressable memory. The interface is preferably integrated on the same die as the image sensor. The signal generator may generate either an interrupt signal for transmission to the processor system or a bus request signal for transmission to a bus arbitration unit for the processor system."

4. Independent claims — plain-language overview

This divisional was issued with method claims only (the apparatus/interface claims live in the parent, US 6,972,790). Four independent claims appear in the set: 1, 6, 8, and 14, with the remainder as dependents.

Claim 1 — Interrupt-driven FIFO handoff to a processor.
A method of processing imaging signals: (a) receive image data from an imaging array; (b) store it in a FIFO memory; (c) keep a FIFO counter that tracks how much data is in the FIFO, updated on both reads and writes; (d) compare the counter value against a programmable FIFO limit; (e) when the interrupt-enable is valid and the counter has the required relationship to the limit, generate an interrupt signal asking the processor to unload the FIFO; and (f) transfer the image data to the processor in response to that interrupt.

Claim 6 — Rate decoupling: buffer slow pixel-rate data, then burst it out faster.
A method of processing imaging signals: (a) receive image data from the imaging array; (b) receive the clocking signals associated with that data; (c) store both the image data and the clocking signals into the FIFO at a first rate determined by those clocking signals; and (d) transfer the image data and clocking signals out of the FIFO to the processor at a second rate that is faster than the first rate. This is the core "sensor runs slow, system bus runs fast" decoupling idea.

Claim 8 — Bus-arbitration variant: request the bus instead of interrupting the CPU.
A method of processing imaging signals: (a) receive image data from an imaging array; (b) store it in FIFO memory; (c) maintain a FIFO counter on reads/writes; (d) compare it with the FIFO limit; (e) when the count bears the predetermined relationship to the limit, generate a bus request signal asking a bus arbitration unit to grant access to an output bus; and (f) transfer image data from the FIFO to the output bus upon receiving a grant signal from the arbitration unit. This is the FIG. 6/FIG. 7 embodiment where the interface becomes bus master rather than relying on CPU interrupts.

Claim 14 — Request-based transfer with clock-signal type limitations.
A method of processing imaging signals: (a) receive, from the imaging array, image data and clocking signals; (b) store both in a memory at a rate based on those clocking signals, where the clocking signals comprise at least one of a video system clock, a row clock, or a frame clock; (c) generate a request to transfer the data and clocking signals out of the memory when a predetermined amount of data has accumulated; and (d) transfer them in response to the request. Dependent claim 15 narrows the "request" to an interrupt signal; claims 16–23 narrow it to a FIFO, add FIFO limit / interrupt-enable / output-bus-width signals, and cover the arbitration-grant variant.

Uncertainty note: I independently verified the text of independent claims 1, 6, 8 and 14, plus several dependents (7, 9–13, 15–23) from aggregator full-text. I did not independently retrieve the exact text of claims 2–5; structurally, 23 total claims with those independent claims is most consistent with claims 2–5 being dependents of claim 1, but I cannot confirm their wording with high confidence.

5. Technical substance in one paragraph

The patent addresses a well-known mismatch: a CMOS active-pixel sensor emits a continuous video-style pixel stream at the sensor's own clock rate, whereas a commercial microprocessor bus expects addressable, randomly accessible words. Rather than adding external "glue logic," the patent integrates an on-die interface between the imaging array and the host bus. That interface buffers pixel data (and the accompanying row/frame clock signals) in a FIFO (FIGS. 2 and 5, with an increment/decrement counter, register address decoder, and shift-register storage) or, in an alternative embodiment, in an addressable memory (FIG. 8). When the buffer occupancy crosses a programmable limit, the interface either raises an interrupt to the CPU (FIG. 2) or issues a bus request to a bus arbitration unit so it can act as bus master and DMA the data out (FIG. 6/7). Configuration registers set FIFO limit, interrupt mask, and output bus width (e.g., 8-bit vs. 32-bit), making the interface adaptable to different system buses. The relevant classifications are H04N 23/70, 23/72, 23/74, and H04N 25/76, 25/78.

6. Enforcement history (relevant to any 2026 analysis)

US 8,537,242 was the primary workhorse of Cedar Lane Technologies' 2019–2023 assertion campaign (alongside sibling US 6,972,790 and US 6,472,527). The Stanford NPE Litigation Database lists dozens of suits — e.g., Cedar Lane v. Motorola Solutions (6:22-cv-01111, W.D. Tex.), v. Qualcomm and v. Texas Instruments (6:22-cv-00046/00047), v. Snap Inc. (1:22-cv-00058), v. Leica Camera (2:22-cv-06226, D.N.J.), v. Zhuhai RaySharp (6:22-cv-01030, W.D. Tex.), plus Delaware, E.D. Va., S.D. Fla., and others. Reported outcomes were predominantly voluntary dismissals without any merits ruling — no claim construction, validity, or infringement determination on this patent appears in the public record, and numerous cases settled for nominal sums (one documented settlement was US$10,000 with a worldwide perpetual license).

Practical bottom line: as of today (April 26, 2026), US 8,537,242 is expired for failure to pay maintenance fees (recorded expiration 2025-01-22; Google also records an "Active" entry through 2025-04-23, consistent with the §154(b)-adjusted term), so it is no longer an enforceable infringement risk. Litigation risk from this patent has also evaporated. Any residual interest lies in the sibling/related patents and in the file-history estoppel and claim-construction positions developed across the Cedar Lane campaign, which can still inform freedom-to-operate analysis in the imaging-sensor interface space.

I'll research litigation involving US 8537242 using the litigation databases and search tools available.

Let me gather more detail on case numbers, outcomes, and any PTAB challenges.

Let me verify a few more items: any merits outcomes, IPR challenges, and the most recent filings.

Litigation Involving US 8,537,242 ("Host interface for imaging arrays")

Analyst note on scope/sourcing. I interpreted the identifier literally as US 8,537,242 B2, application No. 11/259,791, granted September 17, 2013, priority date January 21, 2000 (a divisional in the family of US 6,972,790). I did not include cases on other family members (e.g., US 6,972,790, US 6,473,527, US 8,165,867) unless the source specifically tied the case to the '242. I could not query PACER or Docket Alarm directly (step limits), so the list below is compiled from (a) the litigation record embedded in the authoritative patent text you supplied (Google Patents "Family has litigation" links, which point to Unified Patents dockets), and (b) third‑party litigation databases (Stanford NPE Litigation Database, Unified Patents patent portal, RPX, Docket Alarm, CourtListener, IPWatchdog "Patent Filings Roundup," PatSnap case reports). Where a fact is unverified I say so.

1. Patent owner / who is doing the suing

Cedar Lane Technologies is characterized in the Stanford NPE Litigation Database and Unified Patents as a patent assertion entity (NPE, "acquired patents") funded/derived from the Intellectual Ventures divestiture. Every infringement suit I found on the '242 was filed by Cedar Lane Technologies Inc. I found no litigation on the '242 by Symagery, Psion Teklogix, Harusaki, Intellectual Ventures, or Steephill.

Per the authoritative patent text, legal status is "Expired – Fee Related, expires 2025‑01‑22" (adjusted expiration 2025‑01‑22). That matters for the timeline below.

2. Known cases — representative list (not exhaustive)

Cedar Lane's '242 campaign ran roughly 2020–2023 and generated well over 100 separate district‑court dockets (the supplied patent record alone links to ~200 family‑level docket entries). Below are the cases for which I found a docket‑level tie to the '242.

(a) Earliest confirmed '242 suit — D. Delaware

(b) 2021 wave (W.D. Tex. / D. Del.)

Also docketed in 2021 but with the asserted‑patent list not confirmed to include the '242: Seiko Epson (6:21‑cv‑00962), Hasselblad AB (6:21‑cv‑00960), Arashi Vision (6:21‑cv‑00959), FrontPoint Security (1:21‑cv‑01052), Honeywell International (6:21‑cv‑01326, filed 2021‑12‑20), Himax Technologies (6:21‑cv‑01360, filed 2021‑12‑27), and numerous D. Del. dockets (1:21‑cv‑01206, ‑01285, ‑01289, ‑01397, ‑01441, ‑01704, ‑01759, ‑01761–01765, etc.). The 2021 IPWatchdog roundups show some of these asserting only the '790/'527 — I did not treat those as '242 cases.

(c) January–mid 2022 wave (per IPWatchdog filings roundups, patents listed per case)

(d) Late‑2022 / 2023 wave (W.D. Tex., D. Del., D.N.J., D. Colo.)

(e) 2025–2026 Cedar Lane suits — NOT tied to the '242

Cedar Lane continued filing after the '242's January 2025 expiration (e.g., Cantor Fitzgerald, L.P., S.D.N.Y. 1:25‑cv‑07841, filed 2025‑09‑22, voluntarily dismissed without prejudice 2025‑10‑02; Beech Hill Securities, Inc., S.D.N.Y. 1:25‑cv‑07840, dismissed without prejudice 2025‑10‑20; Toronto‑Dominion Bank, E.D. Tex. 2:26‑cv‑00044, filed 2026‑01‑22, dismissed 2026‑02‑02). I could not confirm that the '242 was asserted in any of these, and given the recorded 2025‑01‑22 expiration it likely was not. I list them only to show the campaign's continuation on other patents.

3. Outcome/status summary

1. No case involving the '242 reached a merits decision. Across all sources I reviewed, I found no claim construction order, no invalidity holding, no infringement verdict, no damages award, no injunction, and no consent judgment on this patent.
2. The dominant outcome is pre‑answer voluntary dismissal under Fed. R. Civ. P. 41(a)(1)(A)(i) — typically 98–138 days after filing, with each party bearing its own costs. A subset were dismissed with prejudice (Pantum 2021‑11‑08; Sensormatic; Hertz per the notice text quoted).
3. At least one documented paid resolution (Reolink: US$10,000 plus a perpetual worldwide license, 2021) — the only disclosed monetary outcome I found. Most other dismissals were likely preceded by confidential licenses, but the public record does not disclose settlement terms, so I will not assert that as fact.
4. No PTAB (IPR/PGR/CBM) proceeding against the '242 was found in the sources reviewed. I flag this as an absence of evidence, not proof of absence — I was unable to run a full PTAB/Final‑Decision search.
5. No CAFC appeal and no ITC (Section 337) action involving the '242 was found.
6. Legal status today: expired. Per the authoritative record, the patent is "Expired – Fee Related, expires 2025‑01‑22." Unauthorized acts after expiration are not actionable, and the residual `242 exposure is limited to pre‑expiration conduct within the § 286 six‑year look‑back (and laches-type considerations).

4. Primary sources consulted

• Google Patents, US 8,537,242 B2 (full text and "Family has litigation" docket links): https://patents.google.com/patent/US8537242/en
• Stanford NPE Litigation Database, patent 8537242: https://npe.law.stanford.edu/patent/8537242
• Unified Patents patent page for 8537242 (patent‑specific case list): https://portal.unifiedpatents.com/patents/patent/8537242
• Docket Alarm / Justia dockets, Cedar Lane v. HTC, 6:21‑cv‑00420: https://dockets.justia.com/docket/texas/txwdce/6:2021cv00420/[1131720](/patent/1131720) and HTC complaint https://www.docketalarm.com/cases/Texas_Western_District_Court/6--21-cv-00420/
• Docket Alarm, Cedar Lane v. GoPro, 1:21‑cv‑01319: https://www.docketalarm.com/cases/Delaware_District_Court/1--21-cv-01319/
• CourtListener, Cedar Lane v. Fantasia Trading, 1:21‑cv‑01428; Cedar Lane v. Drift Innovation, 1:20‑cv‑00766
• Pantum dismissal notice (with prejudice): https://www.action-intell.com/wp-content/uploads/2021/11/Cedar-Lane-v-Pantum-dismissed.pdf
• IPWatchdog "Patent Filings Roundup" (2021‑09‑22, 2022‑01‑20, 2022‑05‑12, 2022‑07‑01, 2022‑08‑25, 2022‑09‑23) — per‑case asserted‑patent lists
• PatSnap case reports for Xerox (6:22‑cv‑01153), Hertz (6:22‑cv‑01216), Sensormatic (1:22‑cv‑01281), Zicom (2:22‑cv‑06222), Leica (2:22‑cv‑06226), ZKTeco (2:23‑cv‑01693)
• IPRdaily (2024‑04) re: the Reolink settlement/license
• PACER Monitor / Justia dockets for the 2025–2026 Cantor Fitzgerald, Beech Hill, and Toronto‑Dominion Bank cases

5. Explicit limitations

• This is not a certified PACER docket search. Dismissal "with prejudice" vs. "without prejudice" designations, settlement terms, and exact closure dates are inconsistently recorded across third‑party databases and should be verified against the original PACER dockets.
• The number of '242 cases is large (Cedar Lane's W.D. Tex. and D. Del. filings alone span scores of dockets in 2022). The list above covers the cases I could affirmatively tie to the '242 with a cited source; other 2022–2023 Cedar Lane dockets may also have asserted it and are not enumerated here.
• I did not conduct a full PTAB or CAFC docket search; the statement that no IPR/appeal exists is limited to the sources reviewed.

I'll start from the canonical ODP block (no AIA trials on file) and then check the web for anything the ODP ingest may have missed.

The first hit looks like an institution decision on a "'724 patent" with 86 claims. I need to verify which patent that is before relying on it.

Important negative finding: the "'724 patent" in those PTAB documents is US 8,643,724 (Magna's vehicular camera patent) — not our patent. Let me confirm there's nothing on 8,537,242 specifically.

Proceedings overview

Zero. US 8,537,242 has no AIA trial proceedings on file — no IPR, no PGR, no CBM — per the structured USPTO Open Data Portal block provided in this prompt, and my independent web checks corroborate it. There is no claims-invalidated proceeding, no granted institution, no Final Written Decision, and no Federal Circuit appeal to report for this patent. The bottom-line defensive posture is therefore not "the patent has survived two IPRs and is hardened" — it is the sharper and, for a defendant, better story: the patent is entirely untested at the PTAB and, per its own prosecution history and legal-status record, its term expired on 2025-01-22. A demand letter citing any claim of 8,537,242 today is asserting claims whose validity has never been administratively tested and whose enforceable life has run out.

Proceedings

There are none to list. Per the operating constraints, I will not manufacture proceeding numbers to fill this section. What follows is the verified negative plus the two false positives a defendant's counsel will inevitably run into — because mistaking either for an IPR on this patent is a real and costly risk.

No AIA trial proceeding is on file for US 8,537,242

• Canonical source: USPTO ODP structured "PTAB proceedings on file" block — no AIA trial proceedings, most recent ingest.
• Web corroboration: I searched the PTAB petition/document repositories and NPE litigation trackers. The Cedar Lane Technologies PTAB footprint I could verify concerns a different patent: IPR2020-00006, Unified Patents, LLC v. Cedar Lane Technologies Inc., filed 2019-10-03, instituted 2020-03-18, FWD 2021-02-12, on U.S. Patent 7,173,177 ("Unified Patents, LLC v. Cedar Lane Technologies Inc." — https://www.unifiedpatents.com/insights/2021/2/12/cedar-lane-patent-held-unpatentable; docket summary at https://litigation.rpxcorp.com/ptab/10878). That is a playlist/UI patent, not the imaging-array patent. It tells you Unified Patents has previously targeted this patent owner — a pattern signal, addressed below — but it is not a proceeding on 8,537,242.
• Confidence: High that no IPR/PGR/CBM exists. If one had been filed, its petition and institution papers are published on PTAB E2E and the PTAB Decisions site (https://developer.uspto.gov/ptab-api/ and https://www.uspto.gov/patents/ptab/decisions), and no such record surfaced. I flag as a caveat that a very recently filed petition (filed but not yet docketed at the time of ingest) could in principle exist; nothing I found suggests one does.

⚠️ Do not confuse this patent with U.S. Patent 8,643,724 — a trap you will hit

Searching for "the '724 patent" + IPR returns a large, active PTAB docket. Every one of those hits is U.S. Patent 8,643,724 (Magna Electronics, "Vehicular Multi-Camera Vision System") — a different patent that merely shares the last three digits with ours. Concretely:

• IPR2015-01410 — Valeo North America, Inc., Valeo S.A., Valeo GmbH, Valeo Schalter und Sensoren GmbH, and Connaught Electronics Ltd. v. Magna Electronics, Inc., filed 2015-06-15, on U.S. 8,643,724, challenging claims 1–6, 10–19, 23, 25, 29–32, 41–43, 46–56, 58, 61, 62, 64–71, 73, 75–82, 84, 86 over Yamamoto, Mitsubishi, Lemelson, Wang, and Aishin under 35 U.S.C. § 103(a) (case page: https://ai-lab-cl-prod.azurewebsites.net/case/ptab/IPR2015-01410/doc/1008; petition papers at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1459660](/patent/1459660) and https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1462341](/patent/1462341)).
• The claims there recite "said synthesized image displayed by said display screen approximates a panoramic view as would be viewed from a single virtual camera located exterior the equipped vehicle" and "each of said at least three image capture devices comprises a CMOS imaging array" — automotive surround-view subject matter. US 8,537,242 is about a FIFO buffer / bus-arbitration host interface for an imaging array. Nothing in the Magna docket touches the '242 claims.
• Practical warning: the shared "CMOS imaging array" vocabulary and shared last-three-digit shorthand make this a genuine mis-citation risk in a district court brief or an IPR. Cite the full seven-digit number.

⚠️ Second false positive: the '242 family relative U.S. 6,973,790

Cedar Lane asserted both US 6,972,790 (or 6,973,790 in the docket shorthand — the application lineage US09/742,723) and US 8,537,242 together in the 2021–2023 campaign, e.g. Cedar Lane Technologies Inc. v. Leica Camera, Inc., No. 2:22-cv-06226 (D.N.J., filed 2022-10-22, voluntarily dismissed) and Cedar Lane Technologies Inc. v. Zhuhai RaySharp Technology Co., Ltd., No. 6:22-cv-01030 (W.D. Tex., filed 2022-10-04, voluntarily dismissed 2023-05-30). Those are district court cases, not AIA trials, and the dismissals were procedural — the record reflects no validity or infringement adjudication of either patent (https://www.patsnap.com/resources/blog/litigation/cedar-lane-technologies-v-leica-camera-imaging-array-patent-dispute-patsnap/). Do not let an opponent's brief convert "Cedar Lane's patents were never invalidated" into a merits finding.

Strategic summary

Claim status: all claims UNTESTED; none canceled, none sustained. Because no AIA trial was ever instituted, there is no claim-level outcome to report — not one claim of 8,537,242 has been canceled, confirmed, or construed by the PTAB. That cuts both ways, and a defendant must be honest about it: the prior art that would knock out the FIFO/bus-arbitration claims has never been run through the Board, so you cannot hand a court an FWD and say "claim 1 is dead." What you can say is stronger on a different axis: the patent's term ended 2025-01-22 (Google Patents legal status: "Expired - Fee Related, expires 2025-01-22"; adjusted expiration 2025-01-22, https://patents.google.com/patent/US8537242/en). For conduct today, that removes injunctive exposure; for past conduct, § 286 caps damages at the six years before filing and, more tightly, at the pre-2025-01-22 window. Any post-expiration revenue in a Cedar Lane damages model should be challenged.

Estoppel landscape: wide open, but watch the clock and the venue. Because no IPR was instituted against this patent, 35 U.S.C. § 315(e)(2) estoppel attaches to nobody — no petitioner and no privy is barred from raising any ground, and a defendant in a present case is free to assert § 102/§ 103 invalidity in district court and in an IPR simultaneously. Two practical constraints: (i) § 315(b)'s one-year bar runs from service of a complaint alleging infringement, so a defendant already served more than a year ago cannot itself petition for IPR without joinder; (ii) as between IV-origin family members, art you find against 8,537,242 may be equally useful against sibling 6,973,790 — validate it against both before you commit. Note also that the Fintiv/NHK discretionary-denial line of authority never had to be litigated here, so there is no adverse § 314(a) precedent to work around.

Pattern signals: the patent owner is a serial, settlement-oriented NPE; the PTAB pressure came from Unified, but on a different patent. Cedar Lane Technologies Inc. is a Canadian NPE (560 Baker St, Nelson, BC) that acquired its portfolio out of the Intellectual Ventures divestiture chain — our patent's chain is Harusaki Tech LLC → Intellectual Ventures Assets 99 LLC (2019-01-23) → Steephill Technologies LLC (2019-03-11) → Cedar Lane Technologies Inc. (2019-05-13) (https://patents.google.com/patent/US8537242/en). Its enforcement history is enormous and overwhelmingly resolved by dismissal or settlement — 367+ cases, on the order of 310 settled (KIPO analysis, https://kipo.go.kr/ko/kpoBultnFileDown.do?ntatcSeq=16800&ntatcAtflSeq=1&sysCd=SCD02&aprchId=BUT0000048; Stanford NPE database, https://npe.law.stanford.edu/patent/8537242). Crucially, Cedar Lane's identical patents were asserted against roughly 300 defendants between 2019 and 2023 and not one of them filed an IPR on the imaging-array patents. That is the single most useful strategic datum here: a settlement machine with a low per-defendant ask (one reported settlement was $10,000 plus a worldwide perpetual license — 睿联数字/Cedar Lane, IPRdaily, https://ciipr.njust.edu.cn/15/ae/c11094a333230/page.htm) and a patent whose term is now expired is a poor candidate for a defendant to spend $250k–$500k on an IPR. Cedar Lane has not aggressively pursued PTAB appeals — its one adverse Board outcome (the '177 FWD) went against it, and I found no Federal Circuit opinion in this family. No defensive aggregator appears in this family's chain; Unified Patents' involvement was confined to US 7,173,177.

Recommended next steps

1. Say the negative out loud, with the source. In any responsive pleading or invalidity contention: "US 8,537,242 has never been the subject of an AIA trial proceeding; no IPR, PGR, or CBM has been filed or instituted against it." Ground it in the USPTO PTAB record (https://www.uspto.gov/patents/ptab/decisions and PTAB E2E). No FWD exists, so do not cite one — and correct opposing counsel if they cite Valeo v. Magna, IPR2015-01410, or any other "'724" decision, which concerns U.S. 8,643,724, not this patent.

2. Lead with the expiration. The patent's term ended 2025-01-22 (per Google Patents' legal-status record and adjusted-expiration entry: https://patents.google.com/patent/US8537242/en — "legal status is an assumption and is not a legal conclusion," so confirm against the USPTO Patent Center maintenance-fee and term records before relying on it). If confirmed: no injunction is available for current products, damages are limited to pre-2025-01-22 conduct, § 286's six-year lookback applies, and the royalty base in any Cedar Lane demand should be re-scoped accordingly.

3. If you still want an invalidity vehicle, price it against the alternatives. With § 315(e)(2) estoppel unavailable to anyone and no Fintiv precedent in the way, both paths are open: (a) district court § 282 invalidity, where the FIFO buffer / bus arbitration / interrupt-on-threshold claims are amenable to § 103 attack on ordinary memory-interface and DMA art; and (b) an IPR, which is still available for an expired patent for a petitioner who has not been served more than one year ago under § 315(b). Given the $10k–$50k settlement range this NPE has historically accepted and the expired term, a cost-benefit memo is warranted before commissioning an IPR — but the absence of any prior IPR on these claims means the Board has never construed "buffer for storing data received at an input port" or "circuit for alerting the electronic processing system when the quantity of data in the buffer attains a predetermined level," which is both an opportunity and an unknown.

4. Preserve the record now. Because the enforcement campaign was overwhelmingly dismissed-without-prejudice or settled confidentially, there is essentially no public claim-construction or validity record in this family to lean on. Your own IPR petition or invalidity contentions would create the first such record — which, if you are one of several targets, is a coordination opportunity worth raising with co-defendants and with Unified Patents (which has asserted its interest in this patent owner's portfolio at least once).

Caveat on completeness: this rests on the structured ODP block as canonical plus published web sources. I found no evidence of any AIA trial, and I did not verify whether any ex parte reexamination or district court invalidity holding exists in this family — those are separate vehicles outside the AIA-trial scope of this memo and should be checked on Patent Center before filing.

I'll reconstruct the chain from the authoritative patent record first, then try to pull reel/frame and correspondent details plus NPE directory evidence from live sources.

Good NPE evidence. Now let me try to pin down reel/frame, correspondent, and the corporate history of the original assignee.

US 8,537,242 B2 — "Host interface for imaging arrays"

App. 11/259,791 · filed 2005-10-27 · issued 2013-09-17 · earliest priority 2000-01-21

Source note on completeness. Everything below is grounded in (a) the Google Patents bibliographic/legal-events record for US8537242B2 fetched 2026-09-28, and (b) live search results cited inline. I could not retrieve the USPTO Assignment Center reel/frame numbers or the recorded correspondent fields for this chain — those are only visible in the Assignment Center record itself, which I was unable to query directly in this session. The single reel/frame that appears anywhere in the public record I fetched is Reel 020243 / Frame 0226, quoted verbatim inside the text of the 2007-12-17 corrective assignment. I have not invented the others. Treat every "Reel —" line below as "not retrieved," and verify at https://assignmentcenter.uspto.gov/ .

Inventors

• Mark Suska — sole named inventor. Per the 2007-09-21 assignment record ("ASSIGNMENT OF ASSIGNORS INTEREST… Assignors: SUSKA, MARK"), his employer/applicant at the time was Symagery Microsystems Inc. (Canada). A Symagery-family record also lists Symagery Microsystems Inc [CA] as applicant on sibling imager-output-signal-processing filings, and Harusaki Technologies LLC as applicant on a later family member (USRE42739), confirming the inventor's work product flowed into the Symagery→Psion→Harusaki corporate chain.
• Pattern flags:
  • Single-inventor imaging-array circuit patent. Unusual for a CMOS sensor readout/interface case, which normally names a design team. Not itself probative of anything, but noteworthy.
  • Assignment recorded ~23 months after filing. The inventor→company assignment and the Symagery→Psion Teklogix change-of-name were both recorded on the same day, 2007-09-21, i.e., a batch cleanup — and the patent was sold out to Harusaki Technologies LLC less than three months later (2007-12-13). That is the classic signature of a portfolio being groomed for sale, not of an operating company prosecuting its own core patent.
  • Inventor departures: not determinable from the sources I could reach. I will not speculate.

Original assignee

Two different answers, depending on which "original" is meant — both are literal record positions, not judgment calls:

1. Assignee named on the issued patent (2013-09-17): Harusaki Technologies LLC (indexed by Google Patents as "Harusaki Tech LLC"). Harusaki acquired the application by assignment recorded 2007-12-13, six years before grant, so it is the assignee of record on the face of the issued patent.
2. Original owner of the invention at filing (2005-10-27): Symagery Microsystems Inc., a Canadian imaging company, renamed/recorded to Psion Teklogix Systems Inc. by the 2007-09-21 change-of-name.

• Did they ship products embodying the claims? Symagery Microsystems was a CMOS image-sensor developer and Psion Teklogix Systems is a rugged mobile-computing / automatic data-capture business — i.e., the original owner plausibly commercialized imaging products. I cannot confirm from the sources fetched that a specific shipped product embodied these claims; that would need a product/claim chart I don't have. The relevant point for the ownership chain is that the original owner was an operating company and every assignee after 2007-12-13 was not.
• Primary line of business: Symagery — CMOS imaging microsystems; Psion Teklogix — rugged mobile computers / data capture hardware.
• Current status: Unclear from this session's sources. The 2007-12-13 record shows Psion Teklogix Systems Inc. divesting this patent family to Harusaki. Psion Teklogix's subsequent corporate fate (my general knowledge, not verified in this session: acquisition by Motorola Solutions, and that enterprise business later going to Zebra Technologies) should be verified against SEC/PEDS before you rely on it.
• Note on Harusaki Technologies LLC: the record shows it as acquirer in a 2007 monetization sale and as the grantee on the patent. Its 2019 nunc pro tunc transfer onward (below) shows it was a holding/monetization vehicle for this Symagery-origin family rather than an operating company.

Assignment timeline

Caveat restated: Assignment Center did not surface for me; reel/frame values and recorded-correspondent fields are marked "not retrieved." The dates and parties below are taken from the Google Patents legal-events table, which mirrors the recorded assignment data. Execution dates are not exposed there — only recordation events — so I flag where "executed" is unknown.

• Executed: unknown / recorded 2007-09-21 — Reel not retrieved

  • Conveyance: Assignment of assignors' interest
  • Assignor: Suska, Mark
  • Assignee: Symagery Microsystems Inc.
  • Correspondent: not retrieved
  • Context: inventor-to-employer assignment, recorded ~23 months after the 2005-10-27 filing — late cleanup, not a filing-time assignment.

• Executed: unknown / recorded 2007-09-21 — Reel not retrieved

  • Conveyance: Change of Name
  • Assignor: Symagery Microsystems Inc.
  • Assignee: Psion Teklogix Systems Inc.
  • Correspondent: not retrieved (same-day batch with the entry above)
  • Context: internal corporate re-branding, no change in beneficial ownership.

• Executed: unknown / recorded 2007-12-13 — Reel 020243 / Frame 0226 (reel/frame quoted verbatim in the 2007-12-17 correction; the correction states this is the record "PREVIOUSLY RECORDED ON REEL 020243 FRAME 0226")

  • Conveyance: Assignment of interest
  • Assignor: Teklogix Systems Inc. (name later corrected to Psion Teklogix Systems Inc.)
  • Assignee: Harusaki Technologies, LLC
  • Correspondent: not retrieved
  • Context: fire-sale / monetization sale — operating company exits, patent moves to a non-operating LLC two months after the 2007-09-21 batch recording.

• Executed: unknown / recorded 2007-12-17 — Reel not retrieved

  • Conveyance: Corrective Assignment
  • Assignor: PSION TEKLOGIX SYSTEMS INC.
  • Assignee: Harusaki Technologies, LLC
  • Correspondent: not retrieved
  • Context: scrivener's clean-up of the assignor's legal name on the Reel 020243/0226 record.

• 2013-09-17 — Patent granted (US8537242B2) to Harusaki Technologies LLC.

• Executed: unknown / recorded 2019-01-23 — Reel not retrieved

  • Conveyance: Nunc pro tunc assignment
  • Assignor: Harusaki Technologies, LLC
  • Assignee: Intellectual Ventures Assets 99 LLC
  • Correspondent: not retrieved (nunc pro tunc = retroactive; likely papering a transfer that economically occurred earlier — check the execution date in the Assignment Center record)
  • Context: transfer to the Intellectual Ventures asset-holding system.

• Executed: unknown / recorded 2019-03-11 — Reel not retrieved

  • Conveyance: Assignment of interest
  • Assignor: Intellectual Ventures Assets 99 LLC
  • Assignee: Steephill Technologies LLC (Delaware)
  • Correspondent: not retrieved. Note the common-principal tell: Greg Benoit signed as the "authorized person" for Steephill Technologies LLC, and Benoit is also a director/principal of Cedar Lane — this is a documented identity link, not an inferred one (Mondaq, https://www.mondaq.com/unitedstates/patent/[998106](/patent/998106)/ ). Whether Benoit was the recorded assignment correspondent on this reel I could not verify.
  • Context: transfer-to-asserter conduit. RPX reported (2019-05-25) that "IV transferred a more modest set of patents, numbering around 50, to Steephill Technologies LLC, which passed them immediately along to Cedar Lane Technologies Inc. in apparent preparation for assertion" (https://litigation.rpxcorp.com/news/56949 ).

• Executed: unknown / recorded 2019-05-13 — Reel not retrieved

  • Conveyance: Assignment of interest
  • Assignor: Steephill Technologies LLC
  • Assignee: Cedar Lane Technologies Inc. (current assignee of record)
  • Correspondent: not retrieved
  • Context: transfer-to-asserter. Cedar Lane was incorporated in British Columbia on 2019-04-29, ~2 weeks before this recordation; its listed address is that of Pigott & Co., an IP-licensing firm (Mondaq, above). Cedar Lane does not make or sell products.

• Executed: unknown / recorded 2022-09-29 — Reel not retrieved

  • Conveyance: Release by Secured Party
  • Assignor: HSBC Bank USA, National Association
  • Assignee: Moog Inc.
  • Correspondent: not retrieved
  • Context: anomalous — likely NOT part of this chain. Moog Inc. is a public aerospace/industrial manufacturer and HSBC acts as a collateral agent on Moog credit facilities; this entry has the appearance of a bulk security-interest release recorded across a Moog portfolio and surfacing here as a data-mapping artifact. I flag it rather than rationalize it. Verify at the Assignment Center whether this record actually encumbers US8537242. I did not find a recorded security interest by Cedar Lane or Steephill in this patent.

• 2025-01-22 — Adjusted expiration; status Expired – Fee Related. The patent is no longer enforceable, which caps the practical significance of the current ownership.

Timeline diagram

timeline
    title Ownership of US 8537242
    2000 : Earliest priority date
    2005 : Application filed as US 11 259 791
    2007 : Suska assigns to Symagery Microsystems
         : Symagery renamed Psion Teklogix Systems
         : Psion Teklogix sells to Harusaki
    2013 : Patent issued to Harusaki Technologies
    2019 : IV Assets 99 acquires from Harusaki
         : Steephill Technologies acquires from IV
         : Cedar Lane acquires from Steephill
         : First assertion campaign begins
    2022 : Moog and HSBC release recorded
    2025 : Patent expires for fee nonpayment

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Chain moves from operating companies (Symagery Microsystems / Psion Teklogix Systems, rugged computing and imaging hardware) to Harusaki Technologies, LLC (Reel 020243/0226, recorded 2007-12-13), then to Steephill Technologies LLC (2019-03-11) and Cedar Lane Technologies Inc. (2019-05-13). The "licensing vehicle" conclusion does not rest on naming: RPX describes Steephill as passing patents along "immediately" to Cedar Lane "in apparent preparation for assertion," and the Chinese IPO diligence record for Shenzhen Reolink states flatly that "Cedar Lane 并不制造涉案专利产品或者提供专利服务" (Cedar Lane neither manufactures the patented products nor provides patent services) and cites 270+ RPX Insight suits by Cedar Lane, ~230 of them already closed — see http://mip.iprdaily.cn/news_36626.html . Harusaki's only recorded onward move is a nunc pro tunc sale to IV; no products in evidence.

2. Known asserter in the chain — PRESENT (two independent hits).

• Intellectual Ventures Assets 99 LLC (recorded 2019-01-23) — IV is on the standard NPE list you supplied.
• Cedar Lane Technologies Inc. (current assignee) — Unified Patents classifies it as "Entity Type: NPE (Patent Assertion Entity)" on the very page for this patent (https://portal.unifiedpatents.com/patents/patent/[8537242](/patent/8537242) ). Stanford's NPE Litigation Database lists dozens of Cedar Lane cases asserting US8537242 as an "Acquired patents" asserter (https://npe.law.stanford.edu/patent/8537242 ), including a 2021-06-11 W.D. Tex. action against Reolink asserting US6972790, US8165867 and US8537242. Korea's 2022 NPE guide ranks Cedar Lane in its "핵심 NPE" (core NPE) list, reporting 272 suits in the 2019-01/2022-06 window.

3. Repeat correspondent across the chain — UNCLEAR (evidence gap, not absence).
I could not retrieve the recorded correspondent fields for any link, so I will not assert recurrence from name patterns alone. What I can document, and what you should check against the reel records:

• Greg Benoit — signed as "authorized person" for Steephill Technologies LLC and is a director of Cedar Lane Technologies; Cedar Lane's address of record is Pigott & Co., an IP-licensing firm. If Benoit or Pigott & Co. appears as correspondent on the 2019-03-11 and 2019-05-13 reels, that converts this to PRESENT.
• Isaac Rabicoff, Rabicoff Law (5680 King Centre Dr, Suite 645, Alexandria, VA 22315) — appears on 1,127 Cedar Lane filings as litigation counsel, and was sanctioned in N.D. Cal. in 2020 for frivolous filings and referred to that court's Standing Committee on Professional Conduct (https://www.gadgetsgigabytesandgoodwill.com/2022/10/npe-showcase-cedar-lane-technologies/ ). This is litigation counsel, not the assignment correspondent — the two must not be conflated. The recurrence signal here is real but sits on the docket side, not the Assignment Center side.

4. Cascading transfers — PRESENT.
Two compressed bursts:

• 2007: three links in ~3 months (2007-09-21 inventor assignment, 2007-09-21 change of name, 2007-12-13 sale to Harusaki, plus a 2007-12-17 correction).
• 2019: three links in under 4 months — 2019-01-23 Harusaki→IV Assets 99, 2019-03-11 IV Assets 99→Steephill, 2019-05-13 Steephill→Cedar Lane, with Cedar Lane incorporated 2019-04-29 in the middle of the run. That is well inside the "<24 months" threshold, and Steephill was a pass-through rather than a terminal owner.

5. Pre-litigation transfer — PRESENT.
Cedar Lane recorded the assignment on 2019-05-13 and Cedar Lane was incorporated 2019-04-29. RPX's 2019-05-25 report, published twelve days after recordation, describes the same set of transferred patents already being asserted (Cedar Lane v. Advert Tech, N.D. Ill. 1:19-cv-03442, which appears in the Google Patents litigation list for this family). Even reading it conservatively and dating the first confirmed assertion of US8537242 itself to the 2021-06-11 Reolink suit, the transfer plainly ran ahead of assertion. Caveat: the RPX piece identifies three patents from the ~50-patent block without listing numbers, so I can't certify US8537242 was one of the three in the 2019 case; the claim-mapping to this specific patent is moderate confidence, the pre-litigation sequencing is not.

6. Bankruptcy fire-sale — NOT PRESENT.
No bankruptcy, receivership, or §363 sale appears anywhere in the record for Symagery, Psion Teklogix, or Harusaki. The 2007-12-13 transfer reads as a voluntary out-licensing/sale to a monetization vehicle, not a court-supervised liquidation.

7. Privateering — UNCLEAR.
The 2019 sequence is a monetization channel, not classic privateering: the transferor (IV Assets 99) is itself a non-practicing entity, so there is no operating company using Cedar Lane to attack competitors. RPX's phrase "apparent preparation for assertion" describes intent to assert but does not establish an opco sponsor. No SEC disclosure or Patent Progress/EFF coverage tying a practicing sponsor to this patent was found.

8. Defensive aggregator (anti-NPE) — NOT PRESENT (inverse confirmed).
The chain terminates at Cedar Lane Technologies Inc., an active, high-volume plaintiff — the opposite of neutralization. Nothing in the chain touches RPX, AST, LOT, Unified Patents, or OIN as an owner.

Verdict

NPE — high confidence.

The chain ends at Cedar Lane Technologies Inc., which took the patent by assignment recorded 2019-05-13 from Steephill Technologies LLC (2019-03-11), which had taken it directly from Intellectual Ventures Assets 99 LLC (2019-01-23) — three hops in under four months, with Cedar Lane incorporated in British Columbia on 2019-04-29, mid-sequence. That is at minimum three strong signals at once: shell-entity transfer (operating owner Psion Teklogix → Harusaki → Steephill → Cedar Lane), known asserter in the chain (both IV and Cedar Lane, the latter labeled a Patent Assertion Entity by Unified Patents and placed on Korea's core-NPE list), and cascading + pre-litigation transfer (recordation 2019-05-13, assertion activity reported by RPX by 2019-05-25, and US8537242 confirmed asserted in the 2021-06-11 Reolink W.D. Tex. case per the Stanford NPE database and Reolink's IPO diligence). The absence of any record of a Cedar Lane product, plus the ~96.6% settlement rate on its closed cases, completes the picture.

Two open items you should close at the Assignment Center before this is filed as final: (i) the reel/frame numbers and recorded correspondents — only Reel 020243/0226 is verified, and the repeat-correspondent signal (Greg Benoit / Pigott & Co.) turns on data I could not fetch; and (ii) the anomalous 2022-09-29 Moog Inc. / HSBC Bank USA "release by secured party" entry, which looks like a bulk recording unrelated to this chain but should be confirmed as such rather than assumed.

Verify: https://assignmentcenter.uspto.gov/ (legacy index: https://assignment.uspto.gov/patent/index.html ) — search by patent number 8537242.

I'll search for the prior-art citations listed on the face of US 8,537,242 and cross-check against the USPTO record.

Let me get the complete reference list and the USPTO/Justia citation record.

Let me pull the patent's own front-page "(56) References Cited" list and the Google Patents citation table to reconcile the Japanese citations.

Prior-Art Analysis — US 8,537,242 B2 ("Host interface for imaging arrays")

Scope note: This section addresses only the references cited on the face of US 8,537,242 and their §102 potential. Patent-identity, ownership, expiration, and litigation findings are in the earlier sections and are not repeated. The claim-element framework for independent claims 1, 6, 8 and 14 (FIFO + counter + programmable FIFO limit + interrupt / bus-request; both image data and clocking signals buffered at sensor rate and read out faster) is taken from the prior analysis and used as the mapping key below.

A. Sourcing of the reference list (and what I could and could not verify)

I assembled the citation list from three independent renderings and reconciled them:

Count reconciliation / discrepancy to flag. Google Patents states "Citations (39)." Justia's list totals 38 items (29 U.S. documents + 8 foreign + 1 NPL). Unified Patents' "Patent Art (42)" is not the same universe — it mixes the §56 citation list with family members and other similar documents (it leads with the parent US 6,972,790 and includes items such as JP H09-298714, JP H10-50966 and JP H11-261894 that Justia does not show). I could not resolve the 38-vs-39 count to a single authoritative number, and I did not have direct access to the USPTO PatentCenter "References Cited" pane for this patent. Treat the list below as complete-to-±2 rather than certified complete.

Two identifier discrepancies — reported literally, not auto-corrected:

1. Justia renders two Japanese citations as "JP 2008/314793" (11/1996) and "JP 2009/102907" (4/1997). Read literally these are 2008/2009 publications with 1996/1997 dates, which is internally impossible. The kanji-era equivalents almost certainly intended are JP H08-314793 and JP H09-102907, but per the strict-ID rule I am not silently renaming them.
2. For the December 1993 Japanese document, Justia prints "JP 05-326917" while the CourtListener OCR of the same front page reads "JP 05-226917". One of the two is a transcription error; I cannot tell which from the sources I reached.

B. §102 framework and the effective prior-art date

This is a pre-AIA case. Application 11/259,791 was filed October 27, 2005, but it is a division of 09/742,723 (filed December 21, 2000; now US 6,972,790 B2), which in turn claims benefit of provisional 60/177,496, filed January 21, 2000. Under 35 U.S.C. §120 the claims get the parent's Dec. 21, 2000 filing date for subject matter disclosed in the parent; the Jan. 21, 2000 provisional date applies only to the extent the provisional supports the claims. Practically:

• §102(b) applies to anything publicly available before Jan. 21, 1999 (one year before the earliest priority date). That captures essentially every reference on this list.
• Everything with a 1999 or 2000 date is §102(a) or §102(e) art.
• The three 2002–2004 U.S. pre-grant publications (2002/0101528, 2002/0191090, 2004/0004664) are not §102(b) art on their publication dates, but their underlying applications were filed in 1998, so they qualify as §102(e) art as of those earlier filing dates — which is presumably why the examiner cited them.
• US 6,972,790 (Suska) on this list is the parent patent itself, cited for relatedness/§102(e) completeness rather than as classic prior art. It is not an anticipation reference against its own divisional.

C. Tier 1 — references with genuine §102 anticipation potential

These are the ones whose disclosed subject matter overlaps the actual claim elements (FIFO buffering of sensor data, occupancy threshold, interrupt or bus-request/DMA handoff, on-die sensor-to-host interface).

D. Tier 2 — U.S. references relevant to individual claim elements

E. Tier 3 — cited but, on the available record, background/cumulative only

These appear on the face of the patent but do not map onto the distinguishing claim elements (FIFO occupancy threshold → interrupt or bus-request handoff). I list them for completeness and flag that I did not independently verify the subject matter of several.

• US 5,786,851 — Kondo et al. (July 28, 1998)
• US 6,063,655 — Donahue et al. (TI), virtual-reality playback (May 16, 2000)
• US 6,144,366 — Numazaki et al. (Nov. 7, 2000)
• US 6,298,370 — Tang et al. (Oct. 2, 2001)
• US 6,314,140 — Shelby (Nov. 6, 2001)
• US 6,344,877 B1 — Gowda et al. (IBM), "Image sensor with dummy pixel or dummy pixel array" (Feb. 5, 2002) — pixel-array structure only
• US 6,573,936 — Morris et al. (June 3, 2003)
• US 6,593,967 — McGarvey et al. (July 15, 2003)
• US 6,756,986 — Kuo et al. (June 29, 2004)
• US 6,757,019 — Hsieh et al. (June 29, 2004)
• US 6,833,862 — Li (Dec. 21, 2004)
• US 6,972,790 B2 — Suska — the parent patent (Dec. 6, 2005); cited for relatedness, not anticipation
• EP 0 932 302 A2 — Eastman Kodak Co., "A CMOS Active Pixel Digital Camera" (July 1999) — relevant to the integrated-camera concept (claims 6, 14) but a Kodak APS/camera-architecture disclosure rather than an interface-to-host disclosure
• JP 63-294182 — solid-state imaging device (Nov. 1988)
• JP 02-065380 — (March 1990; priority 1988-08-30)
• JP 05-326917 (CourtListener OCR: JP 05-226917) — Sanyo Electric, "Optical semiconductor device" (Dec. 1993)
• JP 2008/314793 (literally as printed; era-equivalent almost certainly H08-314793) — Nov. 1996
• JP 2009/102907 (literally as printed; era-equivalent almost certainly H09-102907) — Apr. 1997
• From the Unified Patents rendering, and not matched by Justia: JP H09-298714 A (Kodak, "Electronic still camera," published May 1996), JP H11-55571 A (Mitsubishi, "Image processing apparatus and image processing method," 1997), JP H11-261894 A ("Solid-state imaging device") and JP H10-50966 A ("Optical semiconductor integrated circuit," July 1996). Treat these four as unverified members of the same §56 list pending PatentCenter confirmation.

F. Non-patent literature (the only NPL item cited)

OmniVision Technologies, "OV511 Advanced Camera to USB Bridge, Data Sheet Rev. 1.0," July 17, 1998 — cited on the face of the patent as NPL (XP002293773), with the examiner pinpointing pages 6–14, Tables 9–11, and Figures 1–4, 6, 10, 12.

This is a §102(b) printed publication (published ~18 months before the Jan. 2000 priority date) and is arguably more dangerous than most of the patent citations, because the OV511 is literally a single-chip camera-plus-USB-host-interface device — the commercial embodiment of the patent's stated problem. It is the most likely §102 basis for claims 1, 6, 8 and 14, and the pinpoint citations show the examiner actually engaged with it. Its being a data sheet rather than a patent does not reduce its §102(b) status.

G. Bottom line and honest caveats

1. The most relevant prior art, in order of §102 risk, is: (1) US 6,493,025 (Kiriyama/Sanyo); (2) the OmniVision OV511 data sheet (NPL); (3) US 6,947,085 (Booth/Intel); (4) US 6,024,149 (Chow); (5) JP 07-114510 (FIFO-threshold DMA); (6) US 5,752,266 (Miyawaki) for the claim-8 arbitration element; (7) US 5,587,953 (Chung) for the FIFO element.
2. Crucial framing: every one of these references was of record and considered by the examiner, and the patent nonetheless issued with claims 1–23 intact. So none of them was, in the examiner's view, an anticipating reference. My "potentially anticipates" designations are my own analytical mapping, not a record fact — and they should be tested against the actual claim language, which I did not have in complete form for claims 2–5 (see the prior section's uncertainty note).
3. Unverified items: I could not reach the USPTO PatentCenter "References Cited" pane directly, and I did not independently confirm the subject matter of the Tier-3 U.S. patents (e.g., 6,298,370; 6,314,140; 6,573,936; 6,593,967; 6,756,986; 6,757,019; 6,833,862; 5,786,851; 6,144,366). Any of those descriptions should be re-checked before being relied on.
4. Identifier integrity: the "JP 2008/314793" / "JP 2009/102907" renderings and the JP 05-326917-vs-05-226917 conflict are reported as found and not corrected.
5. Reference-count reconciliation failed: 38 (Justia) vs. 39 (Google) vs. 42 (Unified, a partly different universe). I am flagging this rather than papering over it.
6. Nothing in the retrieved sources contradicts the patent text supplied in the prompt.

I'll research the prior-art references cited on this patent's face and in its file history before building the § 103 analysis.

I now have the "References Cited" list. Let me characterize the key references so the combinations are grounded in actual disclosures rather than titles alone.

Let me pull details on the remaining key references and check for any post-grant challenge (IPR/reexam) that would have already framed an obviousness case.

Obviousness Analysis of US 8,537,242 B2 under 35 U.S.C. § 103

0. Scope, sources, and two corrections to the earlier sections

Sources used for the "Prior Art section." The Google Patents record for US 8,537,242 supplies the Prior art keywords ("fifo, image data, memory, signal, rate") and the Prior art date of 2000-01-21, but the enumerated reference list is in the "References Cited" section. I retrieved that list from the Justia record (https://patents.justia.com/patent/[8537242](/patent/8537242)) and corroborated it against the Unified Patents "Patent Art (42)" listing for the same patent (https://portal.unifiedpatents.com/patents/patent/8537242), plus full-text retrieval for the three most load-bearing references. Where I could only confirm a reference's title and date and not its disclosure, I say so.

Correction 1 — claim 6 is dependent, not independent. The earlier section listed claims 1, 6, 8 and 14 as independent. Primary-source claim text (the '242 claim set filed as Exhibit A in Cedar Lane Technologies Inc. v. Fantasia Trading LLC, D. Del. 1:21-cv-01428, https://www.courtlistener.com/docket/60631839/1/1/) shows claim 6 recites "The method of claim 1, further comprising: receiving clocking signals associated with the image data; storing the image data and the clocking signals in the FIFO memory at a first rate…" Claim 6 therefore depends from claim 1. The independent claims are 1, 8 and 14, and that same exhibit resolves the earlier "claims 2–5 unverified" gap: claim 2 = generating a FIFO limit signal, interrupt enable signal and output bus width signal; claim 3 = transfer in response to a processor command; claim 4 = first rate/second faster rate; claim 5 = first rate associated with the array / second rate associated with the processor. This correction narrows the obviousness surface — there are fewer independent claims to attack than previously assumed.

Correction 2 — literal identifiers preserved. The reference list as displayed shows "2008/314793 November 1996" and "2009/102907 April 199…" among the JP documents. Interpreted literally they are nonsensical as JP publication numbers for those dates. I flag this as an OCR/format artifact in the aggregator display and do not auto-correct it; these two documents are omitted from the grounds below for that reason.

1. Governing law and posture

The application 11/259,791 was filed 2005-10-27 but claims benefit back to provisional 60/177,496 (2000-01-21) with the parent non-provisional 09/742,723 filed 2000-12-21. Because the effective filing date predates 2013-03-16, pre-AIA § 103(a) governs, with the Graham v. John Deere framework as elaborated by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007): (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations. Under KSR, the "teaching, suggestion, or motivation" test is one permissible rationale among several; others include (a) combining prior art elements according to known methods to yield predictable results, (b) simple substitution of one known element for another, (c) use of a known technique to improve a similar device in the same way, and (d) "obvious to try" where there is a finite number of identified, predictable solutions. MPEP 2143(I).

Level of ordinary skill (proposed): a B.S. in electrical engineering (or equivalent) with 2–4 years of experience in CMOS image-sensor design and/or digital system bus interfaces, or an M.S. with 1–2 years — a person comfortable with FIFO architecture, counters/comparators, interrupt controllers, and DMA/bus-arbitration protocols. The '242 specification is written at exactly this level (statement of invention describes the FIFO, decoder, configuration registers and counter in textbook terms).

2. The cited prior-art corpus, with its § 102 status

Critical date for pre-AIA § 102(b) statutory bars: 1999-01-21 (one year before the 2000-01-21 priority date; the provisional benefit is available for this purpose, MPEP 2133.01).

Confidence note. I verified disclosure content only for Booth (US 6,947,085), Kiriyama (US 6,493,025) and Ueno (US 6,460,095). For Chow (US 6,021,449) and JP 07-114510 I have titles and dates but not verified text; my searches for their full text were cut off. The grounds below that lean on those two are stated with that caveat, and each should be re-verified against the actual documents before being relied on formally.

3. What the claims require (independent claims)

• Claim 1: receive image data from an imaging array → store in FIFO → update a FIFO counter on reads and writes → compare count to a FIFO limit → generate an interrupt to request the processor to unload, gated by an interrupt-enable signal being valid → transfer in response to the interrupt.
• Claim 8: same front end, but instead of an interrupt → generate a bus request to a bus arbitration unit for access to an output bus → transfer upon receiving a grant signal.
• Claim 14: receive image data and associated clocking signals from the array → store both at a rate based on those clocking signals, the clocking signals comprising at least one of a video system clock, row clock or frame clock → generate a request when a predetermined amount is stored → transfer in response.
• Dependents add: FIFO-limit / interrupt-enable / output-bus-width signals (2, 9); transfer on processor command (3, 10); first-rate/second-rate decoupling (4, 5, 11, 12); clock-signal species (7, 13); interrupt-as-the-request (15).

4. Grounds of rejection

Ground 1 — Claims 1, 2, 3(–5) obvious over Booth (US 6,947,085) in view of Kiriyama (US 6,493,025)

Booth is the closest art and is nearly anticipatory in structure. Booth discloses a CMOS pixel array 11 whose readout is coupled to an interface control 32 that "may include a buffer memory," and expressly states that "a common buffer memory implementation employs a First In First Out (FIFO) memory architecture. As each datum arrives at the interface control 32, it passes through a write counter 37 and is stored in the buffer memory 36. As each datum leaves the interface, it is read from the buffer memory 36 and passes through a read counter 38." When all locations are used, "the buffer is full," and "the data overload sensor 33 senses the full buffer memory through a comparing circuit 39." Booth's FIG. 3c alternative "may establish a protocol with the data processing circuitry when the datum is transmitted," and Booth concedes that "[t]his system of protocol is generally known in the art."

Mapping to claim 1:

Motivation to combine is supplied by the references themselves, which is the strongest form:

1. Same problem, same field. Booth: the sensor "would generate a high frame rate in comparison with a processing rate of a data processing circuitry"; Kiriyama: sensors "output several tens of frames of image data per second. Ordinary personal computers can however receive only several frames of image data per second." Both are image-sensor-to-host interfaces (analogous art under In re Bigio/In re Clay).
2. Express reason to use interrupts. Kiriyama's stated benefit is that the interrupt lets the host "perform[] … processing … in a time-sharing manner." The '242 specification makes the identical point about its interrupt: "The use of an interrupt signal S_I … allows the processor to multi-task." Where the reference states the very advantage the patent claims, the motivation is not speculative.
3. Simple substitution. Booth's flow-control mechanism is a polled/halt-and-protocol handshake; Kiriyama's is an interrupt. Substituting a known signaling mechanism for another known signaling mechanism, to obtain its known benefit, is a classic KSR "simple substitution" ground.
4. Known-technique-to-improve-a-similar-device. FIFO-threshold-plus-interrupt is precisely the technique that JP 07-114510 ("FIFO threshold control DMA control method," 1995-02-03) and Chow (US 6,021,449) apply to video data flow.

The "interrupt enable signal being valid" gating and the programmable "FIFO limit" (claim 2) are the only limitations Booth does not literally show; they are met by Chow's overflow-prevention control (blocking/resuming on a threshold) and JP 07-114510, and independently are routine register-level design choices — a mask bit and a comparator reference value — with no unexpected result.

Claim 3 (transfer on a processor command) is met by Booth's FIG. 3c protocol and by Kiriyama's "read instruction signal … supplied from the personal computer."

Ground 2 — Claims 8 and 9–13 obvious over Booth in view of Miyawaki (US 5,751,226) and JP 07-114510

Claim 8 swaps the interrupt for a bus request to a bus arbitration unit and a grant signal.

• Booth supplies the FIFO, counter, and threshold comparison as above.
• Miyawaki (US 5,751,226) is directly on point on the arbitral element: its title — "Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method" — discloses arbitration/memory-access priority being changed based on the state of the memory, i.e., the reference teaches granting bus/memory access as a function of how full the buffer is. That is the core of claim 8(e) and (f).
• JP 07-114510 supplies threshold-controlled DMA — a transfer that necessarily entails bus requests and grants — in the FIFO context.
• Reinert (US 5,581,280) and Zimmermann (US 6,704,310) provide corroborating video-bus-mastery teachings.

The motivation is that a CPU interrupt imposes host software latency whereas bus-master DMA lets the host memory receive data "without the CPU 10 being disturbed to make the transfer" — the '242's own stated advantage for the FIG. 6/7 embodiment, and the standard rationale for DMA. Both routes (interrupt vs. bus-master/DMA) were known alternatives for the same purpose; choosing between two known mechanisms with predictable trade-offs is obvious under KSR.

Dependents 9–13 are met by Booth/Kiriyama/Ueno as mapped in Ground 3, plus the bus-arbitration teachings above.

Ground 3 — Claims 4, 5, 6, 11, 12 (rate decoupling) obvious over Booth in view of Ueno (US 6,460,095) and Kiriyama

The rate-decoupling limitations are the weakest link in the chain and deserve separate treatment, because Booth shows the opposite rate relationship: in Booth the sensor produces 30 fps and the interface delivers 10 fps — i.e. out-rate slower than in-rate — whereas claim 4 requires the FIFO transfer-out rate to be faster than the store rate.

• Ueno (US 6,460,095) supplies the missing teaching directly: it sizes an input buffer so that CAPW ≥ TW × T1, where T1 is the continuous input rate and TW the maximum interval between bus access permissions. The entire premise is that input arrives continuously at T1 while the bus admits data in faster, intermittent grants — i.e., drain bursts at bus speed. Ueno's abstract: "transfer data continuously input or output to/from a main memory without any interruption and … on a general-purpose bus such as a PCI bus."
• Kiriyama supplies the host-vs-sensor rate mismatch justification and the interrupt that triggers the burst.
• For claim 6/7 and claim 14's requirement that the clocking signals themselves be stored (row clock, frame clock, video system clock), the closest cited art is Kiriyama's sync detector 113 / timing controller 114, which detect and propagate vertical- and horizontal-scan timing pulses, and Booth's FIG. 3c protocol; and EP 0 932 302 (Kodak, CMOS active pixel digital camera) / US 6,721,008 (Lee, "Integrated CMOS active pixel digital camera") which are CMOS-APS timing-generator references.

Candid assessment: I have not verified a cited reference that expressly discloses writing the row/frame clock signals into the same FIFO as the pixel data at a rate set by those clocks. Claim 14 and its dependents 6/7/13 are therefore the claims most likely to survive a § 103 challenge on this record, and the ground for them should be built on references directed to video buffers that carry embedded timing/sync information, which I have not yet verified. This is an evidentiary gap, not a legal conclusion.

Ground 4 — Claim 14 obvious over Kiriyama in view of Booth and Ueno

Claim 14 is the broadest independent claim in one respect — it does not require a FIFO, a counter, or an interrupt; it requires only (i) receiving image data and associated clocking signals, (ii) storing both at a clock-determined rate, the clocking signals comprising a video system, row, or frame clock, (iii) generating a request when a predetermined amount is stored, and (iv) transferring in response. Kiriyama's line memory continuously storing image data plus its timing controller generating the transfer instruction on accumulation, combined with Booth's counter/comparator and Ueno's buffering-to-bridge-rates, renders this obvious on the same rationales as Ground 1, with the "request" limitation satisfied by Kiriyama's interruption signal.

5. Motivation to combine, consolidated (MPEP 2143 categories)

The '242's own specification aids the analysis: it describes the interface at a functional-block level (chip command decoder 45, FIFO configuration registers 46, FIFO read control 47, interrupt generator 48, array registers 49), i.e., from standard parts, and its own background section says the interface "may include interrupt signals to the processor, and enough memory space for a number of pixels."

6. Rebuttal of likely patent-owner arguments

1. "Booth teaches away from buffering." No — Booth criticizes large RAM frame buffers as expensive ("large banks of RAMs are required"). Its own FIG. 3b embodies a FIFO buffer. There is no teaching away from the claimed FIFO.
2. "The references are non-analogous (video encoder vs. image sensor)." All are directed to moving pixel/video data across a digital bus to a processing system; they are from the same field of endeavor and, at minimum, reasonably pertinent to the problem Booth itself articulates.
3. "The interrupt-enable gating and programmable limit are inventive." "Predetermined relationship," "predetermined level," and "FIFO limit" are result-effective variables; a mask bit is the definitional form of an interrupt-enable. No unexpected result is disclosed.
4. Secondary considerations. No evidence of unexpected results, long-felt-but-unsolved need, failure of others, copying, or licensing because of the merits appears in the record. The 2019–2023 Cedar Lane campaign produced voluntary dismissals without a merits ruling and nominal settlements (e.g., a reported US$10,000 worldwide perpetual license), which is weak-to-absent evidence of nexus between commercial success and the claimed subject matter.
5. Contextual note (not itself a § 103 ground). The '242 issued subject to a terminal disclaimer and accrued 1,584 days of § 154(b) term adjustment — a combination consistent with a lengthy, contested prosecution (2005 filing → 2013 issuance on a 2000-priority disclosure) including a double-patenting rejection over the parent, US 6,972,790, the obviation of which required the applicant to concede that the divisional claims were not patentably distinct from the parent's appliance claims. That is a § 101 ODP issue rather than § 103, but the underlying "not patentably distinct" reasoning points the same way as the grounds above.

7. Limits of this analysis and what would change it

• File history is decisive and I do not have it. The eight-year pendency strongly implies the Examiner applied several of these same references under § 103 and the applicant argued or amended around them; whatever the applicant distinguished, and whatever remarks were made, would narrow or reshape every ground above. The prosecution history should be pulled from the USPTO Patent Center before any ground is finalized.
• Unverified disclosures. Chow (US 6,021,449) and JP 07-114510 are cited on title and date only; their use for the "FIFO limit"/"interrupt mask" and DMA elements needs confirmation against the documents.
• The clock-signal-storage limitation (claims 6, 7, 13, 14) is the least-supported element on the cited record, as noted in Ground 3.
• No post-grant challenge located. I did not find an IPR/PGR or reexamination of US 8,537,242 in the sources reached (my searches for Cedar Lane IPR activity were cut off), so this analysis is not a restatement of any prior tribunal's holding.
• Practical relevance is now historical. Per the earlier section and the record — expiration recorded 2025-01-22, "Expired – Fee Related" — the patent is no longer enforceable, so this § 103 analysis is retrospective: it matters for validity-history context and for freedom-to-operate work on the sibling patents (US 6,972,790; US 6,472,527) rather than for any live infringement exposure.

Bottom line: on the cited prior-art record, independent claim 1 is likely obvious over Booth in view of Kiriyama (with Chow/JP 07-114510 supplying the programmable limit and interrupt mask), and claim 8 is likely obvious over Booth in view of Miyawaki and JP 07-114510. Claim 14, and its clocking-signal dependents, is the strongest candidate for survival because the cited references do not clearly show row/frame clock signals being written into the buffer alongside the pixel data — that limitation, not the FIFO/threshold/interrupt architecture, is where a validity defense would have to be fought.