US 8368201

US Patent 8368201: Method for Embedding a Component in a Base

Title: Method for embedding a component in a base

Assignee: Imberatek LLC (Current Assignee listed first, per provided text. Original Assignee: Imbera Electronics Oy)

Inventor: Risto TUOMINEN

Filing Date: July 18, 2011

Issue Date: February 5, 2013

Abstract: The patent describes a method for embedding semiconductor components, or at least some of them, into a base (such as a circuit board) during the base's manufacture. This involves creating through-holes for the components in the base, extending between its first and second surfaces. A polymer film is then spread over the second surface, covering these through-holes. Before or after partial hardening of the polymer film, the semiconductor components are placed into the holes from the first surface and pressed against the polymer film to adhere. The method also includes forming a conductive pattern in the base before component placement, with the component aligned relative to these patterns.

Plain-Language Overview of Independent Claim 1:

Independent Claim 1 describes an electronic module, not a method, with the following key features:

• A baseboard: This forms the foundation of the module, having a top (first) surface and a bottom (second) surface.
• A hardened insulating polymer layer: This layer is situated on the second (bottom) surface of the baseboard and is hardened to provide insulation.
• At least one component within the baseboard: One or more electronic components are embedded inside the baseboard. This component has contact areas on its first surface, and this first surface of the component is positioned directly against the hardened insulating polymer layer.
• Conductive patterns: These patterns are present on the hardened insulating polymer layer.
• Conductors within the hardened insulating polymer layer: These conductors are specifically designed to create electrical connections between at least some of the conductive patterns on the polymer layer and at least some of the contact areas of the embedded component.

CAFC 2026 Dockets:
A search of CAFC 2026 dockets did not identify any cases specifically listing US patent 8368201.

Based on the provided patent text for US8368201, the following litigation is known:

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:22-cv-00233
  • Plaintiff(s): Not explicitly stated in the provided snippet.
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Litigation

• Jurisdiction: California Northern District Court

  • Case Number: 5:25-cv-02206
  • Plaintiff(s): Not explicitly stated in the provided snippet.
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Litigation

• Jurisdiction: California Northern District Court

  • Case Number: 3:25-cv-02206
  • Plaintiff(s): Not explicitly stated in the provided snippet.
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Litigation

• Jurisdiction: PTAB

  • Case Number: IPR2022-01597
  • Plaintiff(s): Petitioner (details not explicitly stated)
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Settlement

• Jurisdiction: PTAB

  • Case Number: IPR2025-00581
  • Plaintiff(s): Petitioner (details not explicitly stated)
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Settlement

• Jurisdiction: PTAB

  • Case Number: IPR2025-01247
  • Plaintiff(s): Petitioner (details not explicitly stated)
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Not Instituted - Procedural

• Jurisdiction: Texas Western District Court

  • Case Number: 1:24-cv-00129
  • Plaintiff(s): Not explicitly stated in the provided snippet.
  • Defendant(s): Not explicitly stated in the provided snippet.
  • Filing Date: Not explicitly stated in the provided snippet.
  • Outcome/Current Status: Litigation

Additionally, the patent notes "First worldwide family litigation filed" with a link to Darts-ip, indicating broader international litigation related to the patent family, but specific details for US8368201 are not provided in the snippet.

Proceedings overview

There has been one AIA trial proceeding filed on US Patent 8368201. This proceeding, IPR2025-01247, resulted in a discretionary denial of institution, leaving all claims of the patent untested by the PTAB.

IPR2025-01247 — Unimicron Technology Corp. v. Risto TUOMINEN

• Type: Inter Partes Review
• Filed: 2025-07-08
• Status: Discretionary Denial
• Judge panel: Not publicly available from the provided data.
• Petition grounds: Not publicly available from the provided data.
• Institution decision: Denied (Discretionary Denial) - 2025-12-23. The panel's reasoning for the discretionary denial is not detailed in the provided snippet.
• Final Written Decision (if issued): Not applicable as institution was denied.
• Settlement / termination: Not applicable.
• Appeal: Not applicable, as institution was denied.
• Defensive value: This proceeding indicates that Unimicron Technology Corp. attempted to challenge the patent through an IPR but was denied institution on discretionary grounds. This means the merits of the patentability of the claims were not addressed, and the claims remain unexamined by the PTAB. Any new IPR petition would need to overcome the discretionary denial precedent, and could face similar issues.

Strategic summary

Currently, all claims of US8368201 (specifically, the single independent Claim 1) are untested by the PTAB. The sole IPR proceeding, IPR2025-01247, resulted in a discretionary denial, meaning the PTAB did not reach the merits of the patentability challenge. Therefore, no claims have been canceled or sustained through IPR.

The estoppel landscape related to IPR2025-01247 would prevent Unimicron Technology Corp. (and its privies) from raising the same or reasonably could have raised grounds in a future PTAB proceeding against US8368201. However, since the institution was denied on discretionary grounds, rather than on the merits of the prior art, the specific prior-art grounds raised in that petition are not publicly known from the provided information. For other potential defendants, all prior-art grounds remain theoretically available, assuming they are not in privity with Unimicron.

The fact that the patent has faced only one IPR, which was denied institution, suggests that the patent owner has so far successfully defended against challenges at the institution phase. This could signal a robust patent, or it could simply mean the petitions filed thus far have had procedural weaknesses or faced unfavorable discretionary rulings.

Recommended next steps

Given that all claims of US8368201 are currently unchallenged by PTAB proceedings (due to the discretionary denial of the single IPR filed), a defendant facing assertion of this patent would need to conduct a thorough prior art search to identify strong invalidity arguments. If new prior art or compelling arguments can be found, a new IPR petition could be considered, though it would need to address potential discretionary denial issues raised in IPR2025-01247. There are no active proceedings or upcoming trial-stage milestones for this patent in the PTAB. The absence of PTAB activity on the merits means there is no FWD to link to or quote regarding claim dispositions.

Inventors

• Risto TUOMINEN: CEO and founder of Imbera Electronics Oy at the time of filing.

Original assignee

The original assignee was Imbera Electronics Oy, a pioneering Finnish company specializing in advanced embedded electronics packaging technology and manufacturing solutions. Their primary line of business was developing and providing embedded technology that allows for smaller, more efficient electronic devices, used in products like smartphones, tablets, avionics, and power distribution systems. Imbera Electronics Oy shipped products embodying the claims, specifically their Integrated Module Board (IMB) solution.

Imbera Electronics Oy was acquired by GE Healthcare Finland Oy, in partnership with GE Idea Works, on September 27, 2013, for its technology and intellectual property. Therefore, it is no longer an independent operating entity.

Assignment timeline

• 2020-01-22 (executed) / recorded 2020-01-28 — Reel 052445/0969

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: TUOMINEN, RISTO
  • Assignee: GE EMBEDDED ELECTRONICS OY
  • Correspondent: ROTHWELL, FIGG, ERNST & MANBECK, P.C. (Washington, DC)
  • Context: Confirmatory assignment from the inventor to the GE subsidiary that acquired the original assignee's assets.

• 2020-02-18 (executed) / recorded 2020-02-21 — Reel 052570/0675

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: GE EMBEDDED ELECTRONICS OY
  • Assignee: IMBERATEK, LLC
  • Correspondent: ROTHWELL, FIGG, ERNST & MANBECK, P.C. (Washington, DC). This correspondent recurs in this chain.
  • Context: Transfer from a GE subsidiary to an entity commonly associated with patent assertion.

• 2020-06-05 (executed) / recorded 2020-06-05 — Reel 053077/0371

  • Conveyance: PATENT SECURITY AGREEMENT
  • Assignor: ACACIA RESEARCH GROUP LLC, AMERICAN VEHICULAR SCIENCES LLC, BONUTTI SKELETAL INNOVATIONS LLC, CELLULAR COMMUNICATIONS EQUIPMENT LLC, INNOVATIVE DISPLAY TECHNOLOGIES LLC, LIFEPORT SCIENCES LLC, LIMESTONE MEMORY SYSTEMS LLC, MERTON ACQUISITION HOLDCO LLC, MOBILE ENHANCEMENT SOLUTIONS LLC, MONARCH NETWORKING SOLUTIONS LLC, NEXUS DISPLAY TECHNOLOGIES LLC, PARTHENON UNIFIED MEMORY ARCHITECTURE LLC, R2 SOLUTIONS LLC, SAINT LAWRENCE COMMUNICATIONS LLC, STINGRAY IP SOLUTIONS LLC, SUPER INTERCONNECT TECHNOLOGIES LLC, TELECONFERENCE SYSTEMS LLC, UNIFICATION TECHNOLOGIES LLC
  • Assignee: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
  • Correspondent: BLANK ROME LLP (New York, NY). This correspondent recurs in this chain.
  • Context: Securitization involving a broad portfolio of patents, including this one, granted to a collateral agent by entities associated with Acacia Research.

• 2020-07-08 (executed) / recorded 2020-07-08 — Reel 053154/0254

  • Conveyance: RELEASE OF SECURITY INTEREST IN PATENTS
  • Assignor: STARBOARD VALUE INTERMEDIATE FUND LP
  • Assignee: SAINT LAWRENCE COMMUNICATIONS LLC, SUPER INTERCONNECT TECHNOLOGIES LLC, LIMESTONE MEMORY SYSTEMS LLC, BONUTTI SKELETAL INNOVATIONS LLC, CELLULAR COMMUNICATIONS EQUIPMENT LLC, NEXUS DISPLAY TECHNOLOGIES LLC, LIFEPORT SCIENCES LLC, AMERICAN VEHICULAR SCIENCES LLC, MOBILE ENHANCEMENT SOLUTIONS LLC, MONARCH NETWORKING SOLUTIONS LLC, STINGRAY IP SOLUTIONS LLC, R2 SOLUTIONS LLC, PARTHENON UNIFIED MEMORY ARCHITECTURE LLC, ACACIA RESEARCH GROUP LLC, TELECONFERENCE SYSTEMS LLC, UNIFICATION TECHNOLOGIES LLC
  • Correspondent: BLANK ROME LLP (New York, NY). This correspondent recurs in this chain.
  • Context: Release of the previously granted security interest.

• 2020-10-20 (executed) / recorded 2020-10-22 — Reel 053654/0254

  • Conveyance: STATEMENT REGARDING SECURITY INTEREST INCORRECTLY RECORDED AGAINST PATENTS
  • Assignor: ACACIA RESEARCH GROUP LLC, R2 SOLUTIONS LLC
  • Assignee: IMBERATEK, LLC
  • Correspondent: BLANK ROME LLP (New York, NY). This correspondent recurs in this chain.
  • Context: Correction stating that a security interest was incorrectly recorded and confirming Imberatek, LLC as the intended assignee.

• 2020-12-30 (executed) / recorded 2021-01-07 — Reel 053916/0471

  • Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 053654 FRAME 0254. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST GRANTED PURSUANT TO THE PATENT SECURITY AGREEMENT PREVIOUSLY RECORDED.
  • Assignor: STARBOARD VALUE INTERMEDIATE FUND LP
  • Assignee: R2 SOLUTIONS LLC
  • Correspondent: BLANK ROME LLP (New York, NY). This correspondent recurs in this chain.
  • Context: Corrective assignment confirming release of security interest and indicating R2 Solutions LLC was the intended assignee for a prior record.

• 2021-03-29 (executed) / recorded 2021-04-01 — Reel 054238/0023

  • Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 052853 FRAME: 0153. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
  • Assignor: R2 SOLUTIONS LLC
  • Assignee: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
  • Correspondent: BLANK ROME LLP (New York, NY). This correspondent recurs in this chain.
  • Context: Corrective assignment clarifying an assignor name and confirming an assignment to Starboard Value as collateral agent.

Timeline diagram

timeline
    title Ownership of US 8368201
    2011 : Filed by Imbera Electronics Oy
    2013 : Issued
    2020 : Inventor assigned to GE Embedded
         : GE Embedded to Imberatek LLC
         : Patent security agreement
         : Security interest released
         : Security interest correction
    2021 : Corrective assignment
         : R2 Solutions to Starboard Value

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from GE EMBEDDED ELECTRONICS OY to IMBERATEK, LLC on 2020-02-18 / recorded 2020-02-21 (Reel 052570/0675). Imberatek, LLC's name and its association with known NPEs (Acacia Research Group LLC and R2 Solutions LLC, as seen in Reel 053077/0371, 053154/0254, 053654/0254) are strong indicators of a shell entity.
2. Known asserter in the chain — Present. ACACIA RESEARCH GROUP LLC is explicitly named as an assignor (Reel 053077/0371, Reel 053654/0254) and assignee (Reel 053154/0254) in the patent's assignment history. Acacia Research Corp is a prominent, well-known Non-Practicing Entity. R2 SOLUTIONS LLC, another entity appearing in the chain (Reel 053077/0371, 053154/0254, 053654/0254, 053916/0471, 054238/0023), is also associated with patent assertion.
3. Repeat correspondent across the chain — Present. BLANK ROME LLP (New York, NY) served as the correspondent for five consecutive complex security and corrective assignments between 2020-06-05 (Reel 053077/0371) and 2021-03-29 (Reel 054238/0023). ROTHWELL, FIGG, ERNST & MANBECK, P.C. also appears as correspondent for the first two recorded assignments (Reel 052445/0969 and Reel 052570/0675).
4. Cascading transfers — Present. A series of highly complex security agreements, releases, and corrective assignments (Reel 053077/0371, 053154/0254, 053654/0254, 053916/0471, 054238/0023) occurred rapidly between June 2020 and April 2021, involving numerous NPE-affiliated entities and a collateral agent, demonstrating a complex and rapid shuffling of interests.
5. Pre-litigation transfer — Present. The transfer to Imberatek, LLC (Reel 052570/0675) occurred in February 2020, and the series of security/corrective assignments concluded in April 2021. The first recorded district court litigation case (2:22-cv-00233 in Texas Eastern District Court) was filed in 2022. The PTAB IPR2022-01597 was also filed in 2022. This demonstrates that the patent was transferred into the NPE ecosystem prior to the commencement of litigation.
6. Bankruptcy fire-sale — Not present. The patent originated from an operating company (Imbera Electronics Oy) that was acquired by GE, not one that underwent bankruptcy.
7. Privateering — Unclear. While GE divested the patent to an NPE-affiliated entity, there is no direct evidence to suggest GE is using Imberatek, LLC or other NPEs for covert assertion on its behalf against competitors.
8. Defensive aggregator (anti-NPE) — Not present. The chain clearly involves entities associated with patent assertion, with Starboard Value Intermediate Fund LP acting as a collateral agent for a portfolio involving known NPEs, rather than a defensive aggregator.

Verdict

NPE — high confidence

The extensive assignment history clearly indicates a transfer from an operating company (GE Embedded Electronics Oy) to a shell entity (Imberatek, LLC) in February 2020 (Reel 052570/0675). This shell entity is part of a broader network involving a well-known NPE, Acacia Research Group LLC, as evidenced by the security agreements and corrective assignments (e.g., Reel 053077/0371, Reel 053154/0254). The presence of multiple NPE-affiliated entities, cascading transfers, and a repeat correspondent (Blank Rome LLP) further solidify this conclusion. The subsequent litigation activities in 2022-2025 follow this transfer into the NPE ecosystem.

Verification: USPTO Assignment Center Search for US8368201

To identify the most relevant prior art for US patent 8368201, I will examine the patent citations listed within the patent itself. Since the patent states its priority date is January 31, 2002, I will consider prior art references that have a publication or filing date before this date, as per 35 U.S.C. § 102 (pre-AIA, given the priority date).

Here's an analysis of the cited prior art:

Most Relevant Prior Art for US Patent 8368201

The following patents are cited as prior art in US patent 8368201:

1. US4246595A: Electronics circuit device and method of making the same

   • Full Citation: US4246595A
   • Publication Date: January 20, 1981
   • Filing Date: March 8, 1977
   • Brief Description: This patent describes an electronic circuit device and its manufacturing method, where circuit components are embedded within an insulating substrate. The components are placed in recesses or holes, and then the substrate is formed around them.
   • Potential Anticipation (35 U.S.C. § 102): US4246595A could potentially anticipate aspects of Claim 1, specifically the concept of "at least one component within the baseboard" and a "hardened insulating polymer layer" formed around it, especially if the "baseboard" is interpreted broadly to encompass an insulating substrate into which components are embedded. The patent's focus on embedding components in an insulating substrate and forming the circuit around them aligns with the general concept of the base and component integration in US8368201.

2. US4783695A: Multichip integrated circuit packaging configuration and method

   • Full Citation: US4783695A
   • Publication Date: November 8, 1988
   • Filing Date: September 26, 1986
   • Brief Description: This patent details a multichip integrated circuit packaging configuration and a method for its fabrication. It involves placing multiple unpackaged semiconductor dice into cavities in a substrate and then encapsulating them.
   • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "at least one component within the baseboard" feature of Claim 1, particularly if "component" is understood as an unpackaged semiconductor die. The concept of placing components into cavities and encapsulating them within a base could potentially anticipate the embedding aspect.

3. US4894115A: Laser beam scanning method for forming via holes in polymer materials

   • Full Citation: US4894115A
   • Publication Date: January 16, 1990
   • Filing Date: February 14, 1989
   • Brief Description: This patent describes a method for forming via holes in polymer materials using a laser beam. While it doesn't directly address component embedding, it pertains to a manufacturing technique relevant to circuit boards.
   • Potential Anticipation (35 U.S.C. § 102): This reference primarily relates to manufacturing processes (e.g., how holes could be made), rather than the structural elements of Claim 1. Therefore, it is less likely to anticipate Claim 1 directly but is important for understanding the technical landscape of forming holes in polymer layers.

4. US5102829A: Plastic pin grid array package

   • Full Citation: US5102829A
   • Publication Date: April 7, 1992
   • Filing Date: July 22, 1991
   • Brief Description: This patent discloses a plastic pin grid array package for integrated circuits, where the integrated circuit die is encapsulated within a plastic body.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US4783695A, this reference is relevant to the concept of encapsulating a component within a package. It could anticipate the "at least one component within the baseboard" and "hardened insulating polymer layer" aspects of Claim 1, especially concerning the packaging of semiconductor components.

5. JPH04283987A: Electronic circuit device and manufacture thereof

   • Full Citation: JPH04283987A
   • Publication Date: October 8, 1992
   • Filing Date: March 13, 1991
   • Brief Description: This Japanese patent application describes an electronic circuit device and its manufacturing method, where electronic components are mounted on a flexible substrate and then covered with a resin layer.
   • Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate elements of Claim 1, particularly the embedding of components ("at least one component within the baseboard") and the use of a "hardened insulating polymer layer" to cover them, especially given the flexibility aspect mentioned in the US8368201 description.

6. US5162613A: Integrated circuit interconnection technique

   • Full Citation: US5162613A
   • Publication Date: November 10, 1992
   • Filing Date: July 1, 1991
   • Brief Description: This patent describes a technique for interconnecting integrated circuits, focusing on creating electrical connections between layers.
   • Potential Anticipation (35 U.S.C. § 102): This reference is most relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" aspect of Claim 1, as it deals with interconnection techniques between circuit layers.

7. US5208188A: Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process

   • Full Citation: US5208188A
   • Publication Date: May 4, 1993
   • Filing Date: October 2, 1989
   • Brief Description: This patent describes a process for making a multilayer lead frame assembly and a multilayer integrated circuit die package, involving embedding die within layers.
   • Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to the "at least one component within the baseboard" and the overall structure described in Claim 1, particularly its focus on embedding integrated circuit dice within a multilayer structure.

8. US5216806A: Method of forming a chip package and package interconnects

   • Full Citation: US5216806A
   • Publication Date: June 8, 1993
   • Filing Date: September 1, 1992
   • Brief Description: This patent describes a method for forming a chip package and its interconnects, including embedding a chip and forming connections.
   • Potential Anticipation (35 U.S.C. § 102): This patent directly addresses the formation of a chip package with interconnects, which aligns with several elements of Claim 1, including the embedded component, insulating layer, and conductors for electrical contacts.

9. US5227338A: Three-dimensional memory card structure with internal direct chip attachment

   • Full Citation: US5227338A
   • Publication Date: July 13, 1993
   • Filing Date: April 30, 1990
   • Brief Description: This patent describes a three-dimensional memory card structure where chips are directly attached internally within the structure.
   • Potential Anticipation (35 U.S.C. § 102): This is highly relevant to the "at least one component within the baseboard" feature of Claim 1, especially in the context of creating a compact, multi-layered electronic module. The "internal direct chip attachment" directly relates to embedding components.

10. US5248852A: Resin circuit substrate and manufacturing method therefor

    • Full Citation: US5248852A
    • Publication Date: September 28, 1993
    • Filing Date: October 20, 1989
    • Brief Description: This patent describes a resin circuit substrate and a method for its manufacture, where components are integrated within the resin substrate.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "baseboard" being a circuit board and "at least one component within the baseboard," as it describes components integrated into a resin substrate. The "hardened insulating polymer layer" could also be anticipated by the resin substrate.

11. US5250843A: Multichip integrated circuit modules

    • Full Citation: US5250843A
    • Publication Date: October 5, 1993
    • Filing Date: March 27, 1991
    • Brief Description: This patent describes multichip integrated circuit modules where multiple chips are packaged together.
    • Potential Anticipation (35 U.S.C. § 102): Similar to other multichip packaging references, this patent could anticipate the "at least one component within the baseboard" and the general concept of embedding multiple components within a module.

12. US5306670A: Multi-chip integrated circuit module and method for fabrication thereof

    • Full Citation: US5306670A
    • Publication Date: April 26, 1994
    • Filing Date: February 9, 1993
    • Brief Description: This patent describes a multi-chip integrated circuit module and its fabrication method, where chips are embedded within the module.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes both a multi-chip module and a method of fabrication that involves embedding chips, directly anticipating the "at least one component within the baseboard" and the overall electronic module structure of Claim 1.

13. US5353195A: Integral power and ground structure for multi-chip modules

    • Full Citation: US5353195A
    • Publication Date: October 4, 1994
    • Filing Date: July 9, 1993
    • Brief Description: This patent focuses on integral power and ground structures for multi-chip modules, which implies embedded or integrated chips.
    • Potential Anticipation (35 U.S.C. § 102): While focusing on power/ground, the underlying structure would inherently involve "at least one component within the baseboard" and "conductive patterns" on layers, making it relevant to Claim 1.

14. US5497033A: Embedded substrate for integrated circuit modules

    • Full Citation: US5497033A
    • Publication Date: March 5, 1996
    • Filing Date: February 8, 1993
    • Brief Description: This patent describes an embedded substrate specifically designed for integrated circuit modules.
    • Potential Anticipation (35 U.S.C. § 102): This reference is very closely aligned with the subject matter of Claim 1, directly discussing an "embedded substrate" for integrated circuit modules, which strongly anticipates the "baseboard," "at least one component within the baseboard," and potentially the "hardened insulating polymer layer" and "conductive patterns."

15. US5637919A: Perimeter independent precision locating member

    • Full Citation: US5637919A
    • Publication Date: June 10, 1997
    • Filing Date: July 28, 1993
    • Brief Description: This patent describes a precision locating member for components, which could be used in assembly processes.
    • Potential Anticipation (35 U.S.C. § 102): This reference primarily relates to alignment or assembly techniques, which are part of the method described in US8368201 but do not directly anticipate the structural features of Claim 1.

16. US5870289A: Chip connection structure having direct through-hole connections through adhesive film and wiring substrate

    • Full Citation: US5870289A
    • Publication Date: February 9, 1999
    • Filing Date: December 15, 1994
    • Brief Description: This patent describes a chip connection structure with direct through-hole connections through an adhesive film and a wiring substrate.
    • Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" and the general embedding of components, as it specifically mentions through-hole connections and an adhesive film (which could be a polymer layer) in conjunction with a wiring substrate.

17. US5943216A: Apparatus for providing a two-sided, cavity, inverted-mounted component circuit board

    • Full Citation: US5943216A
    • Publication Date: August 24, 1999
    • Filing Date: June 3, 1997
    • Brief Description: This patent describes an apparatus for a two-sided, cavity, inverted-mounted component circuit board.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "baseboard" and "at least one component within the baseboard" features, especially if the component is mounted in a cavity. The "inverted-mounted" aspect could relate to the component's first surface being against the polymer layer.

18. US5970321A: Method of fabricating a microelectronic package having polymer ESD protection

    • Full Citation: US5970321A
    • Publication Date: October 19, 1999
    • Filing Date: January 31, 1996
    • Brief Description: This patent describes a method of fabricating a microelectronic package with polymer ESD protection.
    • Potential Anticipation (35 U.S.C. § 102): This reference focuses on a microelectronic package and uses a polymer for ESD protection, which aligns with the "hardened insulating polymer layer" and "at least one component within the baseboard" of Claim 1.

19. US6015722A: Method for assembling an integrated circuit chip package having an underfill material between a chip and a substrate

    • Full Citation: US6015722A
    • Publication Date: January 18, 2000
    • Filing Date: October 14, 1997
    • Brief Description: This patent describes a method for assembling an integrated circuit chip package that includes an underfill material between a chip and a substrate.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the connection of components to a substrate, particularly the idea of an intermediate material (like an underfill) which could be analogous to the polymer layer in Claim 1, even if its primary purpose is different.

20. US6038133A: Circuit component built-in module and method for producing the same

    • Full Citation: US6038133A
    • Publication Date: March 14, 2000
    • Filing Date: November 25, 1997
    • Brief Description: This patent describes a circuit component built-in module and a method for producing it, where components are integrated into the module.
    • Potential Anticipation (35 U.S.C. § 102): This patent directly addresses the concept of a "built-in module" with integrated components, making it highly relevant to the entire structure of Claim 1, including the "baseboard," "at least one component within the baseboard," and the overall electronic module.

21. US6100108A: Method of fabricating electronic circuit device

    • Full Citation: US6100108A
    • Publication Date: August 8, 2000
    • Filing Date: February 17, 1997
    • Brief Description: This patent describes a method of fabricating an electronic circuit device.
    • Potential Anticipation (35 U.S.C. § 102): Without more specific details from the search result, it's hard to precisely pinpoint which claims are anticipated. However, a general method for fabricating an electronic circuit device could potentially encompass aspects of embedding components and forming connections, relevant to Claim 1.

22. US6131269A: Circuit isolation technique for RF and millimeter-wave modules

    • Full Citation: US6131269A
    • Publication Date: October 17, 2000
    • Filing Date: May 18, 1998
    • Brief Description: This patent describes a circuit isolation technique, likely involving shielding, which could relate to the electromagnetic protection mentioned in US8368201's description.
    • Potential Anticipation (35 U.S.C. § 102): While US8368201 describes electromagnetic protection in its detailed description, Claim 1 itself does not explicitly include shielding as a required element. Therefore, this reference is less likely to directly anticipate Claim 1.

23. JP2000311229A: IC card and manufacturing method thereof

    • Full Citation: JP2000311229A
    • Publication Date: November 7, 2000
    • Filing Date: April 27, 1999
    • Brief Description: This Japanese patent describes an IC card and its manufacturing method, where an IC chip is embedded.
    • Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant as it describes embedding an IC chip, which is a type of component, in an IC card, which could be considered a "base" similar to a circuit board. This could anticipate "at least one component within the baseboard" and the general module structure.

24. US6154366A: Structures and processes for fabricating moisture resistant chip-on-flex packages

    • Full Citation: US6154366A
    • Publication Date: November 28, 2000
    • Filing Date: November 23, 1999
    • Brief Description: This patent describes structures and processes for fabricating moisture-resistant chip-on-flex packages.
    • Potential Anticipation (35 U.S.C. § 102): This patent is relevant due to "chip-on-flex" packages, which involve a component (chip) on a flexible base, covered by a protective layer. This directly relates to the "at least one component within the baseboard" and "hardened insulating polymer layer" of Claim 1, especially considering the mention of flexible circuit boards in the US8368201 description.

25. JP2001053447A: Component built-in multilayer wiring board and method of manufacturing the same

    • Full Citation: JP2001053447A
    • Publication Date: February 23, 2001
    • Filing Date: August 5, 1999
    • Brief Description: This Japanese patent describes a component-built-in multilayer wiring board and its manufacturing method.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in multilayer wiring board," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1.

26. US6271469B1: Direct build-up layer on an encapsulated die package

    • Full Citation: US6271469B1
    • Publication Date: August 7, 2001
    • Filing Date: November 12, 1999
    • Brief Description: This patent describes a direct build-up layer on an encapsulated die package, indicating embedded or integrated components.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "at least one component within the baseboard" and the formation of layers, potentially anticipating the "hardened insulating polymer layer" and "conductive patterns" over encapsulated components.

27. US6284564B1: HDI chip attachment method for reduced processing

    • Full Citation: US6284564B1
    • Publication Date: September 4, 2001
    • Filing Date: September 20, 1999
    • Brief Description: This patent describes a High Density Interconnect (HDI) chip attachment method for reduced processing.
    • Potential Anticipation (35 U.S.C. § 102): This reference relates to chip attachment, which implies embedding or integrating a component, and the interconnects necessary for electrical contacts, making it relevant to the "at least one component within the baseboard" and "conductors within the hardened insulating polymer layer" aspects of Claim 1.

28. US6292366B1: Printed circuit board with embedded integrated circuit

    • Full Citation: US6292366B1
    • Publication Date: September 18, 2001
    • Filing Date: June 26, 2000
    • Brief Description: This patent describes a printed circuit board with an embedded integrated circuit.
    • Potential Anticipation (35 U.S.C. § 102): This is exceptionally relevant as it directly describes a "printed circuit board with embedded integrated circuit," essentially encompassing the core features of Claim 1: "baseboard" (PCB), "at least one component within the baseboard" (embedded IC), and the implied presence of "hardened insulating polymer layer" and "conductive patterns" in a PCB structure.

29. JP2001274034A: Electronic component package

    • Full Citation: JP2001274034A
    • Publication Date: October 5, 2001
    • Filing Date: January 20, 2000
    • Brief Description: This Japanese patent describes an electronic component package.
    • Potential Anticipation (35 U.S.C. § 102): General electronic component packages often involve embedding or encapsulating components, making this potentially relevant to the "at least one component within the baseboard" and "hardened insulating polymer layer" features of Claim 1.

30. US6324067B1: Printed wiring board and assembly of the same

    • Full Citation: US6324067B1
    • Publication Date: November 27, 2001
    • Filing Date: November 16, 1995
    • Brief Description: This patent describes a printed wiring board and its assembly.
    • Potential Anticipation (35 U.S.C. § 102): This reference, dealing with printed wiring boards, would implicitly cover the "baseboard" and "conductive patterns." If it describes components embedded within the board, it could anticipate other aspects of Claim 1.

31. JP2001345560A: Wiring board, and its manufacturing method, and electronic component

    • Full Citation: JP2001345560A
    • Publication Date: December 14, 2001
    • Filing Date: February 9, 2000
    • Brief Description: This Japanese patent describes a wiring board, its manufacturing method, and an electronic component.
    • Potential Anticipation (35 U.S.C. § 102): Similar to JP2001053447A and US6324067B1, this reference's focus on a "wiring board" and "electronic component" can be relevant to the "baseboard" and "at least one component within the baseboard" of Claim 1.

32. US20010054758A1: Three-dimensional memory stacking using anisotropic epoxy interconnections

    • Full Citation: US20010054758A1
    • Publication Date: December 27, 2001
    • Filing Date: June 21, 2000
    • Brief Description: This patent application describes three-dimensional memory stacking using anisotropic epoxy interconnections.
    • Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to the concept of stacking components and forming interconnections with an epoxy (polymer) material. It could anticipate "at least one component within the baseboard," "hardened insulating polymer layer," and "conductors within the hardened insulating polymer layer" in the context of a three-dimensional module.

33. JP2002016327A: Wiring board and method of manufacturing the same

    • Full Citation: JP2002016327A
    • Publication Date: January 18, 2002
    • Filing Date: April 24, 2000
    • Brief Description: This Japanese patent describes a wiring board and a method of manufacturing it.
    • Potential Anticipation (35 U.S.C. § 102): Similar to other wiring board patents, this would be relevant to the "baseboard" and "conductive patterns" of Claim 1. If it includes embedded components, it would be even more directly anticipatory.

34. US20020020898A1: Microelectronic substrates with integrated devices

    • Full Citation: US20020020898A1
    • Publication Date: February 21, 2002
    • Filing Date: August 16, 2000
    • Brief Description: This patent application describes microelectronic substrates with integrated devices.
    • Potential Anticipation (35 U.S.C. § 102): This reference is directly relevant to "microelectronic substrates" (baseboard) with "integrated devices" (components within the baseboard), making it highly anticipatory of Claim 1. The integration implies insulating layers and conductive patterns for connections.

35. US6350633B1: Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint

    • Full Citation: US6350633B1
    • Publication Date: February 26, 2002
    • Filing Date: August 22, 2000
    • Brief Description: This patent describes a semiconductor chip assembly with simultaneously electroplated contact terminals and connection joints.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" aspect of Claim 1, particularly concerning the formation of electrical contacts to a component.

36. US6396148B1: Electroless metal connection structures and methods

    • Full Citation: US6396148B1
    • Publication Date: May 28, 2002
    • Filing Date: February 10, 2000
    • Brief Description: This patent describes electroless metal connection structures and methods.
    • Potential Anticipation (35 U.S.C. § 102): This reference focuses on methods of forming conductive connections, which could be relevant to the "conductive patterns" and "conductors within the hardened insulating polymer layer" of Claim 1.

37. US20020063342A1: Pre-bond encapsulation of area array terminated chip and wafer scale packages

    • Full Citation: US20020063342A1
    • Publication Date: May 30, 2002
    • Filing Date: August 9, 1999
    • Brief Description: This patent application describes pre-bond encapsulation of chip and wafer scale packages.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to encapsulating components ("at least one component within the baseboard") using a material that could be a "hardened insulating polymer layer" as described in Claim 1.

38. JP2002158307A: Semiconductor device and manufacturing method thereof

    • Full Citation: JP2002158307A
    • Publication Date: May 31, 2002
    • Filing Date: November 22, 2000
    • Brief Description: This Japanese patent describes a semiconductor device and its manufacturing method.
    • Potential Anticipation (35 U.S.C. § 102): A general semiconductor device patent, depending on its specific details, could anticipate the "at least one component within the baseboard" and associated structures of Claim 1.

39. US20020117743A1: Component built-in module and method for producing the same

    • Full Citation: US20020117743A1
    • Publication Date: August 29, 2002
    • Filing Date: December 27, 2000
    • Brief Description: This patent application describes a component built-in module and a method for producing it.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1.

40. US20020127770A1: Die support structure

    • Full Citation: US20020127770A1
    • Publication Date: September 12, 2002
    • Filing Date: March 9, 2001
    • Brief Description: This patent application describes a die support structure.
    • Potential Anticipation (35 U.S.C. § 102): A die support structure would inherently be part of the "baseboard" and would support "at least one component within the baseboard," making it relevant to Claim 1.

41. US20020132096A1: Wiring board

    • Full Citation: US20020132096A1
    • Publication Date: September 19, 2002
    • Filing Date: December 25, 2000
    • Brief Description: This patent application describes a wiring board.
    • Potential Anticipation (35 U.S.C. § 102): Similar to other wiring board patents, this would be relevant to the "baseboard" and "conductive patterns" of Claim 1.

42. US6475877B1: Method for aligning die to interconnect metal on flex substrate

    • Full Citation: US6475877B1
    • Publication Date: November 5, 2002
    • Filing Date: December 22, 1999
    • Brief Description: This patent describes a method for aligning a die to interconnect metal on a flexible substrate.
    • Potential Anticipation (35 U.S.C. § 102): While this is a method patent, the underlying structure it describes would include a component (die) on a substrate (baseboard) with interconnects (conductive patterns and conductors), and a flexible substrate is mentioned as a possible embodiment in US8368201. This could be relevant to the structural features of Claim 1.

43. US6489685B2: Component built-in module and method of manufacturing the same

    • Full Citation: US6489685B2
    • Publication Date: December 3, 2002
    • Filing Date: January 19, 2001
    • Brief Description: This patent describes a component built-in module and a method of manufacturing it.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1.

44. US20020185303A1: Wiring circuit board and method for producing same

    • Full Citation: US20020185303A1
    • Publication Date: December 12, 2002
    • Filing Date: March 12, 2001
    • Brief Description: This patent application describes a wiring circuit board and a method for producing it.
    • Potential Anticipation (35 U.S.C. § 102): Similar to other wiring board patents, this would be relevant to the "baseboard" and "conductive patterns" of Claim 1.

45. US6495394B1: Chip package and method for manufacturing the same

    • Full Citation: US6495394B1
    • Publication Date: December 17, 2002
    • Filing Date: February 16, 1999
    • Brief Description: This patent describes a chip package and a method for manufacturing it.
    • Potential Anticipation (35 U.S.C. § 102): This reference directly describes a "chip package," which would inherently include a "component" (chip) and a surrounding structure, potentially anticipating the "hardened insulating polymer layer" and other aspects of Claim 1.

46. JP2003037205A: Multilayer substrate with built-in IC chip and method of manufacturing the same

    • Full Citation: JP2003037205A
    • Publication Date: February 7, 2003
    • Filing Date: July 23, 2001
    • Brief Description: This Japanese patent describes a multilayer substrate with a built-in IC chip and a method for manufacturing it.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "multilayer substrate with built-in IC chip," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

47. US6521530B2: Composite interposer and method for producing a composite interposer

    • Full Citation: US6521530B2
    • Publication Date: February 18, 2003
    • Filing Date: November 13, 1998
    • Brief Description: This patent describes a composite interposer and a method for producing it.
    • Potential Anticipation (35 U.S.C. § 102): An interposer serves as an intermediate connection layer, which would include "conductive patterns" and potentially insulating layers, relevant to Claim 1's features regarding electrical connections. Its publication date is after the priority date of US8368201, but its filing date is before.

48. US6537848B2: Super thin/super thermal ball grid array package

    • Full Citation: US6537848B2
    • Publication Date: March 25, 2003
    • Filing Date: May 30, 2001
    • Brief Description: This patent describes a super thin/super thermal ball grid array package.
    • Potential Anticipation (35 U.S.C. § 102): While focused on thermal management and thinness, this patent describes a package (electronic module) with a component (BGA), which implies embedded components and insulating layers, making it relevant to Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

49. US6538210B2: Circuit component built-in module, radio device having the same, and method for producing the same

    • Full Citation: US6538210B2
    • Publication Date: March 25, 2003
    • Filing Date: December 20, 1999
    • Brief Description: This patent describes a circuit component built-in module and a method for producing it.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "circuit component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

50. US20030068852A1: Protective film for the fabrication of direct build-up layers on an encapsulated die package

    • Full Citation: US20030068852A1
    • Publication Date: April 10, 2003
    • Filing Date: September 13, 2000
    • Brief Description: This patent application describes a protective film for the fabrication of direct build-up layers on an encapsulated die package.
    • Potential Anticipation (35 U.S.C. § 102): This reference directly discusses encapsulated die packages and protective films, aligning with the "at least one component within the baseboard" and "hardened insulating polymer layer" of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

51. US6562657B1: Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint

    • Full Citation: US6562657B1
    • Publication Date: May 13, 2003
    • Filing Date: August 22, 2000
    • Brief Description: This patent describes a semiconductor chip assembly with simultaneously electrolessly plated contact terminals and connection joints.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the "conductors within the hardened insulating polymer layer for forming electrical contacts" aspect of Claim 1, particularly concerning the formation of electrical contacts to a component. Its publication date is after the priority date of US8368201, but its filing date is before.

52. US20030090883A1: Component built-in module and method for producing the same

    • Full Citation: US20030090883A1
    • Publication Date: May 15, 2003
    • Filing Date: October 18, 2001
    • Brief Description: This patent application describes a component built-in module and a method for producing it.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

53. US20030100142A1: Semiconductor package and method for fabricating the same

    • Full Citation: US20030100142A1
    • Publication Date: May 29, 2003
    • Filing Date: May 7, 1999
    • Brief Description: This patent application describes a semiconductor package and a method for fabricating the same.
    • Potential Anticipation (35 U.S.C. § 102): This reference describes a semiconductor package, which would encompass a component (semiconductor) and a surrounding structure, potentially anticipating the "hardened insulating polymer layer" and other aspects of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

54. US20030137045A1: Circuit component built-in module and method of manufacturing the same

    • Full Citation: US20030137045A1
    • Publication Date: July 24, 2003
    • Filing Date: January 23, 2002
    • Brief Description: This patent application describes a circuit component built-in module and a method of manufacturing the same.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "circuit component built-in module," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date and filing date are after the priority date of US8368201.

55. US6607943B1: Low profile ball grid array package

    • Full Citation: US6607943B1
    • Publication Date: August 19, 2003
    • Filing Date: February 24, 1998
    • Brief Description: This patent describes a low profile ball grid array package.
    • Potential Anticipation (35 U.S.C. § 102): A BGA package is an electronic module containing a component. This would be relevant to the "at least one component within the baseboard" and the overall package structure of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

56. US6710458B2: Tape for chip on film and semiconductor therewith

    • Full Citation: US6710458B2
    • Publication Date: March 23, 2004
    • Filing Date: October 13, 2000
    • Brief Description: This patent describes a tape for chip-on-film applications and associated semiconductors.
    • Potential Anticipation (35 U.S.C. § 102): "Chip on film" technology involves a component on a flexible film, similar to the flexible circuit board mentioned in US8368201. This would be relevant to the "baseboard," "at least one component within the baseboard," and "hardened insulating polymer layer" of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

57. US6790712B2: Semiconductor device and method for fabricating the same

    • Full Citation: US6790712B2
    • Publication Date: September 14, 2004
    • Filing Date: March 21, 2001
    • Brief Description: This patent describes a semiconductor device and a method for fabricating the same.
    • Potential Anticipation (35 U.S.C. § 102): A general semiconductor device patent, depending on its specific details, could anticipate the "at least one component within the baseboard" and associated structures of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

58. US6979596B2: Method of fabricating a tape having apertures under a lead frame for conventional IC packages

    • Full Citation: US6979596B2
    • Publication Date: December 27, 2005
    • Filing Date: March 19, 1996
    • Brief Description: This patent describes a method of fabricating a tape with apertures under a lead frame for IC packages.
    • Potential Anticipation (35 U.S.C. § 102): This reference relates to IC packages and apertures, which could be relevant to the structural arrangement of components and electrical connections within a package, relevant to Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

59. US20050285244A1: Method of embedding semiconductor element in carrier and embedded structure thereof

    • Full Citation: US20050285244A1
    • Publication Date: December 29, 2005
    • Filing Date: June 29, 2004
    • Brief Description: This patent application describes a method of embedding a semiconductor element in a carrier and the resulting embedded structure.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes embedding a semiconductor element in a carrier (baseboard) and the resulting embedded structure. This directly anticipates many aspects of Claim 1, including the component within the baseboard and the overall structure. Its publication date and filing date are after the priority date of US8368201.

60. US20060105500A1: Process for fabricating chip embedded package structure

    • Full Citation: US20060105500A1
    • Publication Date: May 18, 2006
    • Filing Date: May 11, 2004
    • Brief Description: This patent application describes a process for fabricating a chip embedded package structure.
    • Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it describes a "chip embedded package structure," directly anticipating the "baseboard," "at least one component within the baseboard," and the overall electronic module structure of Claim 1. Its publication date and filing date are after the priority date of US8368201.

61. JP2002202025A: Injector integrated module

    • Full Citation: JP2002202025A
    • Publication Date: July 19, 2002
    • Filing Date: November 6, 2000
    • Brief Description: This Japanese patent describes an injector integrated module.
    • Potential Anticipation (35 U.S.C. § 102): This reference is relevant to the general concept of an "electronic module" containing integrated components, but more specific details would be needed to assess anticipation of particular elements of Claim 1. Its publication date is after the priority date of US8368201, but its filing date is before.

62. RU2001132099A: METHOD FOR PRODUCING MICROPLATES

    • Full Citation: RU2001132099A
    • Publication Date: July 20, 2003
    • Filing Date: November 29, 2001
    • Brief Description: This Russian patent describes a method for producing microplates.
    • Potential Anticipation (35 U.S.C. § 102): Without more specific details about the microplates, it's difficult to assess direct anticipation. However, "microplates" could be considered a type of base or substrate for electronic components. Its publication date and filing date are after the priority date of US8368201.

Summary of Most Relevant Prior Art for Claim 1 (by filing/priority date before US8368201's priority date of 2002-01-31):

Based on the analysis, several references stand out as highly relevant for potentially anticipating Claim 1 of US8368201 due to their clear descriptions of embedding components within a base or substrate, forming insulating layers, and creating electrical connections. The most notable among these are:

• US6292366B1 (Filing Date: June 26, 2000): Printed circuit board with embedded integrated circuit. This patent directly describes a "printed circuit board with embedded integrated circuit," which aligns almost entirely with the core elements of Claim 1.
• JP2001053447A (Filing Date: August 5, 1999): Component built-in multilayer wiring board and method of manufacturing the same. This also directly describes a "component built-in multilayer wiring board," strongly anticipating the elements of Claim 1.
• US5497033A (Filing Date: February 8, 1993): Embedded substrate for integrated circuit modules. This patent is highly relevant due to its focus on an "embedded substrate for integrated circuit modules."
• US5306670A (Filing Date: February 9, 1993): Multi-chip integrated circuit module and method for fabrication thereof. This patent describes a multi-chip module with embedded chips.
• US20010054758A1 (Filing Date: June 21, 2000): Three-dimensional memory stacking using anisotropic epoxy interconnections. This reference highlights component stacking and epoxy (polymer) interconnections, anticipating multiple aspects of Claim 1 in a 3D context.
• US6038133A (Filing Date: November 25, 1997): Circuit component built-in module and method for producing the same. This directly addresses the concept of a "built-in module" with integrated components.
• US20020020898A1 (Filing Date: August 16, 2000): Microelectronic substrates with integrated devices. This describes microelectronic substrates with integrated devices.
• US5870289A (Filing Date: December 15, 1994): Chip connection structure having direct through-hole connections through adhesive film and wiring substrate. This is very relevant to the interconnection elements within the polymer layer.

These patents and applications, filed or published before the priority date of US8368201, disclose similar structural arrangements involving embedded components, insulating layers, and conductive patterns, which are the fundamental features of Claim 1.

To analyze the obviousness of US patent 8368201 under 35 U.S.C. § 103, we will consider the claims of the patent and relevant prior art references. The authoritative priority date for US8368201 is January 31, 2002.

Independent Claim 1 of US8368201 defines an electronic module comprising:

1. A baseboard having a first surface and a second surface;
2. A hardened insulating polymer layer on the second surface of the baseboard;
3. At least one component within the baseboard, the component having contact areas on a first surface of the component, said first surface of the component being against the hardened insulating polymer layer;
4. Conductive patterns on the hardened insulating polymer layer; and
5. Conductors within the hardened insulating polymer layer for forming electrical contacts between at least some of the conductive patterns and at least some of the contact areas of the component.

The following prior art references, published before the priority date of US8368201, are particularly relevant for an obviousness analysis:

• US5870289A (Hitachi, Ltd.) published on February 9, 1999, titled "Chip connection structure having direct through-hole connections through adhesive film and wiring substrate".
• US6292366B1 (Intel Corporation) published on September 18, 2001, titled "Printed circuit board with embedded integrated circuit".

Obviousness Analysis: Combination of US5870289A and US6292366B1

A person having ordinary skill in the art (POSA) in circuit board manufacturing, at the time of the invention of US8368201 (i.e., before January 31, 2002), would have been motivated to combine the teachings of US5870289A and US6292366B1 to arrive at the subject matter of Claim 1 of US8368201.

Motivation for Combination:
US5870289A specifically discloses a method and structure for embedding an IC chip in a wiring substrate and making through-hole connections through an adhesive film. This reference provides a detailed approach to physically integrating a component into a base and establishing initial electrical connections. US6292366B1, on the other hand, describes a printed circuit board with an embedded integrated circuit, and more broadly teaches that an embedded IC package is completed by forming "a series of dielectric layers, via holes, and metal layers using conventional PCB fabrication techniques." A POSA, seeking to create a fully functional electronic module with an embedded component, would naturally look to combine the specific embedding and initial connection techniques of US5870289A with the general, well-known build-up processes for forming complete circuit board packages, as taught by US6292366B1. The motivation would be to utilize the advantages of embedded components while ensuring comprehensive electrical connectivity and package completion.

Analysis of Claim Elements:

1. A baseboard having a first surface and a second surface:

   • US5870289A teaches a "wiring substrate 1" with a recess 2 for mounting an IC chip. Any such substrate inherently has distinct surfaces. This element would be obvious to a POSA.

2. A hardened insulating polymer layer on the second surface of the baseboard:

   • US5870289A discloses an "adhesive film 4" used to mount the IC chip 3 in the recess 2 of the wiring substrate 1. The electrodes 3a of the IC chip are positioned against this film. This adhesive film, upon curing (a standard process for adhesives), would become a hardened insulating polymer layer. When a component is inserted into a through-hole in a baseboard, the film at the bottom of that hole, against which the component sits, can be considered as being "on the second surface" in the context of the overall board structure.

3. At least one component within the baseboard, the component having contact areas on a first surface of the component, said first surface of the component being against the hardened insulating polymer layer:

   • US5870289A explicitly shows an "IC chip 3" mounted in a "recess 2" of a "wiring substrate 1". The IC chip has "electrodes 3a" (contact areas) which are positioned against the "adhesive film 4". This directly teaches a component within the baseboard, with its contact areas on a first surface being against the hardened insulating polymer layer.

4. Conductive patterns on the hardened insulating polymer layer:

   • US5870289A shows "wiring patterns 5" formed on the wiring substrate 1. While these patterns are shown on the main substrate surface and not explicitly directly on the surface of the adhesive film 4 in all illustrations, US6292366B1 teaches that an embedded IC package is completed by forming "metal layers" (i.e., conductive patterns) on "dielectric layers" (i.e., insulating polymer layers) using conventional PCB fabrication techniques. A POSA would understand that to complete the module and connect to the embedded component, conductive patterns would need to be formed on or in electrical communication with the insulating polymer layer (adhesive film 4 of US5870289A) or subsequent dielectric layers built upon it. Combining these teachings would lead a POSA to form conductive patterns on the hardened insulating polymer layer to create a functional module.

5. Conductors within the hardened insulating polymer layer for forming electrical contacts between at least some of the conductive patterns and at least some of the contact areas of the component:

   • US5870289A clearly teaches "Through-holes 6" formed in the "adhesive film 4" and the "wiring substrate 1" at positions corresponding to the "electrodes 3a" of the IC chip 3. These through-holes 6 are then filled with "conductive material 7", which connects the chip's electrodes 3a to the "wiring patterns 5" on the substrate. These filled through-holes (conductive material 7) directly constitute the "conductors within the hardened insulating polymer layer" for forming electrical contacts between the conductive patterns and the component's contact areas.

Therefore, the combination of US5870289A and US6292366B1 would have rendered Claim 1 of US8368201 obvious to a person having ordinary skill in the art at the time of the invention.

For US Patent 8368201, a detailed analysis of its patent term, related applications, and expiration date is provided below, based on the authoritative patent text and general patent law principles. Specific Patent Term Adjustment (PTA) and Patent Term Extension (PTE) amounts are not directly calculable from the provided search snippets, but the projected expiration date aligns with the patent's earliest priority claims.

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) is additional time added to the term of a patent to compensate for certain administrative delays by the United States Patent and Trademark Office (USPTO) during the patent prosecution process. While the exact number of PTA days for US8368201 is not explicitly stated in the provided text or readily available through the current search capabilities, the "Anticipated expiration" date listed as 2023-01-28 suggests that any PTA, if granted, was either factored into this date or was negligible, aligning closely with the 20-year term from its earliest effective filing date.

Patent Term Extensions (PTE)

Patent Term Extension (PTE) is available for patents claiming products (e.g., human drugs, food additives, medical devices) that require regulatory approval prior to commercial sale, aiming to restore patent term lost during the regulatory review period. Given that US8368201 is titled "Method for embedding a component in a base" and describes a manufacturing process for electronic modules, it does not fall within the categories typically eligible for PTE. Therefore, it is highly unlikely that this patent received any PTE.

Continuation Applications

US8368201 is identified as a continuation application. The patent text explicitly states:

• This application (US13/185,165, which matured into US8368201B2) is a Continuation of application Ser. No. 11/878,557, filed on Jul. 25, 2007 (which issued as U.S. Pat. No. 7,989,944).
• Application Ser. No. 11/878,557 is a continuation of application Ser. No. 10/502,336, filed on Sep. 23, 2004 (which issued as U.S. Pat. No. 7,294,529).

Divisional Applications

The provided patent text does not explicitly mention any divisional applications for US8368201. Divisional applications are a type of continuing application that allows an applicant to pursue claims to a different invention disclosed in an earlier filed application.

Related Family Members

The patent belongs to a family of related applications, all sharing the same priority date. The family includes the following US applications, as listed in the "Family Applications" section of the provided patent data:

• US10/502,336 (US7294529B2)
  • Priority Date: 2002-01-31
  • Filing Date: 2003-01-28
• US11/797,609 (US7732909B2)
  • Priority Date: 2002-01-31
  • Filing Date: 2007-05-04
• US11/878,557 (US7989944B2)
  • Priority Date: 2002-01-31
  • Filing Date: 2007-07-25
• US13/185,165 (US8368201B2 - the subject patent)
  • Priority Date: 2002-01-31
  • Filing Date: 2011-07-18

The earliest priority claim for this patent family is traced back to an international application, PCT/F103/00065, with a priority date of January 31, 2002, and a filing date of January 28, 2003.

Projected Expiration Date

For utility patents filed on or after June 8, 1995, the patent term generally expires 20 years from the earliest filing date of the application, or of an earlier application to which it claims priority under 35 U.S.C. §§ 120, 121, or 365(c). In the case of US8368201, the earliest effective filing date from which the 20-year term is measured is the filing date of the PCT/F103/00065 application, which is January 28, 2003.

Therefore, the calculated statutory expiration date, prior to any adjustments, would be January 28, 2023.

The Google Patents listing for US8368201 shows "Anticipated expiration 2023-01-28" and a "Legal status (The legal status is an assumption and is not a legal conclusion...): Expired - Fee Related". This precisely matches the 20-year term from the earliest effective filing date, indicating that the patent term concluded on this date. The "Expired - Fee Related" status suggests that the patent lapsed due to failure to pay maintenance fees rather than reaching its full statutory term naturally, though the expiration date itself aligns with the statutory calculation.

The USPTO search confirms the patent number 8368201. The patent information from the prompt is consistent with typical USPTO records.

Now, proceeding with the "Defensive Disclosure" document.

---

Defensive Disclosure for US Patent 8368201: Method for embedding a component in a base

Date: April 26, 2026

Patent Under Analysis: US 8368201 B2, "Method for embedding a component in a base"

Objective: To expand the public domain of prior art related to embedded component technology, thereby rendering future incremental improvements by competitors as obvious or non-novel in the context of US Patent 8368201. This document details derivative variations of the electronic module described in independent claim 1 of US 8368201, covering material/component substitutions, operational parameter expansions, cross-domain applications, integration with emerging technologies, and inverse/failure modes.

Derivative Variations of the Electronic Module

1. Material & Component Substitution

Enabling Description: The electronic module as described in claim 1 is herein disclosed with a ceramic (e.g., Alumina, Aluminum Nitride) baseboard to enhance thermal conductivity and mechanical rigidity. The hardened insulating polymer layer is substituted with a high-performance polyimide film (e.g., Kapton® HN) applied via spin-coating and subsequently cured, offering superior dielectric strength and temperature resistance. The at least one component embedded within the baseboard comprises a micro-electromechanical system (MEMS) device, such as an accelerometer or gyroscope, instead of a standard microcircuit. The contact areas on the first surface of the MEMS component are fabricated with gold (Au) bumps via electroplating. The conductive patterns on the hardened insulating polyimide layer are formed from a nickel-palladium-gold (NiPdAu) stack, patterned by subtractive etching. The conductors within the hardened insulating polyimide layer for forming electrical contacts between the conductive patterns and the MEMS component contact areas are realized as copper (Cu) pillars grown via through-hole plating, subsequently filled with a conductive epoxy for mechanical reinforcement.

graph TD
    A[Select Ceramic Baseboard (Alumina/AlN)] --> B[Spin-coat Polyimide Film (Kapton HN)]
    B --> C{Cure Polyimide Film}
    C --> D[Embed MEMS Component (Accelerometer/Gyroscope)]
    D --> E[MEMS Component with Au Bumps on First Surface]
    E --> F[Pattern NiPdAu Conductive Layer on Polyimide]
    F --> G[Grow Cu Pillars for Interconnects]
    G --> H[Fill Cu Pillars with Conductive Epoxy]
    H --> I[Finished Electronic Module]

2. Operational Parameter Expansion - Nanoscale Integration

Enabling Description: An electronic module integrating components at the nanoscale. The baseboard is a self-assembling polymer-nanocomposite matrix (e.g., polystyrene-block-poly(methyl methacrylate) copolymer with embedded carbon nanotubes) approximately 500 nm thick. The hardened insulating polymer layer consists of an atomic layer deposition (ALD) grown hafnium dioxide (HfO₂) or aluminum oxide (Al₂O₃) layer, approximately 5 nm thick, providing ultra-thin, high-k dielectric insulation. The embedded component is a quantum dot (QD) based sensor array (e.g., for light detection), with individual quantum dots having dimensions less than 10 nm, configured with contact areas comprising graphene nanoribbon pads. These quantum dot components are directly integrated "within" the polymer-nanocomposite matrix. Conductive patterns on the HfO₂/Al₂O₃ layer are formed by directed self-assembly of metallic nanoparticles (e.g., Au or Ag nanoparticles) or electron beam lithography of platinum (Pt) lines, with feature sizes below 50 nm. Conductors within the ALD dielectric layer are vertically aligned carbon nanotubes (CNTs) or atomic-scale metallic nanowires (e.g., copper nanowires), acting as through-insulator vias (TIVs) to establish electrical contacts between the conductive patterns and the graphene nanoribbon contact areas of the quantum dot components. This fabrication requires precision at the picometer scale for alignment.

classDiagram
    class ElectronicModule {
        -PolymerNanocompositeMatrix baseboard
        -ALD_Dielectric insulatingLayer
        -QuantumDotArray embeddedComponent
        -GrapheneNanoribbon contactAreas
        -MetallicNanoparticlePattern conductivePatterns
        -CarbonNanotubeVias conductors
    }
    class PolymerNanocompositeMatrix {
        +SelfAssembly()
        +EmbedCNTs()
    }
    class ALD_Dielectric {
        +HFO2_Layer()
        +AL2O3_Layer()
    }
    class QuantumDotArray {
        +SensorFunctionality()
        +GrapheneNanoribbonPads()
    }
    class MetallicNanoparticlePattern {
        +DirectedSelfAssembly()
        +EBL_PtLines()
    }
    class CarbonNanotubeVias {
        +VerticalAlignment()
        +AtomicScaleNanowires()
    }
    ElectronicModule *-- PolymerNanocompositeMatrix
    ElectronicModule *-- ALD_Dielectric
    ElectronicModule *-- QuantumDotArray
    QuantumDotArray *-- GrapheneNanoribbon
    ElectronicModule *-- MetallicNanoparticlePattern
    ElectronicModule *-- CarbonNanotubeVias

3. Operational Parameter Expansion - High Temperature/Pressure Environments

Enabling Description: An electronic module designed for extreme operational environments (e.g., downhole oil/gas exploration, aerospace engine control) capable of sustained operation at temperatures up to 300°C and pressures up to 200 MPa (approx. 2000 atmospheres). The baseboard is constructed from a silicon carbide (SiC) or aluminum nitride (AlN) ceramic substrate, chosen for its high thermal stability and mechanical strength. The hardened insulating layer is a high-temperature polybenzimidazole (PBI) polymer film, or a thin layer of boron nitride (BN) deposited via chemical vapor deposition (CVD), specifically engineered to maintain insulating properties and structural integrity under extreme heat and pressure. The embedded component consists of wide bandgap (WBG) semiconductors (e.g., SiC MOSFETs, GaN HEMTs) configured with high-temperature metallization (e.g., tungsten, platinum, nickel silicide) for their contact areas. Conductive patterns on the PBI/BN layer are formed using refractory metals (e.g., molybdenum, tantalum) patterned by laser ablation, ensuring thermal and chemical stability. Conductors within the insulating layer are high-aspect-ratio through-silicon vias (TSVs) filled with tungsten or an intermetallic compound like Cu/Sn-Ag, providing robust electrical contacts that withstand thermal cycling and high pressures, minimizing delamination and electromigration effects.

stateDiagram-v2
    State_Init: Module Assembly
    State_Init --> State_LowTempPressure: Initial Deployment
    State_LowTempPressure --> State_HighTempPressure: Operational Mode
    State_HighTempPressure --> State_HighTempPressure: Sustained Operation (300C, 200MPa)
    State_HighTempPressure --> State_Cooling: Deactivation/Cooling
    State_HighTempPressure --> State_CriticalFailure: Over-limit Excursion
    State_Cooling --> State_Storage: Return to Ambient
    State_CriticalFailure --> State_Shutdown: Safe Shutdown
    State_HighTempPressure -- (monitor > 300C or > 200MPa) --> State_OverLimitWarning
    State_OverLimitWarning --> State_CriticalFailure

4. Cross-Domain Application - Automotive Engine Control Units (ECUs)

Enabling Description: An electronic module specifically adapted for use as an Engine Control Unit (ECU) in automotive applications, emphasizing robustness against vibration, temperature extremes, and electromagnetic interference (EMI). The baseboard is a high-Tg epoxy resin composite (e.g., FR-4 variant with ceramic fillers or a polyimide-based laminate) for enhanced thermal and mechanical stability, approximately 1.5 mm thick. The hardened insulating polymer layer is a flexible, high-temperature polyimide film (e.g., DuPont™ Pyralux® AP) with integrated damping characteristics to mitigate vibrational stress, laminated onto the baseboard. Embedded components include automotive-grade microcontrollers (e.g., Infineon AURIX™ family), power management ICs, and sensor interface ASICs. These components feature robust, lead-free solder ball grid arrays (BGAs) or copper pillar bumps as contact areas. Conductive patterns on the insulating layer are formed from thick copper traces (e.g., 70 µm) for high current carrying capability and EMI shielding. Furthermore, as explicitly mentioned in US8368201 (FIG. 4), integrated ground planes and Faraday cages (using copper foil plating on cavity sidewalls and above/below components) are incorporated around the embedded components within the baseboard structure to provide electromagnetic protection, connecting to the main ground plane of the ECU. Conductors within the insulating layer are formed by laser-drilled and copper-filled microvias.

graph TD
    A[Automotive Baseboard (High-Tg Epoxy/Polyimide)] --> B{Embed Automotive Microcontroller (e.g., AURIX)}
    B --> C{Embed Power Management ICs/Sensors}
    C --> D[Laminate Flexible Polyimide Insulating Layer with Damping]
    D --> E[Components' BGA/Copper Pillars Against Insulating Layer]
    E --> F[Pattern Thick Copper Traces on Insulating Layer]
    F --> G[Integrate EMI Shielding / Ground Planes (per FIG. 4)]
    G --> H[Form Laser-Drilled, Copper-Filled Microvias]
    H --> I[Finished Automotive ECU Module]

5. Cross-Domain Application - Medical Implants (Neuromodulation)

Enabling Description: An electronic module designed for chronic medical implantation, such as a neuromodulation device (e.g., for deep brain stimulation or spinal cord stimulation), requiring stringent biocompatibility, miniaturization, and long-term reliability. The baseboard is a thin (e.g., 100-200 µm) medical-grade titanium alloy (Ti-6Al-4V) or a specialized ceramic (e.g., Al₂O₃ or ZrO₂) for mechanical support and hermeticity. The hardened insulating polymer layer is a biocompatible Parylene C (poly-para-xylylene) film, deposited conformally via chemical vapor deposition (CVD) to a thickness of 5-10 µm, offering excellent moisture barrier properties and chemical inertness. Embedded components are ultra-low-power neuromodulation micro-chips (e.g., ASICs for signal processing and stimulation), with contact areas comprising platinum-iridium (PtIr) pads for biocompatibility and electrical stability. Conductive patterns on the Parylene C layer are thin-film platinum (Pt) or gold (Au), patterned using photolithography and lift-off techniques to minimize surface roughness and potential for biological interaction. Conductors within the Parylene C layer are formed by laser ablation of microvias and subsequent PtIr or Au metallization, creating direct, robust electrical connections between the PtIr/Au pads of the neuromodulation micro-chips and the thin-film Pt/Au conductive patterns. The entire module is hermetically sealed within a biocompatible encapsulation.

classDiagram
    class MedicalImplantModule {
        -TitaniumAlloy/Ceramic baseboard
        -ParyleneC_Film insulatingLayer
        -NeuromodulationMicrochip embeddedComponent
        -PlatinumIridium contactAreas
        -ThinFilmPt/Au conductivePatterns
        -LaserAblatedPtIr/AuVias conductors
        +BiocompatibleEncapsulation
    }
    class TitaniumAlloy {
        +MedicalGrade()
        +HighStrength()
    }
    class ParyleneC_Film {
        +CVD_Deposition()
        +MoistureBarrier()
    }
    class NeuromodulationMicrochip {
        +UltraLowPower()
        +ASIC_Functionality()
    }
    MedicalImplantModule *-- TitaniumAlloy
    MedicalImplantModule *-- ParyleneC_Film
    MedicalImplantModule *-- NeuromodulationMicrochip
    MedicalImplantModule *-- PlatinumIridium
    MedicalImplantModule *-- ThinFilmPt/Au
    MedicalImplantModule *-- LaserAblatedPtIr/AuVias

6. Cross-Domain Application - Renewable Energy (Smart Grid Sensors)

Enabling Description: An electronic module tailored for deployment as a smart sensor node within harsh outdoor environments of renewable energy infrastructure (e.g., solar farms, wind turbines), demanding extreme longevity, wide operating temperature range, and resistance to environmental degradation. The baseboard is a high-strength, UV-stabilized composite material, such as a fiberglass-reinforced polymer (FRP) or a specialized weatherproof FR-4 laminate, providing structural integrity against mechanical stress and environmental exposure. The hardened insulating polymer layer is a robust fluoropolymer (e.g., PTFE or FEP), chosen for its excellent chemical inertness, UV resistance, and wide operating temperature range (-60°C to +200°C), applied via lamination or spray coating. Embedded components are ultra-low-power sensor microcircuits (e.g., for voltage, current, temperature, vibration monitoring), energy harvesting PMICs, and wireless transceivers. These components feature environmentally hardened contact areas, such as robust copper-nickel-gold pads. Conductive patterns on the fluoropolymer layer are thick film silver (Ag) or copper (Cu) traces with an anti-corrosion overcoat, formed by screen printing or conventional etching. Conductors within the fluoropolymer layer are filled with a UV-stable conductive epoxy or specialized weather-resistant plated vias, establishing durable electrical connections. The module includes an integrated inductive power transfer coil for maintenance-free power delivery and a robust, sealed enclosure.

graph LR
    A[Baseboard: FRP/Weatherproof FR-4] --> B(Insulating Layer: Fluoropolymer (PTFE/FEP))
    B --> C[Embed Components: Ultra-Low-Power Sensors, PMICs, Transceivers]
    C --> D(Component Contact Areas: CuNiAu Pads)
    D --> E[Conductive Patterns: Thick Film Ag/Cu + Overcoat]
    E --> F[Conductors: UV-Stable Conductive Epoxy/Plated Vias]
    F --> G(Integrated Inductive Power Transfer Coil)
    G --> H[Robust Sealed Enclosure]
    H --> I[Smart Grid Sensor Module]

7. Integration with Emerging Tech - AI-driven Manufacturing Optimization

Enabling Description: The manufacturing process for the electronic module, as described, is enhanced through an AI-driven optimization system. An electronic module with embedded components is produced using a baseboard (e.g., FR4), an insulating polymer layer (e.g., pre-preg), embedded microcircuits, conductive patterns, and through-layer conductors. During each critical manufacturing step (e.g., polymer film lamination, component placement, curing, metallization), real-time sensor data (temperature, pressure, alignment accuracy from machine vision, chemical bath composition, viscosity of filler material) is collected and fed to a central AI agent. This AI agent, based on a reinforcement learning or predictive control algorithm, dynamically adjusts operational parameters (e.g., laminator speed and temperature, component placement force and alignment offsets, curing time and temperature profiles, electrochemical deposition parameters) to maximize yield, minimize defects, and optimize electrical performance of the embedded components. For instance, the AI analyzes variations in baseboard flatness and adjusts component insertion depth to ensure optimal contact with the polymer film, or modifies curing profiles based on real-time epoxy polymerization rates. The AI system learns from historical manufacturing data and real-time feedback loops to continuously improve the embedding process, making it adaptive and self-optimizing.

sequenceDiagram
    participant MCS as Manufacturing Control System
    participant Sensors
    participant AI as AI Optimization Agent
    participant ManufacturingTools as Manufacturing Tools (Laminator, Pick&Place, Oven, Plater)

    loop Manufacturing Cycle
        MCS->>ManufacturingTools: Initiate Stage (e.g., Lamination)
        ManufacturingTools->>Sensors: Collect Real-time Data (Temp, Pressure, Viscosity, Alignment)
        Sensors->>AI: Send Real-time Data
        AI->>AI: Analyze Data & Predict Outcomes (Yield, Defects, Performance)
        AI->>AI: Determine Optimal Parameter Adjustments
        AI->>ManufacturingTools: Send Optimized Parameters (e.g., Laminator Speed, Temp)
        ManufacturingTools->>MCS: Report Stage Completion
    end
    AI->>AI: Update Model based on Final Product Quality

8. Integration with Emerging Tech - IoT Sensors for Real-time Monitoring

Enabling Description: An electronic module where the embedded components themselves, or additional micro-sensors integrated within the baseboard and hardened insulating polymer layer, are equipped for real-time monitoring of the module's operational health and environmental conditions. This module comprises a standard FR4 baseboard, a cured epoxy insulating layer, and embedded microcircuits. Additionally, miniature MEMS temperature sensors, strain gauges, and impedance monitoring points are embedded adjacent to critical components and interconnects within the polymer layer. These embedded sensors are connected via dedicated conductors within the hardened insulating polymer layer to a low-power wireless transceiver micro-chip, also embedded within the module. This transceiver continuously collects sensor data (e.g., component temperature, localized strain, interconnect resistance changes) and transmits it via a low-energy wireless protocol (e.g., Bluetooth Low Energy (BLE) or Thread) to a nearby Internet of Things (IoT) gateway. The IoT gateway then relays this data to a cloud-based analytics platform for predictive maintenance, anomaly detection, and long-term performance tracking. This enables continuous, non-invasive health monitoring of the embedded components throughout the module's lifecycle.

graph TD
    A[Electronic Module] --> B{Embedded Components (Microcircuits)}
    A --> C{Embedded IoT Micro-Sensors (Temp, Strain, Impedance)}
    C --> D[Low-Power Wireless Transceiver (Embedded)]
    D -- BLE/Thread --> E(IoT Gateway)
    E -- Internet --> F(Cloud Analytics Platform)
    F --> G{Predictive Maintenance Alerts}
    F --> H{Performance Analytics}

9. The "Inverse" or Failure Mode - Graceful Degradation / Low-Power Mode

Enabling Description: An electronic module designed with an inherent "graceful degradation" capability, allowing for continued, albeit limited, operation upon detection of a primary component failure or a critical power event. The module consists of a multi-layer baseboard with redundant, embedded microcontrollers (e.g., a primary high-performance core and a secondary low-power core) within different sections of the baseboard, separated by hardened insulating polymer layers. Each microcontroller has its dedicated power plane and a set of critical contact areas. A dedicated Power Management Unit (PMU), also embedded, continuously monitors the health (e.g., voltage, current draw, clock integrity) of the primary components. Upon detection of a failure in the primary microcontroller or a significant drop in the module's power supply (e.g., battery low), the PMU automatically switches control from the primary core to the secondary low-power core. This secondary core activates a limited-functionality mode, enabling essential operations (e.g., critical data logging, emergency communication, safety shutdown procedures) while deactivating non-essential peripherals to conserve power. The conductors within the insulating layer are designed with redundant paths, allowing the PMU to re-route power and data signals to the operational core.

stateDiagram-v2
    state PrimaryOperational <<start>>
    state LowPowerMode

    PrimaryOperational --> PrimaryFailureDetected: Primary component fails
    PrimaryOperational --> LowBatteryDetected: Power supply critically low

    PrimaryFailureDetected --> TransitionToLowPowerMode: PMU re-routes control
    LowBatteryDetected --> TransitionToLowPowerMode: PMU re-routes control

    TransitionToLowPowerMode --> LowPowerMode: Secondary core activated

    LowPowerMode --> CriticalDataLogging: Essential operation
    LowPowerMode --> EmergencyCommunication: Essential operation
    LowPowerMode --> SafeShutdownProcedure: Essential operation
    LowPowerMode --> PrimaryOperational: Primary system restored (if possible)

10. The "Inverse" or Failure Mode - Environmentally Responsive Disassembly

Enabling Description: An electronic module engineered for environmentally responsive disassembly or degradation at the end of its useful life, addressing e-waste and material recovery. The baseboard is constructed from a biodegradable polymer composite (e.g., polylactic acid (PLA) reinforced with natural fibers). The hardened insulating polymer layer is a thermo-responsive or water-soluble polymer (e.g., polyvinyl alcohol (PVA) or a specific self-dissolving epoxy), designed to lose its adhesive and insulating properties under specific environmental triggers (e.g., elevated temperature (e.g., >80°C) or immersion in water/solvent). Embedded components are standard microcircuits, but their contact areas and the conductive patterns on the insulating layer are made from easily separable or recyclable metals (e.g., pure copper or aluminum). The conductors within the insulating layer are also designed for easy recovery (e.g., solid copper vias). Upon intentional immersion in a hot water bath or a specific solvent at end-of-life, the thermo-responsive/water-soluble polymer layer degrades or dissolves, allowing for clean separation of the baseboard, embedded components, and conductive materials. This facilitates automated sorting and recycling of the constituent materials, minimizing hazardous waste and maximizing resource recovery.

graph TD
    A[Electronic Module] --> B{Baseboard: Biodegradable Polymer (PLA)}
    B --> C{Insulating Layer: Thermo-Responsive/Water-Soluble Polymer (PVA/Self-Dissolving Epoxy)}
    C --> D{Embedded Components: Standard Microcircuits}
    D --> E{Contact Areas/Conductive Patterns: Easily Separable Metals (Cu/Al)}
    E --> F{Conductors: Solid Copper Vias}
    F --> G(Trigger End-of-Life: Heat/Water/Solvent Immersion)
    G --> H[Polymer Degrades/Dissolves]
    H --> I[Separation of Materials: Baseboard, Components, Conductors]
    I --> J[Facilitated Recycling/Degradation]

Combination Prior Art Scenarios

These scenarios combine the teachings of US 8368201 with existing open-source standards, thereby expanding the prior art landscape.

1. US 8368201 with IPC-A-610 and IPC-7351 Standards for Embedded Components:

   • Description: The method and resulting electronic module of US 8368201, which describes embedding components within a baseboard and forming electrical contacts, are considered in the context of widely accepted industry standards for electronic assembly. Specifically, the principles of ensuring proper alignment of components and reliable electrical contacts, as detailed in US 8368201 (e.g., aligning component holes relative to conductive patterns in stage E and G, using contact protrusions 9 for connection in FIG. 3), are combined with the "Acceptability of Electronic Assemblies" (IPC-A-610) criteria for embedded components and the "Generic Requirements for Surface Mount Design and Land Pattern Standard" (IPC-7351). This combination establishes that the fabrication of conductive patterns and component placement for embedded chips, where components are pressed against a polymer film, must meet specific quality and reliability standards, making any future incremental improvement in manufacturing tolerances or connection integrity for such embedded modules an obvious design choice for a skilled artisan seeking to comply with IPC standards. This extends to visual inspection criteria (IPC-A-610) for microvias and embedded pad structures, and land pattern design considerations (IPC-7351) for the component contact areas and conductive patterns on the insulating layer.

2. US 8368201 with RISC-V Open Standard Architecture:

   • Description: The methodology of US 8368201 for embedding microcircuits within a base is applied specifically to integrate open-source RISC-V processor cores. An electronic module is constructed wherein the "at least one component within the baseboard" (claim 1) is a bare die RISC-V microcontroller (e.g., a commercial implementation of the RV32I or RV64GC instruction set architecture). The baseboard, hardened insulating polymer layer, conductive patterns, and conductors are manufactured according to the techniques described in US 8368201 (e.g., using FR4, RCC foil, copper metallization as in FIG. 1). The design of the RISC-V chip's contact areas and the corresponding conductive patterns on the polymer layer are made in accordance with the open specifications for the RISC-V processor interface, utilizing standard flip-chip or copper pillar bump geometries. This explicitly discloses embedding an open-source, configurable processor architecture directly into a circuit board structure via the described method, making any future embedding of other open-source IP cores or variations of RISC-V chips using similar methods obvious to one skilled in the art.

3. US 8368201 with Open-Source Hardware Initiatives (e.g., Arduino/Raspberry Pi Design Principles):

   • Description: The electronic module and embedding methodology of US 8368201 are utilized to create a highly compact, ruggedized version of an open-source hardware platform, such as an Arduino-compatible microcontroller board or a simplified Raspberry Pi compute module. The "at least one component within the baseboard" (claim 1) comprises the core microcontroller (e.g., ATmega328P for Arduino, or a Broadcom SoC for Raspberry Pi) and associated essential passive components (resistors, capacitors) as bare dies, embedded directly into a multi-layer FR4 baseboard using the process of US 8368201. The hardened insulating polymer layer and internal conductors are formed to create the necessary interconnections, power planes, and ground planes, effectively shrinking the form factor. External conductive patterns on the outer surface of the hardened insulating polymer layer provide standard interface connections (e.g., GPIO pins, USB data lines) consistent with the open-source hardware schematics. This demonstrates the application of the embedding technique to integrate common, publicly available electronic building blocks into a compact, embedded form, thus making the embedding of other standard electronic components or functional blocks from open-source hardware designs an obvious extension.