US US8307116B2

Here's a concise summary of US patent US8307116B2, "Scalable bus-based on-chip interconnection networks":

Patent US8307116B2 Summary

• Title: Scalable bus-based on-chip interconnection networks
• Inventors: Stephen W. Keckler and Boris Grot
• Filing Date: 2009-06-19
• Issue Date: 2012-11-06
• Current Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC (Note: The patent document's "Current Assignee" field at the top lists "University of Texas System," but the detailed "Legal status" timeline indicates a reassignment to EMPIRE TECHNOLOGY DEVELOPMENT LLC on 2019-07-31.)
• Abstract: The patent describes systems for routing data across multinodal on-chip networks. These systems include a multinodal array with multiple processing nodes connected by physical communication channels. At least one of these channels is configured to route data from a single starting node to two or more other destination nodes. The disclosure also covers methods for routing data and computer-accessible mediums storing instructions for such routing techniques.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (System Claim): This claim describes an on-chip network system designed for efficient data routing. The system features a multi-node array where processing nodes are arranged in horizontal and vertical rows. A key aspect is that the number of physical communication channel rows in each direction (horizontal or vertical) matches the number of nodes in that respective row. Within this system, at least one communication channel can route data from a starting node to two or more other destination nodes. A crucial efficiency feature is that data can be routed between any two nodes in the entire network with a maximum of two "hops" (i.e., transfers across a communication channel).
• Independent Claim 8 (Method Claim): This claim outlines a method for routing data within a multinodal on-chip network. The method involves first retrieving data from a storage unit using a processing arrangement. Then, a routing device sends this retrieved data from a first node to at least two other destination nodes via a single physical communication channel. Similar to Claim 1, the underlying network structure is defined by physical communication channels arranged in horizontal and vertical rows, where the number of channel rows corresponds to the number of nodes in each row. The method ensures that data transfer between any two nodes in the network is completed within a maximum of two hops.
• Independent Claim 14 (Computer-Accessible Medium Claim): This claim covers a non-transitory computer-accessible medium (like a memory chip or storage drive) that stores executable instructions. When a processing arrangement runs these instructions, it performs a procedure for routing data in a multinodal on-chip network. This procedure includes retrieving data from a storage arrangement and routing it from a first node to at least two other destination nodes through a single physical communication channel. The claim reiterates the same network configuration as in Claims 1 and 8: communication channels extending along horizontal and vertical rows, with the number of channel rows equal to the number of nodes in those rows, and all data routing occurring within a maximum of two hops.

Litigation Information:

The patent document itself notes that the patent family has litigation, specifically a US case filed in the Texas Western District Court, case number 1:26-cv-00989. However, a search for CAFC 2026 dockets for US8307116B2 did not yield any specific results indicating litigation for this patent at the U.S. Court of Appeals for the Federal Circuit for the year 2026.