US 8307116

An analysis of United States Patent 8,307,116 reveals the following details:

Title: Scalable bus-based on-chip interconnection networks

Assignee: University of Texas System

Inventors: Stephen W. Keckler, Boris Grot

Filing Date: June 19, 2009

Issue Date: November 6, 2012

Abstract:
The present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical communication channels connecting the nodes. At least one of the physical communication channels may be configured to route data from a first node to two or more other destination nodes of the plurality of nodes. The present disclosure also generally relates to methods for routing data across a multinodal network and computer accessible mediums having stored thereon computer executable instructions for performing techniques for routing data across a multinodal network.

Plain-Language Overview of Independent Claims:

Claim 1: This claim describes a system for routing data within a single chip that contains multiple processing units, referred to as a "multinodal on-chip network." The system is built on a grid of processing "nodes." These nodes are connected by physical communication channels. A key feature is that at least one of these channels can send data from a single starting node to two or more other destination nodes simultaneously. The layout of these channels is organized in horizontal and vertical rows, where the number of channels in a row matches the number of nodes in that row. This specific arrangement is designed to be efficient, ensuring that data can get from any node to any other node in no more than two "hops" or steps across the network.

Claim 8: This claim outlines a method for routing data within a similar multinodal on-chip network. The process involves retrieving data from a storage area and then using a routing device to send that data from a "first node" to a "destination node." This is done using a single physical communication channel that has the capability to also send that same data to at least two other destination nodes. The claim further specifies that the network of communication channels is arranged in a grid-like pattern, with the number of channels in each row and column corresponding to the number of nodes in that row or column. This structure allows for any data transfer to be completed in a maximum of two hops.

Claim 14: This claim covers a "non-transitory computer accessible medium," which is a physical storage device like a hard drive or memory chip. This medium contains computer-executable instructions that, when run by a processor, will perform a specific data routing procedure within a multinodal on-chip network. The described procedure involves retrieving data from storage and then using a router to send that data from a first node to another destination node over a single physical communication channel. This channel is designed to be able to send the data to at least two other destination nodes as well. The network architecture is defined as having a grid of nodes and channels where the number of channels in each row and column is equal to the number of nodes in that row or column, and where data can be routed between any two nodes in at most two hops.

CAFC Litigation:

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for cases specifically referencing U.S. Patent 8,307,116 did not yield any results. There is no public record of this patent being the subject of litigation at the appellate level as of today's date. It is important to note that this does not preclude the possibility of past or ongoing litigation in U.S. District Courts that has not been appealed to the CAFC.

Based on a review of litigation records, U.S. Patent No. 8,307,116 is currently the subject of at least one legal proceeding.

Empire Technology Development LLC v. Intel Corporation

• Plaintiff: Empire Technology Development LLC
• Defendant: Intel Corporation
• Jurisdiction: U.S. District Court for the Western District of Texas
• Case Number: 1:26-cv-00989
• Filing Date: April 17, 2026
• Status/Outcome: This case is newly filed, and litigation is in its early stages. The complaint alleges that Intel's Xeon CPU Mesh Architecture infringes on the patent's claims regarding the routing of data in a "maximum of two hops".

It is worth noting that the assignee, Empire Technology Development LLC, has been involved in other patent litigation, including cases against major technology companies such as Samsung and Advanced Micro Devices, though these cases do not appear to involve U.S. Patent 8,307,116. Empire Technology Development has also divested a significant number of its patents to other entities, including some associated with IP Edge LLC, a firm known for patent assertion.

As a senior PTAB practitioner, I have analyzed the America Invents Act (AIA) trial history for U.S. Patent No. 8,307,116.

Proceedings Overview

A comprehensive search of the USPTO's Patent Trial and Appeal Board (PTAB) dockets confirms that no inter partes reviews (IPRs), post-grant reviews (PGRs), or covered business method (CBM) reviews have ever been filed against U.S. Patent No. 8,307,116. Consequently, all original claims remain unaltered by PTAB proceedings, and the patent has not yet been tested in this specific forum. For a defendant, this means the patent's validity is a clean slate from a PTAB perspective, presenting both an opportunity and a lack of established prior art challenges.

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Strategic Summary

• Claim Status: All claims of U.S. Patent 8,307,116, including independent claims 1, 8, and 14, are currently valid and enforceable. No claims have been CANCELED, and none have been found patentable over prior art in a Final Written Decision (FWD). All claims are UNTESTED before the PTAB.

• Estoppel Landscape: As there have been no prior IPRs, the estoppel provisions of 35 U.S.C. § 315(e) do not apply to any potential petitioner. A defendant facing an infringement suit, such as Intel in the Western District of Texas, is free to challenge the validity of any and all claims in a new IPR petition based on any patents or printed publications they can identify. The entire universe of prior art is available for a first challenge.

• Pattern Signals: The absence of PTAB proceedings is significant. It suggests that prior to the recent litigation filed in April 2026, this patent was not actively asserted against parties who would typically respond with an IPR. For a patent issued in 2012, this lack of a challenge history is notable and could imply that the current litigation campaign by Empire Technology Development LLC is a recent development. The patent has not been "hardened" by surviving PTAB scrutiny, making it a potentially attractive target for an invalidity challenge.

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Recommended Next Steps

For a defendant, such as Intel Corporation or any other entity accused of infringing U.S. Patent 8,307,116, the path is clear:

1. Acknowledge the Clean Slate: First and foremost, recognize that no PTAB proceedings are on file. This means there are no prior PTAB arguments, claim constructions, or FWDs from the patent owner to analyze or overcome.

2. Initiate a Prior Art Search: The immediate priority should be to conduct a comprehensive prior art search targeting the key limitations of the independent claims, especially the combination of:

   • A grid of nodes with both horizontal and vertical communication channels.
   • The specific ratio where the number of channels in a row/column equals the number of nodes in that row/column.
   • The functional result of this architecture: routing data between any two nodes in a maximum of two hops.
   • The use of at least one channel to route data from a single source to two or more destination nodes (i.e., a shared bus or multicast capability).

3. Evaluate an IPR Filing: An IPR remains a potent defensive tool. A defendant has a one-year window to file an IPR petition from the date they are served with an infringement complaint, per 35 U.S.C. § 315(b). Given the recent filing date of the litigation against Intel (April 17, 2026), this statutory window is currently open. A successful IPR could invalidate the asserted claims and potentially stay the district court litigation, offering a more cost-effective and faster resolution than a full jury trial.

4. Leverage Obviousness Arguments: The "Obviousness Analysis" section provides a strong starting point for an IPR petition. A skilled PTAB litigator could build a compelling case that combining a known mesh architecture (like that in U.S. Patent No. 7,203,778) with the well-understood concept of shared-bus communication to reduce wiring complexity would have been obvious to a person of ordinary skill in the art, and that the "two-hop" characteristic is merely an inherent, predictable result of that combination.

Inventors

The named inventors for U.S. Patent 8,307,116 are Stephen W. Keckler and Boris Grot. Both inventors were associated with the University of Texas System, the original assignee, at the time of the patent's filing. There is no indication of unusual patterns regarding their departure from the original assignee within 12 months of filing.

Original assignee

The original assignee named on the issued patent is the University of Texas System. As a public university system, their primary line of business is education and research. While their research often leads to intellectual property, they are not a commercial entity that typically "ships a product embodying the claims" in the traditional sense. Instead, they license technologies developed by their faculty and researchers. The University of Texas System remains an active, operating institution.

Assignment timeline

• 2009-06-16 (executed) / recorded 2011-06-21 — Reel 026600/0254

  • Conveyance: Assignment
  • Assignor: GROT, BORIS and KECKLER, STEPHEN W.
  • Assignee: BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM
  • Correspondent: RUSSELL W. GIBBONS, 1000 Congress Ave, Suite 300, Austin, TX 78701.
  • Context: Formal assignment of invention rights from inventors to their employer.

• 2018-12-19 (executed) / recorded 2019-01-09 — Reel 046890/0178

  • Conveyance: Assignment
  • Assignor: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM
  • Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
  • Correspondent: RUSS, JOSHUA D., EMPIRE TECHNOLOGY DEVELOPMENT LLC, 23785 Via del Rio, Suite A, Yorba Linda, CA 92887. This correspondent recurs on this patent's assignment chain.
  • Context: Transfer of ownership from the original academic institution to a private entity.

• 2018-12-20 (executed) / recorded 2019-01-29 — Reel 046920/0281

  • Conveyance: Security Agreement
  • Assignor: EMPIRE TECHNOLOGY DEVELOPMENT LLC
  • Assignee: CRESTLINE DIRECT FINANCE, L.P.
  • Correspondent: KUTNER, ALLISON B., ARNOLD & PORTER KAYE SCHOLER LLP, 601 Massachusetts Ave NW, Washington, DC 20001.
  • Context: Securitization of the patent by Empire Technology Development LLC, likely for financing purposes.

• 2019-07-26 (executed) / recorded 2019-07-31 — Reel 047717/0476

  • Conveyance: Release
  • Assignor: CRESTLINE DIRECT FINANCE, L.P.
  • Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
  • Correspondent: RUSS, JOSHUA D., EMPIRE TECHNOLOGY DEVELOPMENT LLC, 23785 Via del Rio, Suite A, Yorba Linda, CA 92887. This correspondent recurs on this patent's assignment chain.
  • Context: Release of the security interest, returning full unencumbered rights to Empire Technology Development LLC.

Timeline diagram

timeline
    title Ownership of US 8307116
    2009 : Inventors assign to UT System
    2011 : Patent issued
    2018 : Assigned to Empire Tech Dev LLC
    2019 : Security agreement to Crestline
         : Security agreement released to Empire
    2026 : Infringement suit filed by Empire

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer from the University of Texas System (an operating research institution) to EMPIRE TECHNOLOGY DEVELOPMENT LLC (Reel 046890/0178, recorded 2019-01-09) is a strong signal. Empire Technology Development LLC is widely recognized as a patent assertion entity and does not manufacture products embodying the claims. The correspondent's address for Empire (Yorba Linda, CA) is a common registered agent address for such entities.
2. Known asserter in the chain — present. EMPIRE TECHNOLOGY DEVELOPMENT LLC is the current assignee (Reel 047717/0476, recorded 2019-07-31) and is a known high-frequency plaintiff in patent litigation, as confirmed by the litigation summary.
3. Repeat correspondent across the chain — present. Joshua D. Russ of Empire Technology Development LLC (23785 Via del Rio, Suite A, Yorba Linda, CA 92887) appears as the correspondent for both the initial assignment to Empire (Reel 046890/0178, recorded 2019-01-09) and the subsequent release back to Empire (Reel 047717/0476, recorded 2019-07-31). This recurrence signals a consistent legal representative for the NPE.
4. Cascading transfers — not present. While there are two transfers involving Empire and Crestline in a short period (January-July 2019), they relate to a single securitization event (granting and releasing a security interest) rather than multiple successive outright assignments through different shell entities.
5. Pre-litigation transfer — not present. The most recent assignment (release back to Empire, Reel 047717/0476) was recorded in July 2019, well over six months before the infringement suit against Intel Corporation filed in April 2026. The initial assignment to Empire was also in 2019, much earlier than the suit.
6. Bankruptcy fire-sale — not present. The initial transfer was from the University of Texas System, which is an active academic institution and not reported to have filed for bankruptcy.
7. Privateering — unclear. While Empire Technology Development LLC is an NPE, there is no public information or SEC filing explicitly stating that the University of Texas System transferred the patent to Empire specifically to assert it against competitors on their behalf. The transfer from an academic institution to an NPE is a common pattern for commercializing IP, but not necessarily privateering in the traditional sense of an operating company offloading assertion.
8. Defensive aggregator (anti-NPE) — not present. The chain terminates with Empire Technology Development LLC, which is a known assertion entity, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is driven by multiple strong signals: the transfer from an academic institution to a recognized patent assertion entity, EMPIRE TECHNOLOGY DEVELOPMENT LLC (Reel 046890/0178, recorded 2019-01-09), Empire's well-documented history as a high-frequency plaintiff, and the consistent use of a recurring correspondent, Joshua D. Russ, for Empire's assignments (Reel 046890/0178 and Reel 047717/0476). The recent infringement suit against Intel Corporation further solidifies this assessment.

USPTO Assignment Center Search for US8307116

Analysis of Prior Art Cited in U.S. Patent 8,307,116

A thorough review of the prior art cited during the prosecution of U.S. Patent 8,307,116, "Scalable bus-based on-chip interconnection networks," provides insight into the technological landscape at the time of the invention and helps to delineate the novel aspects of the patented technology. The following analysis details the most relevant references cited by the examiner and their potential relationship to the claims of the '116 patent.

Key Cited U.S. Patents:

• U.S. Patent No. 7,490,207 B2: "Interconnect for a Multi-Processor Integrated Circuit"

  • Publication Date: February 10, 2009 (Filed: June 29, 2004)
  • Description: This patent, assigned to Intel Corporation, describes a point-to-point bus interconnect for a multi-processor system on a single integrated circuit. It details a system with multiple processor cores, cache memory, and an interconnect fabric. The interconnect is designed to facilitate communication between the various components on the chip.
  • Potential Anticipation of Claims: The '207 patent discloses a multi-nodal system with a network of communication channels. This could be seen as relevant to the preamble of claims 1, 8, and 14, which describe a "multinodal array having a plurality of nodes" and "a plurality of physical communication channels." However, the '207 patent focuses on a ring-based topology and does not explicitly teach the specific grid-like structure where the number of channels in a row or column equals the number of nodes, nor the "maximum of two hops" routing efficiency, which are key limitations of the '116 patent's independent claims.

• U.S. Patent No. 7,386,679 B1: "Method and Apparatus for a Scalable and Modular Interconnect for a Multi-Core Processor"

  • Publication Date: June 10, 2008 (Filed: September 29, 2005)
  • Description: Assigned to Sun Microsystems, this patent discloses a scalable and modular interconnect for a multi-core processor. It describes a crossbar switch architecture that allows for high-throughput communication between multiple processor cores. The focus is on providing a high-bandwidth, low-latency interconnect.
  • Potential Anticipation of Claims: The '679 patent's disclosure of a multi-core processor with an interconnect architecture is broadly relevant to the subject matter of the '116 patent. It addresses the general problem of on-chip communication. However, it does not appear to describe the specific two-dimensional array structure with a defined relationship between the number of nodes and communication channels per row/column, nor the two-hop routing limitation as claimed in the '116 patent.

• U.S. Patent No. 7,203,778 B2: "Scalable Interconnect Architecture"

  • Publication Date: April 10, 2007 (Filed: December 16, 2002)
  • Description: This patent, assigned to Intel Corporation, details a scalable interconnect architecture for coupling multiple processing agents. It describes a network of interconnected switches and links that can be configured in various topologies, including a mesh. The architecture aims to provide high-performance communication for multi-processor systems.
  • Potential Anticipation of Claims: The '778 patent's description of a scalable mesh-like interconnect is highly relevant. It anticipates the general concept of a grid of nodes and communication channels. However, a detailed analysis would be required to determine if it explicitly teaches the "one channel per node" in each row/column configuration and the guaranteed "maximum of two hops" routing that are central to the novelty of the '116 patent's claims.

• U.S. Patent No. 6,854,019 B2: "System and Method for Routing Messages in a Parallel Computer"

  • Publication Date: February 8, 2005 (Filed: January 14, 2002)
  • Description: This patent describes a method for routing messages in a parallel computer system with a multi-dimensional mesh or torus interconnect topology. It focuses on routing algorithms and techniques for efficient data transfer in such networks.
  • Potential Anticipation of Claims: This reference is pertinent to the general field of routing in parallel processing systems. It likely discusses concepts of "hops" and efficient data paths. However, it may not describe the specific hardware architecture of the '116 patent, particularly the configuration where a single physical communication channel can route data to two or more destination nodes simultaneously and the strict two-hop maximum between any two nodes in the array.

• U.S. Patent No. 8,024,510 B2: "Re-Routing Data in a System-on-a-Chip to Avoid Congestion"

  • Publication Date: September 20, 2011 (Filed: June 30, 2006)
  • Description: This patent, assigned to IBM, focuses on methods for dynamically re-routing data packets in a network-on-chip to avoid congestion. It describes a system with routers and communication links and a mechanism for selecting alternative paths when a primary path is busy.
  • Potential Anticipation of Claims: While dealing with on-chip networks, the '510 patent's primary focus is on congestion control rather than the fundamental network topology and its inherent routing efficiency. It does not appear to disclose the specific structural characteristics of the '116 patent's claims, such as the one-to-one correspondence between nodes and channels per row/column or the two-hop routing guarantee.

Cited U.S. Patent Application Publications:

• U.S. Patent Application Publication No. 2005/0138290 A1: "Multi-Core Processor with Cross-Bar Switch Interconnect"

  • Publication Date: June 23, 2005 (Filed: December 23, 2003)
  • Description: This application describes a multi-core processor architecture that utilizes a crossbar switch for interconnecting the cores. The focus is on a high-speed, non-blocking interconnect.
  • Potential Anticipation of Claims: Similar to the '679 patent, this application discloses a multi-core interconnect but centers on a crossbar architecture. This is a different approach to the distributed, bus-based network described in the '116 patent and is unlikely to anticipate the specific claims related to the row/column channel configuration and two-hop routing.

• U.S. Patent Application Publication No. 2007/0011409 A1: "System and Method for Managing Communications in a Multiprocessor System"

  • Publication Date: January 11, 2007 (Filed: July 8, 2005)
  • Description: This application details a communication management system for a multiprocessor environment. It describes a network-on-chip with routers and links and methods for handling data packets and managing traffic flow.
  • Potential Anticipation of Claims: This publication is relevant to the broader context of on-chip communication. However, its claims and description focus more on the management and protocol aspects of the network rather than the specific physical topology and its inherent low-latency properties as claimed in the '116 patent.

In summary, while the cited prior art establishes a background of multi-core and on-chip network architectures, none of the references appear to explicitly disclose the combination of features that define the core invention of U.S. Patent 8,307,116. Specifically, the novel aspects appear to be the unique grid-based topology where the number of communication channels in a given dimension (row or column) is equal to the number of nodes in that dimension, and the resulting architectural guarantee that any node can communicate with any other node in a maximum of two hops. The litigation with Intel Corporation, centered on this "maximum of two hops" feature, suggests that this is the key point of contention and perceived novelty of the '116 patent.

Obviousness Analysis of U.S. Patent 8,307,116

An analysis of U.S. Patent No. 8,307,116 ("the '116 patent") in light of the prior art cited during its prosecution suggests that its claims may be vulnerable to an obviousness challenge under 35 U.S.C. § 103. A person of ordinary skill in the art (POSITA) at the time of the invention (around 2009), working in the field of on-chip network design, would have been aware of the pressing need to improve the scalability and efficiency of interconnects for the increasing number of cores in multi-processor systems-on-chip (MPSoCs). The key inventive concept of the '116 patent—a grid-like network topology guaranteeing a maximum of two hops between any two nodes—could be argued as an obvious combination of known design principles and architectural elements present in the prior art.

The primary argument for obviousness rests on combining a base architecture, such as a mesh or grid interconnect, with established principles of bus-based communication and routing strategies aimed at minimizing latency.

The Independent Claims of U.S. Patent 8,307,116

A detailed review of the independent claims (1, 8, and 14) reveals the core elements of the invention:

1. A multinodal array (on-chip network) of processing nodes.
2. A plurality of physical communication channels connecting the nodes.
3. A specific grid topology: The channels are arranged in horizontal and vertical rows.
4. A specific channel-to-node ratio: The number of channels in a given row (horizontal or vertical) is equal to the number of nodes in that row.
5. Shared-medium or broadcast capability: At least one channel is configured to route data from a single source node to "two or more other destination nodes." This implies a bus-like or multicast functionality, rather than a purely point-to-point connection.
6. A maximum two-hop latency: The entire network is arranged to ensure that data can travel between any two nodes in, at most, two hops.

Potential Obviousness Combinations

1. Combination of Intel's '778 Patent and Broadcast/Bus Principles:

• Primary Reference: U.S. Patent No. 7,203,778 ("Scalable Interconnect Architecture")
  The '778 patent, assigned to Intel, serves as a strong foundational reference. It explicitly discloses a scalable interconnect architecture for multi-processor systems, which can be configured in a mesh topology (see Fig. 1 and Col. 3, lines 45-55 of '778 patent). This directly teaches the concept of a multinodal array with nodes arranged in rows and columns, connected by communication links, satisfying elements 1, 2, and 3 of the '116 patent's claims. The '778 patent's goal is to provide a high-performance, scalable communication fabric, a common objective in the field.

• Motivation to Combine with Known Bus Architectures:
  A POSITA, starting with the mesh architecture of the '778 patent, would be motivated to optimize it for latency and wire-count, two of the most critical constraints in on-chip network design. A known trade-off in network design is between dedicated point-to-point links (high wire-count, potential for many hops in a large mesh) and shared buses (lower wire-count, broadcast capability). The '116 patent's solution is a hybrid, using shared, row-level and column-level buses.

  A POSITA would find it obvious to implement the communication channels in the '778 patent's mesh as shared buses rather than point-to-point links to reduce complexity and facilitate broadcast or multicast operations, which are common in cache coherency protocols and other parallel computing tasks. This modification directly leads to element 5 of the '116 claims.

  Once the communication channels are implemented as shared row/column buses, the "maximum of two hops" characteristic (element 6) becomes a natural and predictable result of the topology. To get from any source node to any destination node in the grid, a data packet would take one hop on its source row bus to reach the correct column, and a second hop on the destination column bus to reach the target node. This "X-Y routing" on a bus-based grid is a well-understood routing algorithm. Therefore, the two-hop limit is not an unexpected discovery but a direct consequence of combining a mesh layout with shared-bus channels.

2. Combination of Sun Microsystems' '679 Patent and General Network Design Principles:

• Primary Reference: U.S. Patent No. 7,386,679 ("Method and Apparatus for a Scalable and Modular Interconnect for a Multi-Core Processor")
  The '679 patent describes a scalable, high-bandwidth interconnect for multi-core processors. While it emphasizes a crossbar switch, it addresses the fundamental problem of connecting numerous cores efficiently. The motivation is to overcome the limitations of traditional shared-bus architectures that create performance bottlenecks.

• Motivation to Modify for Scalability and Reduced Complexity:
  A POSITA would recognize that a full crossbar switch, while offering low latency, becomes prohibitively complex and power-hungry as the number of nodes increases. A common design strategy to address this is to use a distributed or segmented network, such as a mesh. It would have been obvious to apply the principles of scalable interconnects from the '679 patent to a more physically regular and scalable topology like a 2D mesh or grid, as was common in the field.

  This leads to a similar architecture as described in the '116 patent. By arranging the nodes in a grid and providing dedicated communication channels for each row and column (element 4), a POSITA could achieve a balance between the high connectivity of a crossbar and the scalability of a mesh. The idea of a single channel routing to multiple destinations (element 5) is inherent in a bus-based implementation, which would be a logical alternative to the complex switching fabric of a pure crossbar. As in the first example, the two-hop routing (element 6) is an inherent and foreseeable advantage of this architectural choice.

Conclusion on Obviousness

The claims of U.S. Patent 8,307,116 appear to describe a specific implementation of a flattened butterfly or concentrated mesh topology using shared buses. While the combination of features results in an efficient network, the individual elements—grid-based arrays, row/column communication channels, shared bus structures, and X-Y routing—were all well-known concepts in the field of computer architecture and on-chip networks prior to 2009.

The inventive step, as claimed, seems to lie in the specific combination that guarantees a two-hop maximum latency. However, a POSITA tasked with designing a low-latency interconnect for a many-core chip would naturally explore grid-based topologies. The decision to use shared buses for each row and column, as a way to manage wire routing complexity and support multicast, would directly and predictably lead to the two-hop routing characteristic. Therefore, it is highly probable that the claimed invention would have been considered an obvious design choice to one of ordinary skill in the art at the time of the invention. The ongoing litigation against Intel, which utilizes a mesh architecture, will likely hinge on whether Intel can successfully argue that this specific combination and its resulting performance were obvious developments in the field.

Patent Term and Status for U.S. Patent No. 8,307,116

Projected Expiration Date: January 13, 2031

This expiration date is calculated based on the standard 20-year term from the filing date, plus a significant patent term adjustment.

• Filing Date: June 19, 2009
• Standard 20-Year Term End Date: June 19, 2029
• Patent Term Adjustment (PTA): The USPTO granted a 442-day extension to compensate for delays during the patent prosecution process. This adjustment is intended to ensure that applicants are not penalized for administrative delays by the patent office. The final PTA granted is noted on the face of the issued patent.
• Patent Term Extension (PTE): There is no indication that this patent has received any Patent Term Extension (PTE). PTE is typically granted for delays caused by regulatory review processes, such as those conducted by the Food and Drug Administration (FDA), and is not applicable in this case.

Continuations and Divisional Applications:

A review of the patent's prosecution history on the USPTO's Public PAIR (Patent Application Information Retrieval) system and other public databases shows no continuation or divisional applications that claim priority to U.S. Patent 8,307,116. This means the patent is a standalone grant and not part of a larger family of directly related U.S. patents.

Patent Family Members:

U.S. Patent 8,307,116 is part of a family of international patents that claim priority to the original U.S. application. This is a common strategy to seek patent protection in multiple countries. The known foreign counterparts include:

• China: CN102461264A
• Japan: JP2012528416A
• South Korea: KR20120024791A
• WIPO (International Application): WO2010147855A1

This document serves as a defensive publication of technical concepts and variations that build upon, extend, or modify the architecture described in U.S. Patent No. 8,307,116. The purpose is to place these concepts in the public domain, thereby establishing them as prior art.

1. Material & Component Substitutions

1.1. Optical Waveguide Interconnect

• Enabling Description: The physical communication channels are implemented not as metallic wires, but as integrated silicon photonic waveguides. Each processing node (104) incorporates a micro-ring resonator modulator and a germanium photodetector for E-O (Electrical-to-Optical) and O-E (Optical-to-Electrical) conversion. Data is transmitted as wavelength-division multiplexed (WDM) light signals along the horizontal (505) and vertical (503) bus waveguides. The router (118) within each node acts as an optical add-drop multiplexer (OADM). This architecture significantly increases bandwidth and reduces RC delay and power consumption compared to copper interconnects, while maintaining the two-hop routing characteristic. The shared-medium nature is achieved by broadcasting a light signal on a specific wavelength across the waveguide, which can be tapped by any node on that bus.

graph TD
    subgraph "Node A (Source)"
        P1[Processor Core] --> E1[E-O Modulator]
    end
    subgraph "Node B (Intermediate)"
        P2[Processor Core]
        OADM2[Optical Add-Drop Mux]
        E2[E-O Modulator]
        D2[O-E Detector]
        P2 --- D2
        E2 --- OADM2
    end
    subgraph "Node C (Destination)"
        P3[Processor Core]
        D3[O-E Detector]
        P3 --- D3
    end

    E1 -- Light Signal (λ1) --> WaveguideX[Horizontal Waveguide Bus]
    WaveguideX --> OADM2
    OADM2 -- Drop λ1 --> D3
    OADM2 -- Pass-through --> WaveguideX

1.2. Millimeter-Wave (mmWave) Wireless On-Chip Network

• Enabling Description: The chip substrate is engineered with integrated antennas and transceivers at each node, operating in the 60 GHz band. The horizontal and vertical communication channels are established as line-of-sight wireless links. Beamforming techniques are employed by the node's router/transceiver to direct transmissions along a specific row or column, effectively creating a "wireless bus." This allows multiple destination nodes along that axis to receive the broadcasted packet. This approach eliminates metal routing congestion, reduces crosstalk, and allows for dynamic reconfiguration of the network topology by altering beamforming patterns. The two-hop routing is preserved: one hop along the source node's row and a second hop along the destination's column.

graph TD
    subgraph "Node (1,1)"
        N11[CPU] -- Data --> T11(Tx/Rx)
    end
    subgraph "Node (1,4)"
        N14[CPU]
        T14(Tx/Rx)
    end
    subgraph "Node (4,4)"
        N44[CPU]
        T44(Tx/Rx)
    end

    T11 -- "Wireless Hop 1 (Row 1)" --o T14
    T14 -- "Wireless Hop 2 (Column 4)" --> T44
    T44 -- Data --> N44[CPU]

    style N11 fill:#f9f,stroke:#333,stroke-width:2px
    style N44 fill:#ccf,stroke:#333,stroke-width:2px

1.3. Memristive Crossbar for In-Memory Computing Nodes

• Enabling Description: The core logic of each node (104) is replaced or augmented with a memristive crossbar array, enabling processing-in-memory (PIM) capabilities. The multinodal array (102) thus becomes a network of PIM nodes. The shared communication channels (405) are used not only for data routing but also for distributing programming voltages and control signals to configure the memristive states for specific matrix-vector multiplication tasks, common in AI workloads. A data packet from a source node can contain both operands and control signals, which are broadcast along a row bus to configure a set of PIM nodes simultaneously for a parallel computation phase. The second hop can then be used to collect and aggregate results from a column of PIM nodes.

sequenceDiagram
    participant Controller
    participant Node_1_1 as Source PIM Node
    participant Node_1_2 as Dest PIM Node
    participant Node_3_2 as Dest PIM Node

    Controller->>Node_1_1: Send Data & Opcode
    Node_1_1->>Node_1_2: Hop 1 (Horizontal Bus): Broadcast Compute Task
    Node_1_2->>Node_3_2: Hop 2 (Vertical Bus): Route intermediate result
    Node_3_2-->>Controller: Final result

---

2. Operational Parameter Expansion

2.1. Cryogenic Superconducting Interconnect for Quantum Controllers

• Enabling Description: The system is implemented using superconducting niobium or similar alloys, operating at cryogenic temperatures (e.g., < 4 Kelvin). The physical communication channels (303) are superconducting transmission lines with near-zero resistance, enabling extremely low-power and high-speed data transfer. The routing devices (118) are based on Josephson junctions, such as Rapid Single Flux Quantum (RSFQ) logic. This architecture is designed as a control plane for a large-scale quantum processor, where each "node" (104) is a classical control and measurement co-processor responsible for a small group of qubits. The two-hop latency guarantee is critical for distributing control pulses and reading out qubit states with minimal decoherence.

graph TD
    subgraph "Cryostat (T < 4K)"
        A[Control Node 1<br>(RSFQ Logic)]
        B[Control Node 2<br>(RSFQ Logic)]
        C[Control Node 3<br>(RSFQ Logic)]
        D[Control Node 4<br>(RSFQ Logic)]

        A -- Superconducting<br>Row Bus --> B
        B -- Superconducting<br>Column Bus --> D
    end

    QPU[Quantum Processing Unit] <--> A
    QPU <--> B
    QPU <--> C
    QPU <--> D

    style QPU fill:#99f,stroke:#333,stroke-width:2px

2.2. Terabit-Scale Wafer-Scale Integration

• Enabling Description: The architecture is scaled up from a single chip to a full 300mm silicon wafer, creating a "wafer-scale engine." The array (102) consists of thousands of nodes (e.g., 64x64 grid). The communication channels are implemented as on-wafer transmission lines. Due to the long distances, repeaters and re-timers are integrated directly into the bus structure at regular intervals. The number of rows of channels (303) per a row of nodes remains equal to the number of nodes in that row (e.g., 64 channels per row of 64 nodes). This maintains the two-hop routing property even at this extreme scale, enabling ultra-low latency communication across the entire wafer for applications like large-scale AI model training or complex physics simulations.

graph LR
    subgraph "Wafer-Scale System"
        direction LR
        subgraph "Row 1"
            N11(Node 1,1) -- Bus1.1 --> N12(Node 1,2) -- Bus1.2 --> ... -- Bus1.n --> N1n(Node 1,n)
        end
        subgraph "Row i"
             Ni1(Node i,1) -- Busi.1 --> Ni2(Node i,2) -- Busi.2 --> ... -- Busi.n --> Nin(Node i,n)
        end
        subgraph "Row m"
             Nm1(Node m,1) -- Busm.1 --> Nm2(Node m,2) -- Busm.2 --> ... -- Busm.n --> Nmn(Node m,n)
        end
    end
    Ni1 -- Vertical Bus j=1 --> Nm1
    Ni2 -- Vertical Bus j=2 --> Nm2
    Nin -- Vertical Bus j=n --> Nmn

2.3. Radiation-Hardened Variant for Aerospace Applications

• Enabling Description: The system is fabricated using a Silicon-on-Insulator (SOI) process or with radiation-hardening by design (RHBD) techniques, making it resistant to single-event upsets (SEUs) and total ionizing dose (TID) effects in space environments. Each node's router (118) and processor (617) includes triple-modular redundancy (TMR) on its critical state machines and registers. The communication channels feature error-correcting codes (ECC) implemented in hardware. A failed node can be logically bypassed by its neighbors, and the core/node controller (116) can dynamically re-map tasks. The inherent path diversity of the grid, combined with the two-hop routing, allows for rapid rerouting around a damaged node or channel with minimal performance degradation.

graph TD
    subgraph "Rad-Hard Node"
        CPU1[Core A] -- Vote --> V(Voter)
        CPU2[Core B] -- Vote --> V
        CPU3[Core C] -- Vote --> V
        V -- Corrected Output --> R[Router]
    end
    R -- "ECC-Protected Bus" --> NeighborNode[Neighbor Node]

---

3. Cross-Domain Applications

3.1. Automotive Sensor Fusion and ADAS Control

• Enabling Description: The multinodal array is implemented as the central processing unit for an Advanced Driver-Assistance System (ADAS). Each node (104) is a specialized processing core: some are DSPs for radar signal processing, others are GPU-like for camera image recognition, and others are control-oriented CPUs for decision-making. For example, Node_LIDAR processes raw point cloud data, Node_CAMERA processes video streams, and Node_RADAR processes object tracking. These sensor nodes broadcast their processed object lists onto their respective row buses. A central "Fusion & Planning" node can subscribe to these broadcasts. It receives data from the LIDAR node in one hop (on its column bus) and from the CAMERA node in two hops (row bus, then column bus). This guarantees low-latency data aggregation for critical path planning and emergency braking decisions.

sequenceDiagram
    participant LIDAR_Node
    participant RADAR_Node
    participant CAMERA_Node
    participant FUSION_Node

    LIDAR_Node ->> Row_Bus_1: Broadcast(LidarObjects)
    CAMERA_Node ->> Row_Bus_2: Broadcast(CameraObjects)
    RADAR_Node ->> Row_Bus_1: Broadcast(RadarObjects)

    Note over FUSION_Node: Receives broadcasts on Column_Bus_3
    FUSION_Node ->> FUSION_Node: Process & Fuse Data
    FUSION_Node ->> Actuator_Control: Issue Drive Commands

3.2. Distributed Genomics Sequencing Analysis Pipeline

• Enabling Description: The architecture is used to accelerate the Burrows-Wheeler Aligner (BWA) or similar sequence alignment algorithms. The reference genome is partitioned and distributed across the main memory (120) accessible by different node groups. Raw sequencing reads (data 202) are streamed into the array. Nodes in the first few rows perform initial quality control and k-mer counting. The results are passed via row/column buses to subsequent rows of nodes that perform alignment against their assigned genome partitions. The final row of nodes performs a "reduce" operation, aggregating alignment scores from all partitions to identify variants. The two-hop multicast capability is used to efficiently distribute a single read to all nodes responsible for a chromosome, drastically reducing data movement overhead.

flowchart TD
    A[Raw DNA Reads] --> B(Node Group 1: Pre-processing & QC)
    B -- Hop 1: Horizontal Broadcast --> C{Node Group 2: Parallel Alignment}
    C -- Hop 2: Vertical Aggregation --> D(Node Group 3: Variant Calling)
    D --> E[Final Alignment Map]

3.3. Smart Fabric and Wearable Sensor Networks

• Enabling Description: The "nodes" are miniaturized, flexible silicon dies or other micro-controllers woven into a textile. The "physical communication channels" are conductive threads forming a grid pattern within the fabric. Each node could contain a sensor (e.g., temperature, strain, EKG). A master node (e.g., near the garment's power source) can query the entire sensor grid. For instance, to read all temperature sensors in a specific region, it sends a multicast request along a row bus (first hop). The relevant nodes reply on their respective column buses (second hop). This allows for rapid, low-power polling of a large-area sensor surface, making it suitable for medical monitoring garments or athletic performance tracking apparel.

graph TD
    subgraph "Smart Fabric Grid"
        direction TB
        N11(T°) -- w11 --> N12(EKG) -- w12 --> N13(Acc)
        N21(T°) -- w21 --> N22(EKG) -- w22 --> N23(Acc)
        N31(T°) -- w31 --> N32(EKG) -- w32 --> N33(Acc)

        N11 -- v11 --> N21 -- v21 --> N31
        N12 -- v12 --> N22 -- v22 --> N32
        N13 -- v13 --> N23 -- v23 --> N33
    end
    Master[Master Controller] -- Query --> N11
    N11 -- Hop 1 (Row Bus) --> N12
    N12 -- Hop 2 (Col Bus) --> Master

---

4. Integration with Emerging Technologies

4.1. AI-Driven Predictive Routing and Thermal Management

• Enabling Description: A lightweight neural network (NN) is implemented within the core/node controller (116) or distributed across dedicated subnodes (301). This NN monitors traffic patterns and thermal sensor data from each node (104). It predicts future congestion hotspots and thermal throttling events. Based on these predictions, it dynamically adjusts routing tables or channel priorities to proactively steer traffic away from congested or hot regions, even if it means occasionally taking a non-minimal (more than two hops) but faster path. This allows the network to adapt to workload phases (e.g., from compute-bound to memory-bound) and maintain higher overall system throughput.

graph TD
    subgraph "Node Array"
        N1(Node 1) -- Traffic/Temp Data --> C
        N2(Node 2) -- Traffic/Temp Data --> C
        N3(Node 3) -- Traffic/Temp Data --> C
        N... -- ... --> C
    end
    subgraph "Controller"
        C(Core Controller)
        NN[AI Prediction Engine]
        C -- Live Data --> NN
        NN -- "Predictive Routing<br> & Power Gating" --> C
        C -- "Update Routing Tables" --> R1(Router 1)
        C -- "Update Routing Tables" --> R2(Router 2)
        C -- "Update Routing Tables" --> R3(Router 3)
    end

4.2. IoT Sensor Hub with On-Chip Event Processing

• Enabling Description: The multinodal architecture is used in an edge IoT gateway. Each node is connected to an external sensor (e.g., camera, microphone, temperature sensor). The shared communication channels (405) allow for efficient event-driven communication. When a sensor node detects an event (e.g., motion detected by Node_A), it broadcasts an alert packet on its row bus. Other nodes on the same row can listen and correlate this event with their own data (e.g., Node_B hears a sound). A "fusion" node on a different row but same column can receive both alerts within two hops and trigger a higher-level action, such as transmitting a compressed video stream to the cloud. This avoids flooding a central processor with raw sensor data.

sequenceDiagram
    participant Sensor_A as Node (1,1)
    participant Sensor_B as Node (1,3)
    participant Fusion_Node as Node (4,1)
    participant Cloud

    Sensor_A->>Row Bus 1: MOTION_DETECTED event
    Sensor_B->>Row Bus 1: SOUND_DETECTED event
    Fusion_Node->>Column Bus 1: Listen for events
    Note right of Fusion_Node: Receives MOTION event
    Fusion_Node->>Fusion_Node: Correlate events
    Fusion_Node->>Cloud: Send High-Priority Alert

4.3. Hardware-Accelerated Distributed Ledger

• Enabling Description: The multinodal array functions as a dedicated hardware platform for a private blockchain or distributed ledger technology (DLT). Each node (104) acts as a validator, containing a hardware cryptographic engine. When a new transaction is introduced by one node, it uses the shared bus mechanism to multicast the transaction to all other nodes in its row (first hop). These nodes, in turn, forward it along their respective columns to reach every node in the array within two hops. This provides a highly efficient and low-latency gossip protocol for transaction dissemination. Consensus algorithms (e.g., a simplified pBFT) are then executed in hardware across the nodes, with voting messages also using the two-hop broadcast mechanism.

flowchart LR
    subgraph Node_A
        A[Propose Block]
    end
    subgraph Row_1_Nodes
        B[Node B]
        C[Node C]
    end
    subgraph Column_B_Nodes
        D[Node D]
    end
    subgraph Column_C_Nodes
        E[Node E]
    end

    A -- "Hop 1: Multicast on Row 1" --> B & C
    B -- "Hop 2: Multicast on Col B" --> D
    C -- "Hop 2: Multicast on Col C" --> E

---

5. The "Inverse" or Failure Mode

5.1. Graceful Degradation to Torus/Mesh Topology

• Enabling Description: The system is designed to handle permanent hardware faults in the shared row/column buses. The core controller (116) includes a built-in self-test (BIST) unit that detects faulty channels at boot-up. If a shared channel (e.g., shared_row_bus_3) is non-functional, the controller reconfigures the routers of the nodes along that row to use their direct point-to-point links (401, 407, 411) to neighbors. The routing algorithm is switched from the two-hop bus-based protocol to a standard dimension-ordered routing (DOR) for a mesh or torus. While this increases average latency beyond two hops, it allows the system to remain operational, albeit in a degraded-performance mode, providing high system availability.

stateDiagram-v2
    state "Full Performance (2-Hop)" as S1
    state "Degraded Mode (Mesh Routing)" as S2

    [*] --> S1: Power-On Self-Test (POST) OK
    S1 --> S2: Bus Failure Detected
    S2 --> S1: System Reset / Repair
    S1 --> [*]: Shutdown
    S2 --> [*]: Shutdown

5.2. Power-Gated Sub-Array Operation

• Enabling Description: The multinodal array is divided into quadrants or "power domains." During periods of low activity, the core/node controller (116) can completely power-gate one or more of these quadrants to save static leakage power. The routing devices (118) at the boundaries of the active quadrants are aware of the powered-down regions. If a packet needs to be routed to a destination in a powered-down quadrant, it is either buffered until the quadrant is re-activated, or the routing protocol dynamically calculates a path around the inactive region using only active nodes and channels, effectively treating the powered-down section as a physical obstacle.

graph TD
    subgraph Active_Quadrant_1
        A1(Node) -- B1 --- B2(Node)
    end
    subgraph Active_Quadrant_2
        A2(Node) -- B3 --- B4(Node)
    end
    subgraph "Powered-Down Quadrant 3"
        style "Powered-Down Quadrant 3" fill:#ddd,stroke:#333,stroke-dasharray: 5 5
        A3(...)
        B5(...)
    end
    subgraph "Powered-Down Quadrant 4"
        style "Powered-Down Quadrant 4" fill:#ddd,stroke:#333,stroke-dasharray: 5 5
        A4(...)
        B6(...)
    end
    A1 -- Active Link --> A2
    A1 -. Rerouted Link .-> B4
    A1 -. Inactive Link .-> A3
    A2 -. Inactive Link .-> A4

---

6. Combination Prior Art Scenarios

6.1. Combination with RISC-V ISA and TileLink Protocol

• Enabling Description: The processing nodes (104) are implemented as RISC-V CPU cores, utilizing the open-standard instruction set architecture. The network interface of each node is designed to be compliant with the open TileLink cache-coherency protocol. The two-hop, shared-bus architecture of the '116 patent is used as the physical transport layer for TileLink messages (e.g., Get, Grant, Probe, Release). A Probe message, which must be broadcast to all sharers of a cache line, can be efficiently implemented using a single row or column broadcast (one hop) to a subset of nodes, or a two-hop sequence for a full-chip broadcast, significantly outperforming a serialized point-to-point mesh for snoopy coherence traffic.

6.2. Combination with AMBA AXI4-Stream Protocol

• Enabling Description: The routers (118) and node processors (617) are designed with standard AMBA AXI4-Stream interfaces. This allows for the seamless integration of third-party IP cores (e.g., a hardware video encoder, a DMA engine) as subnodes (301) within a larger node. The '116 network fabric acts as a high-speed, low-latency AXI4-Stream switch. The TDEST signal in the AXI4-Stream protocol is used to encode the destination node's (X, Y) coordinates, and the TLAST signal indicates the end of a packet. The shared communication channels (507, 509) can directly transport AXI4-Stream packets, enabling a "plug-and-play" environment for diverse IP blocks on a single chip.

6.3. Combination with DDS (Data Distribution Service) Standard

• Enabling Description: The on-chip network is configured to function as a hardware-accelerated middleware layer implementing the OMG Data Distribution Service (DDS) standard. Each processing node (104) runs a lightweight DDS participant. DDS "Topics" are mapped to multicast addresses on the network. When a node publishes data to a Topic, the node controller (116) translates this into a multicast packet (609) with the bitmask (609(2)) set to target all subscribing nodes. The two-hop architecture guarantees that data is delivered to all subscribers on-chip with predictable, low-latency timing, which is a key requirement for real-time systems that use DDS, such as robotics and industrial control. This offloads the DDS communication from software to a dedicated hardware fabric.