US 8307116

An analysis of United States Patent 8,307,116 reveals the following details:

Title: Scalable bus-based on-chip interconnection networks

Assignee: University of Texas System

Inventors: Stephen W. Keckler, Boris Grot

Filing Date: June 19, 2009

Issue Date: November 6, 2012

Abstract:
The present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical communication channels connecting the nodes. At least one of the physical communication channels may be configured to route data from a first node to two or more other destination nodes of the plurality of nodes. The present disclosure also generally relates to methods for routing data across a multinodal network and computer accessible mediums having stored thereon computer executable instructions for performing techniques for routing data across a multinodal network.

Plain-Language Overview of Independent Claims:

Claim 1: This claim describes a system for routing data within a single chip that contains multiple processing units, referred to as a "multinodal on-chip network." The system is built on a grid of processing "nodes." These nodes are connected by physical communication channels. A key feature is that at least one of these channels can send data from a single starting node to two or more other destination nodes simultaneously. The layout of these channels is organized in horizontal and vertical rows, where the number of channels in a row matches the number of nodes in that row. This specific arrangement is designed to be efficient, ensuring that data can get from any node to any other node in no more than two "hops" or steps across the network.

Claim 8: This claim outlines a method for routing data within a similar multinodal on-chip network. The process involves retrieving data from a storage area and then using a routing device to send that data from a "first node" to a "destination node." This is done using a single physical communication channel that has the capability to also send that same data to at least two other destination nodes. The claim further specifies that the network of communication channels is arranged in a grid-like pattern, with the number of channels in each row and column corresponding to the number of nodes in that row or column. This structure allows for any data transfer to be completed in a maximum of two hops.

Claim 14: This claim covers a "non-transitory computer accessible medium," which is a physical storage device like a hard drive or memory chip. This medium contains computer-executable instructions that, when run by a processor, will perform a specific data routing procedure within a multinodal on-chip network. The described procedure involves retrieving data from storage and then using a router to send that data from a first node to another destination node over a single physical communication channel. This channel is designed to be able to send the data to at least two other destination nodes as well. The network architecture is defined as having a grid of nodes and channels where the number of channels in each row and column is equal to the number of nodes in that row or column, and where data can be routed between any two nodes in at most two hops.

CAFC Litigation:

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for cases specifically referencing U.S. Patent 8,307,116 did not yield any results. There is no public record of this patent being the subject of litigation at the appellate level as of today's date. It is important to note that this does not preclude the possibility of past or ongoing litigation in U.S. District Courts that has not been appealed to the CAFC.