US 7373531

US patent 7373531, titled "Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus," was filed on May 5, 2005, and issued on May 13, 2008. The original assignee was Fujitsu Ltd, and the current assignee is Near Field Electronics LLC, as of June 17, 2025. The inventors are Katsuya Shimizu and Hiroko Kinoshita.

Abstract:
The patent describes a power consumption control device designed to detect the output of a pulse signal from an oscillator, which acts as an operation monitoring target. This device outputs a power consumption reduction signal if no pulse signal is detected within a predetermined time. It achieves this by using a p-type transistor and an n-type transistor connected in series, with their gates connected to the oscillator's output terminal. A detecting means then monitors a through current flowing through these transistors, and the power consumption reduction signal is triggered when this through current is not detected for a specified duration.

Independent Claims Overview:

• Claim 1 (Signal Detection Method): This method involves detecting the presence of an input signal by monitoring a "through current" flowing through a circuit. The circuit includes a p-type transistor and an n-type transistor, whose gates receive the input signal, along with a transistor configured to perform a current mirror function. The input of the signal is detected based on whether or not this through current flowed.
• Claim 2 (Signal Detection Method for State Determination): This method detects the through current in a circuit receiving an input signal. If the through current is detected, the signal is determined to be in a "first state," meaning it repeatedly switches between high and low levels. If the through current is not detected within a predetermined period, the signal is determined to be in a "second state," indicating it is held at either a high or low level.
• Claim 4 (Frequency Detection Method): This method detects the frequency of an input signal by detecting a through current flowing through a circuit. The circuit comprises p-type and n-type transistors with gates to which the signal is inputted, and a transistor to perform a current mirror function. The signal's frequency is then determined based on the characteristics of the detected through current.
• Claim 5 (Power Consumption Control Method): This method involves detecting a through current in a circuit receiving a signal from an operation monitoring target. It determines the signal's state as either a "first state" (repeated high/low switching) if through current is detected, or a "second state" (held high/low) if no through current is detected within a predetermined time. A power consumption reduction signal is then outputted if the signal is determined to be in the second state.
• Claim 6 (Signal Detecting Device): This device includes a detector for sensing a through current in a circuit that receives an input signal. The device detects the input of the signal based on the presence or absence of this through current. The circuit itself contains a p-type transistor and an n-type transistor, whose gates are connected to the input signal, and a transistor for a current mirror function.
• Claim 7 (Signal Detecting Device for State Determination): This device, with its detector for through current, determines the state of an input signal. If the detector finds a through current, the signal is considered to be in a "first state" (repeated high/low alternation). If the detector does not find a through current within a predetermined time, the signal is considered to be in a "second state" (held at a high or low level).
• Claim 9 (Frequency Detecting Device): This device comprises a detector for detecting a through current in a circuit that receives an input signal. The device uses the detected through current to determine the frequency of the signal. The circuit includes a p-type transistor, an n-type transistor with gates connected to the signal, and a transistor to perform a current mirror function.
• Claim 10 (Power Consumption Control Device): This device features a detector for a through current in a circuit receiving a signal from an operation monitoring target. It determines if the signal is in a "first state" (repeated high/low) when through current is detected, or a "second state" (held high/low) when no through current is detected within a predetermined time. A power consumption reduction signal is then outputted if the signal is determined to be in the second state.
• Claim 11 (Electronic Apparatus): This apparatus incorporates the power consumption control device described in Claim 10. It also includes an operation monitoring target device that outputs a signal in a "first state" when operating and a "second state" when not operating. Furthermore, it has a power supply control device that executes either a power supply stopping or power supply reducing process for the operation monitoring target, based on the power consumption reduction signal from the control device.

Litigation Information:
According to the patent's metadata, there has been litigation related to this patent family, with several US cases filed in the Texas Eastern District Court and Delaware District Court in 2025. There is also mention of the "First worldwide family litigation filed." However, a search of CAFC 2026 dockets for US7373531 did not yield any specific results for this patent number. Therefore, there is no authoritative information about specific CAFC 2026 dockets related to US7373531.

As of April 26, 2026, the patent metadata indicates that there has been litigation related to US Patent 7373531. Specifically, there are records of several US cases filed in the Texas Eastern District Court and Delaware District Court in 2025. The metadata also notes that the "First worldwide family litigation" has been filed.

However, the provided search results from Unified Patents and PACER, and a specific search for CAFC 2026 dockets for US7373531 did not yield specific case details (plaintiffs, defendants, case numbers, filing dates, and outcomes) for this patent. While Unified Patents tracks patent litigation and challenges patent validity, and PACER provides access to federal court records, the direct queries for US7373531 did not return the granular case information requested.

Therefore, while the patent metadata confirms the existence of litigation, specific details for known cases involving US patent 7373531 are not available in the provided search results.

PTAB proceedings on file

The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest.

Proceedings overview

There are no recorded AIA trial proceedings (IPR, PGR, or CBM) for US Patent 7,373,531 on file. This indicates that the patent claims have not been challenged or adjudicated through the PTAB trial process. This gives a defendant facing assertion of this patent the flexibility to challenge its validity at the PTAB without facing estoppel from prior proceedings.

Strategic summary

As there are no PTAB proceedings on file for US Patent 7,373,531, all claims (1-13) remain UNTESTED at the PTAB. There are no canceled or sustained claims through this administrative process.

The absence of PTAB activity means there is no estoppel landscape under 35 U.S.C. § 315(e)(2) for potential petitioners. Any defendant being asserted against this patent is free to raise any available prior-art grounds for invalidity in a new IPR or PGR petition, assuming the statutory window for filing is open (e.g., IPRs can be filed anytime after the later of 9 months from grant or termination of a PGR, and before a district court complaint is filed, or within one year of service of a complaint). Given the patent's expiration on March 19, 2026, the window for filing new AIA trial proceedings may have closed, as new proceedings cannot be instituted on an expired patent, though a petition could have been filed before expiration and proceed to a decision.

There are no pattern signals to observe, such as multiple IPRs from the same petitioner or aggressive appeals by the patent owner, given the lack of proceedings.

Recommended next steps

Since no PTAB activity exists for US Patent 7,373,531, a defendant facing assertion of this patent should consider the following:

• Validity Analysis: Conduct a thorough prior art search and develop strong invalidity arguments under 35 U.S.C. §§ 102 and 103 against the asserted claims.
• PTAB Feasibility Check (if applicable): While the patent has expired, if a demand letter or lawsuit were initiated before the expiration date (2026-03-19), it would be crucial to determine if there was still an opportunity to file an IPR petition at that time, and whether any such petition was filed but not yet recorded in publicly accessible databases. For any new assertion after the expiration, filing a new PTAB petition is not possible, but prior art defenses can still be raised in district court litigation.
• Leverage Litigation History: The patent's metadata indicates a history of litigation in the Texas Eastern District Court and Delaware District Court in 2025. While these are not PTAB proceedings, understanding the outcomes of these cases and any validity arguments raised therein could be highly beneficial. A deeper dive into these district court dockets would be a crucial next step.
• Absence of PTAB Activity: The fact that no PTAB proceedings were initiated against this patent during its lifetime, despite a history of district court litigation, could suggest a few things: either the prior art challenges were not strong enough to warrant IPRs, or the disputes were resolved through settlement before PTAB challenges were pursued. This absence is itself a signal to investigate further.

Given the patent's expired status, any ongoing litigation would primarily concern past infringement. New IPRs or PGRs are not possible. Therefore, validity challenges would need to be pursued in district court.

Inventors

• Katsuya Shimizu (Fujitsu Ltd)
• Hiroko Kinoshita (Fujitsu Ltd)

No unusual patterns detected regarding inventor departures.

Original assignee

The original assignee on the issued patent was Fujitsu Ltd. Fujitsu Ltd. is a Japanese multinational information and communications technology equipment and services corporation. They ship a wide range of products, including those embodying signal detection and power consumption control technologies. Fujitsu Ltd is currently operating.

Assignment timeline

• 2005-05-05 (executed) / recorded 2005-05-05 — Reel 016542/0351

  • Conveyance: Assignment
  • Assignor: Katsuya Shimizu, Hiroko Kinoshita
  • Assignee: FUJITSU LIMITED
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Original assignment from inventors to the filing company.

• 2008-11-04 (executed) / recorded 2008-12-12 — Reel 021998/0645

  • Conveyance: Assignment
  • Assignor: FUJITSU LIMITED
  • Assignee: FUJITSU MICROELECTRONICS LIMITED
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Internal corporate reorganization/transfer.

• 2010-04-01 (executed) / recorded 2010-07-22 — Reel 024982/0245

  • Conveyance: Change of Name
  • Assignor: FUJITSU MICROELECTRONICS LIMITED
  • Assignee: FUJITSU SEMICONDUCTOR LIMITED
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Corporate name change.

• 2013-08-29 (executed) / recorded 2013-09-11 — Reel 031205/0461

  • Conveyance: Assignment
  • Assignor: FUJITSU SEMICONDUCTOR LIMITED
  • Assignee: SPANSION LLC
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Transfer of assets, likely a fire-sale or portfolio divestiture.

• 2015-03-12 (executed) / recorded 2015-03-21 — Reel 035240/0429

  • Conveyance: Security Interest
  • Assignor: CYPRESS SEMICONDUCTOR CORPORATION, SPANSION LLC
  • Assignee: MORGAN STANLEY SENIOR FUNDING, INC.
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Grant of a security interest, typically related to a loan or financing agreement.

• 2015-06-01 (executed) / recorded 2015-06-30 — Reel 036037/0001

  • Conveyance: Assignment
  • Assignor: SPANSION, LLC
  • Assignee: CYPRESS SEMICONDUCTOR CORPORATION
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Acquisition of Spansion LLC by Cypress Semiconductor Corporation.

• 2016-12-09 (executed) / recorded 2016-12-14 — Reel 040908/0979

  • Conveyance: Assignment
  • Assignor: CYPRESS SEMICONDUCTOR CORPORATION
  • Assignee: MONTEREY RESEARCH, LLC
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Transfer of patent to a licensing entity.

• 2016-12-09 (executed) / recorded 2016-12-22 — Reel 041178/0061

  • Conveyance: Release by Secured Party
  • Assignor: MORGAN STANLEY SENIOR FUNDING, INC.
  • Assignee: CYPRESS SEMICONDUCTOR CORPORATION, SPANSION LLC
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Release of security interest.

• 2015-03-12 (executed) / recorded 2020-11-03 — Reel 058002/0470

  • Conveyance: Corrective Assignment
  • Assignor: CYPRESS SEMICONDUCTOR CORPORATION, SPANSION LLC
  • Assignee: MORGAN STANLEY SENIOR FUNDING, INC.
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Correction of a previously recorded security interest.

• 2025-01-31 (executed) / recorded 2025-05-16 — Reel 071299/0161

  • Conveyance: Assignment
  • Assignor: MONTEREY RESEARCH LLC
  • Assignee: SOUTHFORK IP HOLDINGS LLC
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Transfer of patent between licensing entities.

• 2025-06-17 (executed) / recorded 2025-06-17 — Reel 071434/0523

  • Conveyance: Assignment
  • Assignor: SOUTHFORK IP HOLDINGS LLC
  • Assignee: NEAR FIELD ELECTRONICS LLC
  • Correspondent: Not specified in the provided patent text for this event.
  • Context: Transfer of patent between licensing entities.

Timeline diagram

timeline
    title Ownership of US 7373531
    2005 : Assigned to Fujitsu Ltd
    2008 : Assigned to Fujitsu Microelectronics
    2010 : Name changed to Fujitsu Semiconductor
    2013 : Assigned to Spansion LLC
    2015 : Security interest to Morgan Stanley
         : Assigned to Cypress Semi
    2016 : Assigned to Monterey Research LLC
         : Security interest released
    2020 : Corrective assignment
    2025 : Assigned to Southfork IP Holdings
         : Assigned to Near Field Electronics

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer from Cypress Semiconductor Corporation to MONTEREY RESEARCH, LLC on 2016-12-09 (Reel 040908/0979) and subsequent transfers to SOUTHFORK IP HOLDINGS LLC on 2025-01-31 (Reel 071299/0161) and NEAR FIELD ELECTRONICS LLC on 2025-06-17 (Reel 071434/0523) suggest transfers to licensing-only entities. "Research," "Holdings," and "Electronics" in the names often indicate such entities.
2. Known asserter in the chain — present. Monterey Research, LLC is known as a patent assertion entity. The patent was assigned to Monterey Research, LLC on 2016-12-09 (Reel 040908/0979).
3. Repeat correspondent across the chain — unclear. The provided text from Google Patents legal events does not consistently list correspondent information, making it impossible to determine if the same attorney or firm appears across multiple assignments.
4. Cascading transfers — present. There are two transfers in close succession in 2025: from Monterey Research LLC to Southfork IP Holdings LLC on 2025-05-16 (Reel 071299/0161) and from Southfork IP Holdings LLC to Near Field Electronics LLC on 2025-06-17 (Reel 071434/0523), both within a span of 2 months. This pattern is indicative of cascading transfers.
5. Pre-litigation transfer — unclear. While the patent metadata indicates litigation in 2025, specific filing dates for the lawsuits are not provided in direct relation to the assignment dates. The transfers to Southfork IP Holdings LLC (2025-05-16) and Near Field Electronics LLC (2025-06-17) occurred shortly before or around the time litigation was filed in 2025, which could suggest pre-litigation transfer. However, without precise litigation filing dates, a definitive "present" cannot be made with high confidence.
6. Bankruptcy fire-sale — not present. The assignments from Fujitsu Ltd. to Spansion LLC and later entities do not indicate a bankruptcy proceeding of the original assignee.
7. Privateering — unclear. There is no information in the provided text to suggest that an operating company transferred the patent to an NPE to assert on its behalf against competitors.
8. Defensive aggregator (anti-NPE) — not present. The chain terminates with Near Field Electronics LLC, which is not identified as a defensive aggregator.

Verdict

NPE — high confidence. The presence of a known patent assertion entity (Monterey Research, LLC) in the ownership chain (Reel 040908/0979, 2016-12-14 recorded date) and subsequent cascading transfers to other entities (Southfork IP Holdings LLC on Reel 071299/0161, 2025-05-16 recorded date; Near Field Electronics LLC on Reel 071434/0523, 2025-06-17 recorded date) are strong indicators of an NPE assertion pattern.

For verification, see the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search for patent number 7373531).

To find the most relevant prior art for US patent 7373531 and perform a detailed analysis for each citation, I need direct access to the full citation list from the USPTO database for this specific patent. The provided search results indicate that "Patent Public Search" is the tool to use for this purpose. However, I cannot directly interact with a live USPTO database search interface.

Therefore, I cannot fulfill the request to provide the full citation, publication/filing date, brief description, and which claim(s) it potentially anticipates under 35 U.S.C. § 102 for each prior art reference, as I require the explicit list of cited prior art from the USPTO record for US7373531.

Please provide the list of "Patent Citations" directly from the US7373531 patent document on Google Patents, as found in the "Citations" section. Once that list is available, I can proceed with analyzing each cited reference based on the patent text I have.

Obviousness Analysis of US Patent 7,373,531 under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 7,373,531 ("the '531 patent") by considering combinations of prior art references cited within the patent and general knowledge accessible to a Person Having Ordinary Skill in the Art (PHOSITA) at the time of the invention (priority date January 11, 2005). The '531 patent introduces methods and devices for signal detection, frequency detection, and power consumption control by monitoring "through current" (also known as shoot-through current or short-circuit current) in series-connected p-type and n-type transistors whose gates receive the input signal. This approach aims to overcome limitations of conventional methods, such as the inability to distinguish between active signals and signals stopped at a high level, or slow response times of RC integration circuits, as described in the patent's background (see FIGS. 1 and 2, and discussion of JP2000224015A).

A PHOSITA in the field of digital circuit design and power management at the time of the invention would be motivated to develop simpler, faster, and more reliable methods for detecting signal activity and managing power consumption in electronic devices.

Combination 1: JP2000224015A in view of general knowledge of CMOS through current and current mirror circuits.

This combination primarily addresses the obviousness of independent Claims 1, 2, 3, 5, 6, 7, 8, 10, 11, 12, and 13.

• JP2000224015A (Nec Corp): This Japanese patent application, titled "Clock stoppage detecting circuit and semiconductor integrated circuit device provided therewith," is explicitly discussed in the background of the '531 patent. It teaches a circuit for detecting clock stoppage and outputting a power consumption reduction signal to save power. The '531 patent notes a drawback of this prior art: it "has the problem that the circuit becomes larger in size" because "different circuits are used to detect the clock signal stopped in a high state and the clock signal stopped in a low state, respectively". This reference establishes the problem of inefficient or complex clock stoppage detection for power saving.

• General Knowledge of CMOS Through Current: It is a fundamental principle in CMOS circuit design that when the input signal to a CMOS inverter (comprising a p-type and an n-type transistor connected in series with their gates tied together and receiving the input signal) transitions from a low level to a high level, or vice-versa, both transistors are momentarily conductive. This creates a transient "through current" path from the power supply (VDD) to ground (VGD). Crucially, this through current is present only during transitions and is absent when the input signal is stable at either a high or a low level. This phenomenon is a well-known contributor to dynamic power consumption in CMOS circuits, and its presence or absence is a direct indicator of switching activity. The '531 patent itself acknowledges this principle: "Since the through current is generated at an intermediate potential... it is generated when the signal switches... Therefore, the presence or absence of an input signal can be detected based on the presence or absence of the through current."

• General Knowledge of Current Mirror Circuits: Current mirror circuits are a common and well-understood technique in analog and mixed-signal circuit design for sensing, replicating, or providing a proportional current without significantly loading the source of the current. The '531 patent's detailed description (FIG. 3) illustrates a circuit where transistors M0 and M1 function as a current mirror to detect the through current flowing through M2 and M3.

• Motivation for a PHOSITA to Combine: A PHOSITA, aiming to improve upon the conventional clock stoppage detection circuits (such as those described in JP2000224015A and FIGS. 1 and 2 of the '531 patent's background), would be motivated to find a simpler, faster, and more robust method. Faced with the problems of circuit complexity (e.g., needing separate detectors for high/low stopped states in JP2000224015A) and slow response times (e.g., due to capacitor discharge in FIG. 2 of the '531 patent), a PHOSITA would readily recognize that monitoring the inherent through current in a simple CMOS inverter-like structure (p-type and n-type transistors in series, with gates connected to the input signal) offers an elegant solution. The presence of through current unambiguously indicates signal transitions (the "first state" of repeatedly going high and low, as per Claim 2), while its sustained absence indicates a static signal (the "second state" of being kept at a high or low level). This method provides a unified detection mechanism that is insensitive to the static level of a stopped signal and responds quickly to signal cessation. Employing a standard current mirror circuit to reliably sense and convert this transient through current for further processing (e.g., voltage conversion and comparison, as in the '531 patent's FIG. 3) would be a routine and obvious design choice for a PHOSITA to implement such a detection scheme.

  Therefore, it would have been obvious for a PHOSITA to combine the recognized need for improved clock stoppage detection for power saving (taught by JP2000224015A) with the well-known characteristics of CMOS through current and standard current mirror techniques to achieve a more efficient, compact, and reliable signal detection and power consumption control system.

Combination 2: JP2003066071A or US6798372B1 in view of general knowledge of CMOS through current and current mirror circuits.

This combination primarily addresses the obviousness of independent Claims 4 and 9.

• JP2003066071A (Yokogawa Electric Corp) / US6798372B1 (Maxim Integrated Products, Inc.): These references, titled "Power frequency detection circuit" and "Switched-capacitor frequency-to-current converter" respectively, teach the general concept and need for circuits that detect the frequency of a signal.

• General Knowledge of CMOS Through Current: As discussed above, it is widely known in CMOS circuit design that the average magnitude of the through current in a CMOS inverter (p-type and n-type transistors in series, gates connected to input) is directly proportional to the switching frequency of the input signal. The more frequently the signal transitions, the more often the through current flows, leading to a higher average current over time. The '531 patent explicitly states this principle: "since the through current is almost proportional to the number of times of ON/OFF switching of the input signal, the frequency of the input signal can be detected based on the through current."

• General Knowledge of Current Mirror Circuits: As explained above, current mirror circuits are standard elements for sensing and processing currents in integrated circuits.

• Motivation for a PHOSITA to Combine: A PHOSITA tasked with designing a frequency detection circuit (as taught by JP2003066071A or US6798372B1) would consider various methods. Given the widely understood relationship between CMOS input signal frequency and the average through current generated in a simple CMOS inverter, it would be an obvious and straightforward design choice to utilize this phenomenon for frequency detection. By applying the signal whose frequency is to be detected to the gates of series-connected p-type and n-type transistors and measuring the resultant average through current (which can be smoothed using simple RC filtering, as exemplified by R1 and C1 in FIG. 3 of the '531 patent), the frequency can be directly determined. The use of a current mirror to accurately sense and replicate this through current for robust measurement would be a routine design implementation.

  Therefore, it would have been obvious for a PHOSITA to combine the known goal of frequency detection (taught by JP2003066071A or US6798372B1) with the widely understood proportionality between CMOS through current and switching frequency, augmented by standard current mirror techniques, to create a frequency detection circuit as described in the '531 patent.