US 7354790

I'll search for current information on this patent, including any 2026 litigation activity.

Let me check for litigation activity and current USPTO status.

Let me do one final targeted check for any litigation or 2026 docket activity.

Summary of US Patent 7,354,790 B2

Important caveat up front: I do not have direct credentialed access to USPTO PatentCenter or PACER/CAFC docket systems. What follows is drawn from the authoritative full text you supplied (Google Patents rendering of US7354790B2, fetched 2026‑09‑24) plus secondary web searches. I found no evidence of any 2026 CAFC docket or litigation involving patent 7,354,790 specifically, and I could not verify any such activity — treat that as a negative finding from limited searching, not a confirmed absence. I did not find results for similar-but-different numbers being substituted here.

Bibliographic data

Uncertainty notes on identifiers: The record contains two spelling inconsistencies I am preserving rather than correcting — the 2005 assignment document lists assignor "RANADA, YOGENDRA" while the Google Patents inventor field reads "Ranade, Yogendra"; and the abstract/summary refer to a "dicing saw" embodiment that does not appear as a granted independent claim. Current assignee listings are, per Google Patents' own disclaimer, not a legal conclusion.

Abstract (verbatim)

"A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw."

Note the abstract describes only steps (a)–(c); the granted independent claims add a fourth step (temporary metal structures placed in the saw street for wafer testing), so the abstract is narrower/looser than the claims.

Plain-language overview of the independent claims

Claim 1 — Method (the only independent method claim). A four-step method:

1. Provide a wafer on which multiple IC die will be formed;
2. Form those IC die on the wafer;
3. Form a saw street between the die in a way that relieves cutting stress when a dicing saw separates the die; and
4. Form temporary metal structures in the saw street for testing the wafer, positioned at locations chosen to avoid cutting stress from the dicing saw.

The inventive core is step (d): the same temporary metal features historically used as probe/test pads in the saw street are repositioned so the blade does not chew through them in a way that causes chipping.

Claim 9 — Product/wafer (the only independent apparatus/product claim). The structural mirror of claim 1: a wafer carrying multiple IC die; a saw street between the die that relieves cutting stress during dicing; and temporary metal structures formed in the saw street for wafer testing, located so as to avoid cutting stress from the dicing saw.

Dependent claims 2–8 (method) and 10–18 (wafer/product) elaborate on how the metal structures are positioned or formed, including:

• Structures lying completely outside the dicing saw's cut path (claims 2, 10);
• Structures lying completely inside the leading edges of the cut path, to keep cracks from propagating outward (claims 3, 11);
• No more than about 50% of the structures between the saw-street near side and the leading edges (claims 4, 12) — the dual-blade arrangement of FIG. 8, where leading blades cut <50% and a trailing blade "harvests" the rest;
• Patterning the structures to reduce metal density — described as striping/slotting/cross-hatching (claims 5–6, 13–14; note claim 6 wording is "striping slotting, and cross-hatching," while the specification describes longitudinal slotting, lateral slotting, or cross-hatching);
• A saw street at least about 80 microns wide (claim 7);
• Separating die with a dicing saw having leading edges leaving 0–50% of structure and a trailing edge harvesting the remainder (claim 8);
• Replacing a portion of the copper metal layer in the saw street with another conductive metal of higher absorption energy than copper (claims 15, 17), specifically aluminum (claims 16, 18). This is the FIG. 11 embodiment.

Claim-drafting observation: The specification's "Summary of the Invention" recites three embodiments (method, wafer, and dicing saw), but the granted claim set contains no independent dicing-saw claim — the blade geometry survives only as a dependent method limitation in claim 8. That is a meaningful scope gap in the issued patent relative to the disclosure.

Cited references of record

• Cited by examiner (5): US2002/0098623A1 (Akram); US2003/0082836A1 (Fetterman, stress-migration test structure); US2003/0162368A1 (Connell); US2006/0079024A1 (Akram); US7,087,452B2 (Intel, edge arrangements for IC chips).
• Cited by others (2): US2011/0006389A1 (LSI Corp., "Suppressing fractures in diced integrated circuits"); US10,056,339B2 (Samsung).

Litigation / 2026 docket check

Searches surfaced Bell Semiconductor's broader assertion campaigns (e.g., vs. NXP, Micron, Texas Instruments, MaxLinear, AMS/ams-OSRAM, and the Bell v. Broadcom assignment dispute), and a PTAB matter, IPR2024‑01010, listing inventors "Anand Govind, Zafer Kutlu, Farshad Ghahghahi" (Kutlu is a co-inventor here, consistent with Bell's portfolio-level assertion activity). However, I found no source tying US 7,354,790 itself to any asserted claim chart, IPR, ITC investigation, or 2026 CAFC appeal. Combined with the patent's listed expiration (adjusted expiration 2026‑03‑03), any enforcement window for this specific patent appears closed or effectively closing, but I state that as inference — not a verified legal-status conclusion.

I'll search for litigation involving US patent 7354790.

The first searches returned several "'479" patents that are not US 7,354,790 — I'll disregard those. Let me search more precisely.

Let me search more targeted sources.

Bottom line

I could not identify any litigation involving U.S. Patent No. 7,354,790 ("Method and apparatus for avoiding dicing chip-outs in integrated circuit die," LSI Logic Corp., now Bell Semiconductor LLC) in the sources I was able to search. If any such case exists, it is not surfaced in the public litigation records that my searches reached. I am flagging this as a negative finding based on limited searching, not as a certified "no litigation ever existed" conclusion — see the caveats below.

Important identifier warning (do not conflate these)

My searches repeatedly returned references to different patents that share a "479" shorthand, and none of them is US 7,354,790. These must not be attributed to your patent:

Per the operating rule to interpret identifiers literally: a reference to "the '479 patent" in those cases is not a reference to 7,354,790, and I have not treated it as one.

What the record does show for US 7,354,790

• Owner of record / current assignee: Bell Semiconductor, LLC (via Avago/Broadcom ← LSI Corporation ← LSI Logic Corp.).
• Status (per Google Patents / USPTO): Expired – Lifetime, with adjusted expiration 2026-03-03.
• No district-court or ITC case naming 7,354,790 appeared in my results.
• The only "forward" reference I saw tying 7,354,790 to anything was a later-published application citing it as prior art: US 2011/0006389 A1 (LSI Corporation, "Suppressing fractures in diced integrated circuits"). That is a citation, not litigation.

Context: Bell Semiconductor's assertion campaign (does not include 7,354,790 in what I found)

Bell Semiconductor has run a large, well-documented assertion campaign. The patents-in-suit I observed in those complaints/ITC actions were:

• U.S. 7,231,626 and U.S. 7,260,803 — ITC Inv. No. 337-TA-1340 (filed Oct. 6, 2022; instituted Nov. 7, 2022), respondents incl. NXP, Micron, NVIDIA, AMD, Acer, Infineon, Qualcomm/Motorola, Western Digital.
• U.S. 7,396,760 — ITC Inv. No. 337-TA-1349 (filed Oct. 14, 2022), respondents incl. Analog Devices, Bose, Marvell, Kioxia, MaxLinear, Skyworks, OmniVision, etc. Also asserted in Bell Semiconductor, LLC v. Western Digital Technologies, Inc., 8:22-cv-02083 (C.D. Cal.).
• U.S. 7,007,259 — ITC Inv. No. 337-TA-1319 (instituted June 13, 2022; terminated Aug. 30, 2022 on withdrawal); also Bell Semiconductor v. Lattice Semiconductor (D. Or., consolidated 3:22-cv-01282-MO et al.).
• U.S. 6,436,807 — Bell Semiconductor, LLC v. Western Digital Technologies, Inc., 8:22-cv-01127 (C.D. Cal.).

7,354,790 does not appear in any of these. Related Bell Semiconductor cases I saw (e.g., Bell Semiconductor v. MaxLinear, 3:22-cv-01178 (S.D. Cal.), dismissed Apr. 2023; Bell Semiconductor v. NXP USA, 3:22-cv-01794 (S.D. Cal.), dismissed Dec. 2023) likewise did not name it in the results I retrieved.

Caveats on the negative finding

1. Search coverage was incomplete. I could not reach the Unified Patents litigation caselist, Docket Navigator, or RPX/other aggregators directly within my search budget. My negative result rests on Google Patents' "Cited By" and litigation-adjacent search results plus secondary sources.
2. The Google Patents page for this patent lists no litigations and only two "Cited By" items, both patent documents (US 2011/0006389 A1; US 10,056,339 B2) — consistent with no asserted litigation.
3. Patent-term context: with the patent expiring 2026-03-03, any campaign would likely predate that.

Recommended verification steps (if you need a definitive answer)

• Unified Patents litigation portal: https://portal.unifiedpatents.com/litigation/caselist — search "7354790."
• CourtListener / RECAP: search the docket database for patent number 7354790.
• PACER (district courts) and USITC EDIS (https://edis.usitc.gov) for any Section 337 action.
• Docket Navigator (subscription) for a comprehensive assertion history.

If you can share results from any of those, I'll incorporate them. As of now, based on what I was able to retrieve, no litigation is known involving US 7,354,790.

I'll start by verifying the structured ODP result against public sources.

Let me run additional targeted checks to confirm the absence of proceedings and look for related litigation context.

PTAB Proceedings — US 7,354,790 B2

"Method and apparatus for avoiding dicing chip-outs in integrated circuit die" — LSI Logic Corp. (original assignee) → Bell Semiconductor, LLC (current assignee)

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Proceedings overview

Total PTAB AIA trial proceedings on file: 0 (zero). The USPTO Open Data Portal returns no IPR, PGR, or CBM proceeding naming US 7,354,790 as the challenged patent, and independent web searching of PTAB dockets/decision sets, RPX PTAB trackers, and CourtListener returns no petition, institution decision, or Final Written Decision directed at this patent. There is nothing to break down by status — no claims canceled, no claims sustained, no settlement, no institution denial — which leaves a defendant without an IPR-based invalidity record on this patent, but with two other levers that matter far more (see Strategic summary): the patent's term has run (adjusted expiration 2026-03-03, per the structured data, i.e., it expired before today's date of 2026-09-29), and Bell Semiconductor's enforcement campaign against this portfolio has historically settled rather than gone to an FWD.

Bottom-line defensive posture: No PTAB proceeding exists, so there is no canceled-claim victory to ride and no § 315(e)(2) estoppel to exploit — but also no adverse PTAB ruling to overcome. The patent is a terminal-stage assertion asset: expired as of 2026-03-03, so any live dispute is about past damages only, not injunctive or ongoing-royalty exposure.

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Per-proceeding detail

None. There are no proceedings to enumerate.

No AIA trial proceeding number, petitioner, judge panel, institution decision, or Final Written Decision is on file for US 7,354,790. I will not manufacture one. For completeness, the near-miss / adjacent activity that a defendant should not mistake for action on this patent:

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Strategic summary

Claim status: everything is UNTESTED. Because no petition was ever filed, all 18 claims — independent claim 1 (method) and claim 9 (wafer), plus dependent claims 2–8 and 10–18 — stand exactly as issued and never adjudicated by the PTAB. That is neither a "hardened" patent nor a "dead" one at the Board; it is a blank slate. Any invalidity challenge would have to be built from scratch, and now with a heavily truncated runway (see term status below).

Estoppel landscape — effectively none, and that cuts both ways. With no IPR/PGR, there is no § 315(e)(2) estoppel binding any defendant, and equally no prior petitioner's prior art to inherit. A current target is free to raise any § 102/§ 103 ground, in any forum, on any reference — including art that would have been barred by § 325(d) had an earlier petition been filed and lost. The flip side: because no one has run the IPR gauntlet, you get no free read on claim construction, no PTAB-tested obviousness combinations, and no opportunity to copy a winning petition. Expect the art of record — the five references cited on the face (US 2002/0098623 Akram; US 2003/0082836 Fetterman, Stress migration test structure; US 2003/0162368 Connell; US 7,087,452 Intel, Edge arrangements for integrated circuit chips; US 2006/0079024 Akram) plus the "metal reduction in wafer scribe area" family (e.g., US 6,951,801) — to be the starting point for a fresh § 103 attack.

Pattern signals. Bell Semiconductor (a Hilco-controlled monetization entity) is an active serial assertor across roughly 60+ district court cases and multiple ITC investigations, but its IPR record is one of settlement, not adjudication — IPR2024-01010 against the '245 patent terminated post-institution at the parties' request, and the 2021 TI settlement swept in a bundle of IPRs. No defensive aggregator (Unified Patents, RPX, etc.) has picked up this patent. Consequence: if you are newly accused, there is no pre-existing invalidity record you can lean on, and Bell's revealed preference is to resolve rather than defend claims on the merits at the Board.

Term status — the decisive fact. The structured data lists adjusted expiration 2026-03-03 and legal status "Expired – Lifetime." As of today (2026-09-29) the 20-year term plus PTA has run out. This is not a PTAB point, but it dominates the defensive posture: an expired patent cannot support prospective relief, and damages are confined to the § 286 six-year lookback on past acts. Verify the expiration against the face of the patent and the PTO maintenance/term records before relying on it, since term and PTA are exactly the kind of data that can be mis-transcribed.

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Recommended next steps

• If you have received a demand or been sued on '790: treat the clock as your primary asset. Confirm the adjusted expiration date (2026-03-03) directly from the USPTO Patent Center term record and the printed patent's PTA notice, then move to cabin the case to pre-expiration, lookback-limited past damages and press for an early case-dispositive posture on scope/non-infringement.
• On invalidity: there is no FWD to link, because none exists. Build any § 103 challenge on the cited art (Akram '623/'024, Fetterman '836, Connell '368, Intel '452) and the scribe-line metal-reduction family, and consider whether an IPR is even rational given the 1-year statutory trial deadline now falls months after expiration — a petition filed today could not mature into an FWD before the term ends, which materially weakens the practical value of an IPR as a defense and strengthens the case for forum-based (district court/ITC) invalidity and non-infringement defenses.
• If you are evaluating the portfolio broadly: note that the asserted Bell patents with actual PTAB history are '245 (IPR2024-01010, settled), '626 and '803 (ITC 337-TA-1340/1342), and the EDA-facing '259/'807/'760/'626/'803/'989 set targeted in the Synopsys/Cadence and Siemens declaratory-judgment actions — '790 is not among them. Do not assume IPR outcomes on those patents transfer to '790; they do not.
• Standing rule: because "no PTAB activity" is a negative finding, re-check before relying on it. If a petition against '790 is filed after the ODP ingest date, it would be assignable to the IPR2026-xxxxx series and would flip this analysis — but as of this writing no such proceeding is on file, and the looming expiration makes a new petition unlikely to produce an FWD.

Sources: USPTO Open Data Portal "PTAB proceedings on file" (canonical, returns none); Google Patents US7354790B2 (https://patents.google.com/patent/US7354790/en) for claims, cited art, assignments, and term/status; RPX PTAB tracker and CourtListener docket for IPR2024-01010 and the Bell Semiconductor litigation campaign. No PTAB decision or Federal Circuit opinion on US 7,354,790 was located, because none appears to exist.

Assignment Record Reconstruction — US 7,354,790 B2

Data provenance note (read first): The authoritative source supplied to me is the Google Patents full-text record for US 7,354,790, which reproduces the USPTO "Legal Events" table including reel/frame identifiers for each recorded assignment. I was not able to retrieve the Assignment Center record pages themselves in this session, and critically, the Google Patents legal-events export does not include the correspondent (attorney/firm of record) field. Every correspondent statement below is therefore flagged as unverified rather than filled in. Reel/frame numbers, dates, assignors and assignees below are taken verbatim from the recorded legal events and are not inferred.

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Inventors

Eight named inventors, all of whom executed the original assignment to LSI Logic Corporation on 2005-05-04 / 2005-05-05 (reel 016589/0039, per the recorded assignment's "SIGNING DATES FROM 20050504 TO 20050505"):

Name-discrepancy flag (literal reading): the recorded assignment lists assignor "RANADA, YOGENDRA" while the patent names "Yogendra Ranade." Per the operating rule to interpret identifiers literally, I record the assignment spelling as written and note the apparent typographical variance rather than silently correcting it; it is almost certainly the same person (same first name, same reel, same transaction).

Unusual patterns: none that I can substantiate. I found no evidence of inventors departing LSI Logic within 12 months of the 2005-01-19 priority date. Searching for inventor departure records was not productive (these are engineers, not executives, at a large public company), so this is unverified rather than a negative finding. The only notable structural feature is the size of the inventor group (8) for a single-process patent, typical of a fab process-development team.

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Original assignee

LSI Logic Corporation (Milpitas, CA) — named as assignee on the face of the issued patent and on reel 016589/0039.

• Line of business: operating semiconductor manufacturer (ASICs, storage/HDD controllers, custom silicon); a real fabs-and-products company, not an IP holding vehicle.
• Product embodying the claims: Presumed, not documented. The claims (claims 1–18) are directed to a wafer-manufacturing method — forming a saw street between die to relieve dicing cutting stress, arranging test probe pads relative to the saw path, patterning pads to lower metal density, and substituting aluminum for copper in the saw street. A company that diced its own wafers in 2005 would necessarily have practiced the process, but I found no documentary evidence of a specific LSI Logic product or process explicitly embodying these claims. Treat this as an inference from business type, not a finding.
• Current status: no longer exists as such. LSI Logic acquired Agere Systems in 2007 and renamed itself LSI Corporation (change of name recorded 2014-06-06, effective 2007-04-06, reel 033102/0270). LSI Corporation was acquired by Avago Technologies on 2014-05-06 (confirmed by the SDNY opinion in Bell Semiconductor, LLC v. Broadcom Corp.), whose Singapore IP unit took the patent by assignment (reel 035390/0388). Avago then acquired Broadcom in 2016 and renamed itself Broadcom. The original assignee was absorbed through acquisition, not dissolved or bankrupt.

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Assignment timeline

All ten recorded events below are from the patent's USPTO legal-events record. Correspondent fields are not available in the source record and are marked accordingly.

1. 2005-05-04/05 (executed) / recorded 2005-05-18 — Reel 016589/0039

   • Conveyance: Assignment
   • Assignor: RAJAGOPALAN, PARTHASARATHY; KUTLU, ZAFER; SUGASAWARA, EMERY O.; VONDERACH, CHARLES E.; VIJAY, DILIP P.; RANADA, YOGENDRA; HALL, JEFF; MANNING, DWIGHT
   • Assignee: LSI Logic Corporation (California)
   • Correspondent: Not in the source record — unverified. Would require Assignment Center lookup of reel 016589/0039.
   • Context: Original inventor-to-company assignment; standard employment-obligation transfer at filing.

2. 2014-05-08 recorded (effective 2014-05-06) — Reel 032856/0031

   • Conveyance: Patent Security Agreement (security interest, not a title transfer)
   • Assignor: LSI Corporation; Agere Systems LLC
   • Assignee: Deutsche Bank AG New York Branch, as Collateral Agent
   • Correspondent: Not in the source record — unverified.
   • Context: Securitization — portfolio pledged as collateral in connection with Avago's acquisition financing of LSI.

3. 2014-06-06 recorded (effective 2007-04-06) — Reel 033102/0270

   • Conveyance: Change of Name
   • Assignor: LSI Logic Corporation
   • Assignee: LSI Corporation
   • Correspondent: Not in the source record — unverified.
   • Context: Change of name only — internal reorg; no change in beneficial ownership.

4. 2015-04-03 recorded (effective 2014-08-14) — Reel 035390/0388

   • Conveyance: Assignment (of assignor's interest)
   • Assignor: LSI Corporation
   • Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
   • Correspondent: Not in the source record — unverified.
   • Context: Acquisition-integration step — transfer of LSI titles into Avago's Singapore IP-holding subsidiary following the May 2014 closing.

5. 2016-02-02 recorded (effective 2016-02-01) — Reel 037684/0039

   • Conveyance: Termination and Release of Security Interest (releases RF 032856-0031)
   • Assignor: Deutsche Bank AG New York Branch, as Collateral Agent
   • Assignee: LSI Corporation; Agere Systems LLC
   • Correspondent: Not in the source record — unverified.
   • Context: Securitization release — collateral freed on refinancing.

6. 2016-02-11 recorded (effective 2016-02-01) — Reel 037808/0001

   • Conveyance: Patent Security Agreement
   • Assignor: Avago Technologies General IP (Singapore) Pte. Ltd.
   • Assignee: Bank of America, N.A., as Collateral Agent
   • Correspondent: Not in the source record — unverified.
   • Context: Securitization — the free-and-clear asset immediately re-pledged under a new credit facility. The 4-day gap between release (reel 037684/0039) and re-pledge (reel 037808/0001) is the classic collateral-substitution pattern.

7. 2017-02-03 recorded (effective 2017-01-19) — Reel 041710/0001

   • Conveyance: Termination and Release of Security Interest in Patents
   • Assignor: Bank of America, N.A., as Collateral Agent
   • Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
   • Correspondent: Not in the source record — unverified.
   • Context: Securitization release — the portfolio is freed immediately before the divestiture to Hilco/Bell.

8. 2017-12-17 recorded (effective 2017-12-08) — Reel 044886/0766 ← the pivotal record

   • Conveyance: Assignment of interest
   • Assignor: Avago Technologies General IP (Singapore) Pte. Ltd.; Broadcom Corporation
   • Assignee: Bell Semiconductor, LLC (Illinois)
   • Correspondent: Not in the source record — unverified. If the Assignment Center shows a single recurring attorney or firm on this reel and on reels 045216/0020 / 059723/0382, that is the repeat-correspondent signal; I could not confirm it.
   • Context: Transfer-to-asserter / divestiture of a patent-monetization portfolio. Thousands of assets were conveyed in the same transaction (RPX: patents "picked up from Broadcom in December 2017"; the underlying written assignment agreement is dated 2017-11-30 and was litigated in Bell Semiconductor, LLC v. Broadcom Corp., SDNY, where Bell alleged the portfolio was misrepresented). The counterparties Hilco Patent Acquisition 56 LLC and Bell Northern Research LLC appear on the same collateral document (reel 045216/0020) and on Bell's own PTAB notices as parents/sisters.

9. 2018-02-01 recorded (effective 2018-01-24) — Reel 045216/0020

   • Conveyance: Security Interest (Security Agreement)
   • Assignor: Hilco Patent Acquisition 56, LLC; Bell Semiconductor, LLC; Bell Northern Research, LLC
   • Assignee: Cortland Capital Market Services LLC, as Collateral Agent
   • Correspondent: Not in the source record — unverified.
   • Context: Securitization — >3,700 assets pledged by the Hilco acquirer entities within ~6 weeks of the reel 044886/0766 assignment, consistent with debt-financed acquisition of the portfolio.

10. 2022-04-15 recorded (effective 2022-04-01) — Reel 059723/0382

    • Conveyance: Release by Secured Party / Release of Security Interest
    • Assignor: Cortland Capital Market Services LLC
    • Assignee: Bell Semiconductor, LLC; Bell Northern Research, LLC; Hilco Patent Acquisition 56, LLC
    • Correspondent: Not in the source record — unverified.
    • Context: Securitization release — encumbrance lifted; title remains with Bell Semiconductor, LLC.

Non-assignment legal events (for completeness, no ownership effect): maintenance-fee payments 2011-09-23 (4th yr), 2015-09-29 (8th yr), 2019-09-23 (12th yr, M1553); status "Expired – Lifetime"; adjusted expiration 2026-03-03 (post-PTA; 20-year term from the 2005-05-18 filing date). Given today's date (2026-09-29), this patent expired roughly seven months ago — any assertion value is now historic.

Ownership bottom line: the chain does not terminate at an operating company and does not terminate at a defensive aggregator. Current owner: Bell Semiconductor, LLC (per reel 044886/0766, unencumbered since reel 059723/0382).

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Timeline diagram

timeline
    title Ownership of US 7354790
    2005 : Inventors assign to LSI Logic
    2008 : Patent issues Apr 8
    2014 : Name change to LSI Corporation
         : Avago acquires LSI
         : Deutsche Bank security interest
    2015 : Assigned to Avago Singapore IP unit
    2016 : Deutsche Bank interest released
         : Bank of America security interest
    2017 : Bank of America interest released
         : Portfolio sold to Bell Semiconductor
    2018 : Cortland security interest
    2022 : Cortland interest released
    2026 : Patent expires Mar 3

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NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Reel 044886/0766 (recorded 2017-12-17, effective 2017-12-08) moved the patent from operating companies (Avago/Broadcom) to Bell Semiconductor, LLC, a licensing-only entity. Corroboration is documentary, not name-based: Bell's own PTAB mandatory notices state "Bell Semiconductor, LLC is a wholly owned subsidiary of Hilco Patent Acquisition 56, LLC, which is owned by Hilco IP Merchant Capital, LLC, Hilco, Inc., Vulcan Ventures Inc., CDPQ Investments (U.S.) Inc., and KLIM AIV, LP" (e.g., IPR2021-00191; IPR2024-01010). Siemens' Delaware declaratory-judgment complaint pleads that "BSLLC neither makes products nor invests in research & development. BSLLC's business is litigation." Bell describes itself in its complaints as "a technology and intellectual property licensing company."

2. Known asserter in the chain — PRESENT.
Bell Semiconductor, LLC is the current owner and a documented high-frequency plaintiff, though it is not on the classic named list (Acacia, Marathon, IV, Wi-LAN, etc.). This falls squarely under "any entity surfaced by Unified Patents or RPX as a high-frequency plaintiff": RPX reported Bell Semic's campaigns from November 2019 onward (IDT, 1:19-cv-02155; Renesas, 6:19-cv-02196), then a 2022 wave against AMD, Analog Devices, Infineon, KIOXIA, Marvell, Micron, NVIDIA, NXP, Qualcomm and Socionext plus ITC 337-TA-1319 and 337-TA-1342; Siemens' complaint counts "at least eighteen… Customers in at least 66 cases." Note: I could not verify that US 7,354,790 specifically was ever asserted — it does not appear in the asserted-patent sets reported by RPX, and the visible campaigns target dummy-fill, design-rule and routing patents, not saw-street/dicing patents.

3. Repeat correspondent across the chain — UNCLEAR.
The Assignment Center correspondent fields were not available in the source record for any of the ten reels, so I cannot state whether a single attorney or firm recorded reels 016589/0039, 035390/0388, 044886/0766, 045216/0020 or 059723/0382. Do not treat this as a negative finding — it is a gap. Two adjacent, weaker observations: (a) reels 044886/0766, 045216/0020 and 059723/0382 all involve overlapping Hilco-family assignors/assignees, i.e. the same acquisition family on three records; (b) the litigation record shows a stable firm of record — Skiermont Derby LLP (Steven W. Hartsell, Reg. No. 58,788; Charles C. Koole; Tara M. Williams; Alexander E. Gasser), Dallas/Los Angeles — as Bell Semiconductor's lead PTAB counsel. That is litigation counsel, not assignment correspondent, and I flag it as such rather than conflating the two.

4. Cascading transfers — PRESENT (moderate).
Reel 044886/0766 (recorded 2017-12-17) is followed within ~6 weeks by reel 045216/0020 (recorded 2018-02-01), on which Bell Semiconductor, LLC, Bell Northern Research, LLC and Hilco Patent Acquisition 56, LLC are joint assignors to a common collateral agent — i.e. chained LLCs sharing a single corporate parent (Hilco IP Merchant Capital / Hilco, Inc.) and a common recorded instrument. The 2015–2017 security-interest cycle (reels 035390/0388 → 032856/0031 / 037684/0039 → 037808/0001 → 041710/0001) shows four recorded transactions in ~34 months across the same asset.

5. Pre-litigation transfer — NOT PRESENT as to the documented suits.
The assignment took effect 2017-12-08; Bell Semic's first reported assertions on this portfolio came in November 2019, a ~23-month gap, outside the 6-month window. Because I could not confirm whether the '790 patent itself was asserted at some later point, I leave open the possibility of a later, closer assertion-to-transfer timing — but on the evidence retrieved, the trigger is not met.

6. Bankruptcy fire-sale — NOT PRESENT.
No bankruptcy of LSI Logic, LSI Corporation, Agere, Avago or Broadcom appears in the chain; the 2017 divestiture was a negotiated sale under a written assignment agreement dated 2017-11-30. (Bell's SDNY suit alleges misrepresentation and breach of warranty in that sale — a dispute about the deal, not an insolvency proceeding.)

7. Privateering — PRESENT (moderate).
Broadcom/Avago sold the portfolio to Hilco affiliates and retained a licensee/domestic-industry role: in ITC Inv. No. 337-TA-1319 Bell Semic pleaded satisfaction of the domestic-industry requirement "through the activities of its licensee, Broadcom" (charted against a Broadcom SAS3908A0-2 controller). That is the recognizable structure of an operating company exiting patent enforcement while an affiliate monetizes the same assets against industry competitors — Bell then sued Broadcom's competitors (NXP, Microchip, TI, Qualcomm, Micron, NVIDIA).

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain terminates at Bell Semiconductor, LLC (reel 044886/0766), an asserting Hilco affiliate. There is no RPX, AST, LOT Network, Unified Patents or OIN link anywhere in the recorded chain.

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Verdict

NPE — high confidence.

The chain moves from an operating manufacturer of record (LSI Logic/LSI Corporation, reel 016589/0039; reel 035390/0388) to a Hilco-controlled assertion vehicle: reel 044886/0766 (recorded 2017-12-17, effective 2017-12-08) transferred the asset from Avago/Broadcom to Bell Semiconductor, LLC, which its own PTAB mandatory notices identify as a wholly owned subsidiary of Hilco Patent Acquisition 56, LLC — and which Bell's litigation adversary describes, without contradiction, as making no products and doing no R&D. Bell Semiconductor then ran a documented multi-front assertion campaign from November 2019 across 60+ district court cases and three ITC investigations, while reels 045216/0020 (2018-02-01) and 059723/0382 (2022-04-15) show the portfolio being debt-financed and then released to the same Hilco-family LLCs. Two strong signals are met (shell-entity transfer; known high-frequency asserter), with privateering and cascading-transfer patterns present as supporting evidence. Caveats: the correspondent field could not be verified for any reel, and I could not confirm that this particular patent was asserted — it may be a portfolio filler, and it expired 2026-03-03, so the NPE characterization is about the chain of title rather than about proven litigation over the '790 claims.

Verification links: USPTO Assignment Center search — https://assignmentcenter.uspto.gov/ ; legacy assignment search — https://assignment.uspto.gov/patent/index.html (search "7354790"); patent record — https://patents.google.com/patent/US7354790/en.

I'll start by verifying the patent record and then examine each cited reference.

Let me research each cited reference individually.

Prior-Art Analysis — US 7,354,790 B2

Note on method: I was able to retrieve the full patent text (Google Patents, fetched 2026-09-24), the examiner-cited reference list, and bibliographic/content details for four of the five cited references. My retrieval of full text for US 2006/0079024 A1 (Akram) was cut off by a tool-step limit, so my treatment of that reference is based on its title, dates, and the classification data in the patent record — I flag this explicitly below rather than guessing at its disclosure.

1. The patent under analysis

Claim skeleton (for the §102 mapping below):

• Claim 1 (independent, method): (a) provide wafer; (b) form IC die; (c) form a saw street to relieve cutting stress when die are separated by a dicing saw; and (d) form temporary metal structures in the saw street for testing the wafer, the metal structures formed at locations in the saw street selected to avoid cutting stress from the dicing saw.
• Claims 2–8 (dependent): metal structures completely outside the cut path (2); completely inside the leading edges to prevent crack propagation (3); ≤ ~50% between saw-street near side and each leading edge (4); patterned to reduce metal density (5); striping/slotting/cross-hatching (6); saw street ≥ ~80 µm (7); dicing saw with leading edges leaving 0–50% and trailing edge that harvests (8); plus Cu→higher-absorption-metal replacement (15, 16).
• Claim 9 (independent, wafer): die on wafer + saw street to relieve cutting stress + temporary metal structures in the saw street at selected locations to avoid cutting stress. Claims 10–14, 17, 18 mirror the method dependents.

Key point for §102: the independent claims require both (i) a saw street that relieves dicing cutting stress and (ii) temporary wafer-testing metal structures placed in that street at locations selected to avoid cutting stress. A reference must disclose both to anticipate.

2. Examiner-cited references (Patent Citations, 5 total)

All five pre-date the '790 patent's 2005-01-19 priority date except reference E, which published after that date (2006-04-13) and is therefore available only as §102(e) art as of its 2004-03-10 filing date.

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3. Reference-by-reference analysis

A. US 2002/0098623 A1 — Akram (Micron) — "Semiconductor device including leads in communication with contact pads thereof and a stereolithographically fabricated package substantially encapsulating the leads…"

• Dates: Priority 2000-08-31; published 2002-07-25. §102(b)/102(a) art. (Corresponding grant: US 6,794,224 B2.)
• Subject matter: Chip-scale packaging. A stereolithographic process forms a protective polymer layer over the active surface of a die/wafer with bond pads or leads exposed through the layer; the disclosure addresses wafer-level packaging and later singulation of the wafer into individual dice.
• §102 assessment: No anticipation of any claim. The reference concerns forming protective/package layers and exposing bond pads; it does not disclose (i) a saw street dimensioned or configured to relieve dicing cutting stress, nor (ii) temporary metal structures positioned in the saw street at stress-avoiding locations. It is, at most, general background on wafer-level packaging and singulation. Its mention of waft singulation touches claim 1's environment, not its elements.

B. US 2003/0082836 A1 — Fetterman — "Stress migration test structure and method therefor"

• Dates: Filed 2001-10-31; published 2003-05-01. §102(b)/102(a) art.

• Subject matter (most textually relevant of the five): A metal test structure (a conductive runner with taps at impedance intervals) placed in the street between die areas on a wafer, or on the die, to detect stress-migration voids. Its own claim 1 expressly reads: "at least two die areas formed on the wafer, the at least two die areas defining a street therebetween; and a stress migration test structure in the street…" It also discloses placing test structures between bond pads and die periphery and on multiple metal levels.

• §102 assessment: This is the closest reference for the concept of putting metal structures in the die-separation street for a test purpose, which overlaps with claim 1 step (d) and with claim 9's "metal structures formed in the saw street for testing the wafer." However, it does not anticipate claim 1 or claim 9, because it fails the two limitations that distinguish them:

  1. It does not teach that the saw street is formed to relieve cutting stress during dicing (its purpose is electrical/mechanical stress-migration detection, not dicing-stress relief).
  2. It does not teach that the in-street test structures are placed "at locations… selected to avoid cutting stress from the dicing saw" (outside the kerf, inside the leading edges, ≤50%, patterned to reduce metal density, etc.).

  It is best characterized as §103 combination art with reference D (B + D supplies "arrange in-street metal relative to the cut path") or as evidence of the general practice of placing test structures in streets.

• Potentially relevant claims if combined: 1, 2, 3, 4, 9, 10, 11, 12 — as a secondary reference, not an anticipatory one.

C. US 2003/0162368 A1 — Connell — "Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive"

• Dates: Filed 2002-02-25; published 2003-08-28. §102(b)/102(a) art.
• Subject matter: Applying a back-side coating to balance thin-film (passivation) stress on the front of a wafer and also serve as die-attach adhesive. Concerns wafer-level stress management and die integrity.
• §102 assessment: No anticipation. It addresses film stress balance and die attach, not saw-street geometry, not temporary test metal placement, and not dicing-stress relief by saw-street design. At most it is peripheral background on managing wafer/die stress. It does not disclose any element of claims 1–18 in the required combination.

D. US 7,087,452 B2 — Intel Corp. — "Edge arrangements for integrated circuit chips" (pub. US 2004/0212047 A1)

• Dates: Filed 2003-04-22; granted 2006-08-08 (published as US 2004/0212047 A1 on 2004-10-28). §102(b)/102(a) art as to the '790 priority date.
• Subject matter: Edge/cutting-path arrangements around IC chips in a dual-damascene Cu interconnect stack. It discloses designing and patterning the metal and dielectric structures within the die-separation (laser) cutting path based on the cutting energy/material interaction — e.g., using a large volume fraction of laser-absorbing material, arranging metal structures in the cut path, metal walls, air gaps, guard/seal structures, and a flow of "form active areas → define metal walls → define air gaps → separate by cutting."
• §102 assessment: Strongly relevant to the "pattern/arrange in-street metal relative to the cutting path" concepts of claims 1, 5, 6, 9, 13, 14, but not anticipatory. Grounds for non-anticipation:
  • The Intel reference optimizes laser-cutting absorption ("to obtain a clean, defect-free cut"), not the placement of temporary wafer-probe test metal structures at locations chosen to avoid cutting stress from a dicing saw; its structures are typically permanent interconnect/guard features.
  • It does not disclose temporary metal structures for testing the wafer (probe pads) as required by claim 1(d)/claim 9, nor the specific placement metrics of claims 3, 4, 11, 12, nor the multi-blade saw of claim 8.
  • It is §102 art only for the broad notion of structuring the cutting path; the additional claim elements keep it in §103 territory.
• Most relevant claims as secondary art: 1, 5, 6, 9, 13, 14 (patterning/arrangement of in-street metal relative to the cut).

E. US 2006/0079024 A1 — Akram (Micron) — "Methods relating to singulating semiconductor wafers and wafer scale assemblies"

• Dates: Filed 2004-03-10; published 2006-04-13. Because publication post-dates the '790 priority date (2005-01-19), it is available only as §102(e) prior art as of its 2004-03-10 filing date, and only for subject matter actually disclosed as of that date.
• Subject matter: Per the title and the record, methods relating to singulating (dicing) semiconductor wafers and wafer-scale assemblies — i.e., general dicing/singulation of wafers into die.
• §102 assessment (with disclosed caveat): Based on the title/classification (I could not pull the full specification before the retrieval limit), this reference appears directed to wafer singulation methods and wafer-scale assembly, which parallels the dicing environment of claim 1 and claim 9 but does not appear to disclose the distinguishing combination — a saw street configured to relieve dicing cutting stress plus temporary wafer-testing metal structures placed in the saw street at stress-avoiding locations, nor the Cu→Al saw-street replacement of claims 15–18. I do not have enough verified text to assert anticipation, and I will not do so. I recommend verifying its disclosure before relying on it; on the record available it is background/§103-type art at best.
• Caveat: This analysis is provisional pending direct review of the US 2006/0079024 A1 specification.

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4. Summary conclusions

Bottom line: None of the five examiner-cited references, on the record I could verify, discloses the full combination required by independent claim 1 or independent claim 9. The two most relevant are Fetterman (B) — for the idea of placing a metal test structure in the die-separation street — and Intel (D) — for arranging/designing metal relative to the cutting path. Their combination (B + D) is the most plausible §103 challenge to claims 1–4 and 9–12, but each individually falls short of §102 anticipation because neither teaches temporary wafer-probing metal structures placed at locations selected to avoid cutting stress from a dicing saw in a stress-relieving saw street. References A and C are peripheral background only. I have deliberately not asserted a §102 mapping for reference E because I could not verify its specification text within the tool budget.

Verification note: This analysis is grounded in the USPTO/Google Patents record for US 7,354,790 B2 (https://patents.google.com/patent/US7354790/en) and the cited documents' own records (e.g., US 2003/0082836 at https://patents.google.com/patent/US20030082836; US 7,087,452 at https://uspto.report/patent/grant/[7,087,452](/patent/7087452)). Dates for reference E should be confirmed against the USPTO PatentCenter record, and its full text reviewed before any anticipation position is taken.

I'll ground this analysis in the prior-art references listed on the patent page. Let me pull details on the cited references.

Let me gather details on the remaining cited references and the closely-related scribe-line references.

Let me verify the remaining cited reference (US20020098623A1) so the roster is complete.

Obviousness Analysis — US 7,354,790 B2 under 35 U.S.C. § 103

Patent under analysis: US 7,354,790 B2, "Method and apparatus for avoiding dicing chip-outs in integrated circuit die" (LSI Logic Corp.; priority 2005‑01‑19; filed 2005‑05‑18; granted 2008‑04‑08; now expired).
Source of record: https://patents.google.com/patent/US7354790/en (including the "Patent Citations (5)" and "Similar Documents" lists on that page).
Analysis date: 2026‑04‑26.

Scope note on sources. I retrieved and relied on the full text/claims of four of the five examiner citations and of one closely related document that appears in the "Similar Documents" section of the same page. I did not retrieve the full text of US 2002/0098623 A1 (Akram) and therefore treat it as tangential and do not build a primary combination on it. Where I have less than high confidence in a specific reference's disclosure, I say so explicitly rather than asserting it.

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1. Governing law and the level of ordinary skill

This application has a priority date of 2005‑01‑19 and an actual filing date of 2005‑05‑18, so pre‑AIA § 103(a) governs ("at the time the invention was made") and the pre‑AIA §§ 102(a)/(b)/(e) prior‑art categories apply. The controlling framework is Graham v. John Deere Co., 383 U.S. 1 (1966), as elaborated by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). Under KSR, a claim is obvious where the differences between the claim and the prior art are such that the subject matter as a whole would have been obvious, including where the combination is "the predictable use of prior art elements according to their established functions" (KSR, 550 U.S. at 417), where a known technique is applied to a known device ready for improvement (id. at 417), or where the design need is known and there is a finite number of identified, predictable solutions (id. at 421). MPEP § 2143 lists the rationales usable here: (A) combining prior art elements per known methods to yield predictable results; (B) simple substitution of one known element for another; (C) use of known technique to improve similar devices in the same way; (D) applying a known technique to a known device ready for improvement; (F) obvious to try; (G) design incentives/market forces.

PHOSITA. A person of ordinary skill in the art at the 2005 priority date would be a process/integration engineer with a B.S. (or M.S.) in electrical engineering, materials science, or physics plus roughly 2–5 years of hands‑on experience in wafer fabrication, back‑end/assembly, and wafer singulation (blade dicing, low‑k/Cu integration, scribe-line design rules, and wafer‑level probe testing). Such a person would be familiar with: scribe/saw street design rules; probe/test pad structures built in the streets; blade loading and chipping when a blade cuts copper; and the difference in mechanical behavior between Cu and Al under dicing.

Importantly, all of the cited references are analogous art — every one is directed to semiconductor wafer fabrication, singulation, or wafer/die-level structure. There is no field-of-endeavor obstacle to combining them.

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2. Prior‑art roster and § 102 status

That US 2006/0079024 A1 is a § 102(e) reference keyed to its 2004‑03‑10 filing date, not its 2006 publication date, is important: the reference is available notwithstanding that its face publication post‑dates the patent's priority date.

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3. What each reference teaches (with support)

US 2003/0082836 A1 (Fetterman) — test structures placed in the street.

• Claim 1 is expressly drawn to an article of manufacture comprising the wafer itself: "at least two die areas formed on the wafer, the at least two die areas defining a street therebetween; and a stress migration test structure in the street" (see https://patents.google.com/patent/US20030082836 and https://patents.justia.com/patent/20030082836).
• The stress‑migration test structure is a metal runner — "a thin film metal resistor of aluminum on a silicon substrate" — fabricated in the street between die areas (the reference also contemplates placement "between die areas on a wafer").
• Stated rationale: testing at wafer level without consuming die area.
• Relevance: discloses "temporary metal structures … in the saw street for testing the wafer" (claim 1(d) / claim 9) — literally metal, literally in the street between die, literally a test structure.

US 2006/0079024 A1 (Akram) — structures in streets + cut narrower than the street.

• Background expressly recognizes that "test elements for use in probe testing of wafers may be placed in the areas within the streets to conserve wafer space (or 'real estate')" (see https://www.patents-review.com/a/20060079024-methods-relating-singulating-semiconductor-wafers-wafer.html).
• Background also recites the problem this patent addresses: conventional dicing "can lead to cracking of the material layers, smearing and tearing of metallic pads, formation of polymer slivers, and shredding and tearing of the semiconductor material," and that "the streets must be of sufficient width to allow any such anticipated damage … to remain clear of the functional integrated circuit elements."
• Disclosure: forming channels/trenches in the wafer aligned with the streets, disposing protective material in the channels, then singulating with a laser "having a beam width narrower than a width of the at least one channel to leave portions of the protective layer … covering sidewalls of the at least one channel after cutting through … is complete."
• Relevance: the cut path is deliberately narrower than the street, so structures/materials at the street margins survive the cut — i.e., material on the wafer is positioned outside the kerf by design. Also recites the prior art beveled‑blade partial cut followed by a narrower second cut within the partial cut.

US 7,087,452 B2 / US 2004/0212047 A1 (Intel) — designing what metal sits in the cutting path.

• Describes an interconnect stack with a designed "cutting path" at the chip edge and states that "During the design phase, the appropriate metal and dielectric materials may be provided within the laser cut path based on the type of laser and the type of material to be used" and that the cutting path "may be customized based on the laser and dielectric and interconnect materials so as to optimize the path"; this "may help avoid non‑uniform absorption of the laser" (see https://patents.google.com/patent/US20040212047A1/en).
• Expressly teaches either including or omitting metal from the cut path depending on cutting behavior: "the cutting path may include primarily metal structures (e.g., FIG. 26), and vice versa. For a wavelength(s) that is absorbed by the dielectric materials but not by the metallic materials, the cutting path may primarily include the dielectric materials without any metal patterns (e.g., FIG. 27)."
• Also teaches the volume fraction of materials in the cut path as a design variable, and that "The shapes and sizes of the patterns within the laser cutting paths are merely exemplary as other shapes and sizes are also within the scope."
• Relevance: direct teaching that (i) the presence/absence and (ii) the pattern/density of metal relative to the cut path are deliberate, optimizable design variables chosen to obtain a clean, defect‑free cut, and that metal may be excluded from the cut path or confined within it.

US 6,951,801 B2 / US 2004/0147097 A1 (Motorola/Freescale) — removing/reducing metal in the saw path.

• "Conductive structures 112 which are made of copper in one embodiment, are located in saw path 111. These conductive structures are utilized for testing and alignment guides during manufacture but typically are not electrically coupled to the devices …"; "the copper of these conductive structures … may build up on the saw blade thereby causing problems during singulation. … portions of the metal in the saw path 111 are removed to reduce the metal buildup on a saw blade" (https://www.freepatentsonline.com/[6951801](/patent/6951801).html).
• Stated objective: "reducing the amount of copper or other metals in the saw path to prevent the accumulation of metal on a saw blade … so as to reduce cracking, chipping, or other damage to the wafer" (https://patents.google.com/patent/[US6951801B2](/patent/US6951801B2)).
• Dimension disclosure: "Scribe area 1004 has a width of 1023 which in one embodiment is 100 microns. Saw path 1010 has a width of 1021, which in one embodiment is 50‑55 microns"; and "the scribe area width of a wire bond wafer can be 80 µm."
• Material disclosure: "the conductive structures of the scribe area may be made of other types of metal such as gold, silver, or aluminum."
• Relevance (multiple claims): (a) test structures in the saw path; (b) the explicit causal link between metal in the saw path and cracking/chipping damage; (c) metal reduction/removal as the remedy; (d) an 80 µm scribe width; (e) aluminum as an alternative scribe‑area metal.

US 2003/0162368 A1 (Connell) — stress balancing in wafers.

• Discloses applying a stress‑balancing layer (SBL) on the back side to balance front‑side passivation stress and "prevent dice warp," with singulation after thinning (https://patents.google.com/patent/US20030162368A1/en).
• Assessment: this reference addresses thin‑film/passivation stress and die warp, not cutting stress during dicing. Its correlation to the claimed "relieve cutting stress" is weak. I would use it only as cumulative evidence that stress management in wafer processing was well known, and I would not build a primary combination on it. Presenting it as the primary reference would be vulnerable to attack.

US 2002/0098623 A1 (Akram). Titled to a semiconductor device with leads in communication with contact pads and a stereolithographically fabricated package. Based on the title/classification and its role as a cumulative citation, it appears directed to packaging/lead formation rather than to saw‑street design or dicing. I did not retrieve its text; I would not rely on it in a rejection.

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4. The claims, and where the art lands on each

Independent claim 1 (method): (a) provide a wafer; (b) form die on it; (c) form a saw street between the die "to relieve cutting stress … when the integrated circuit die are separated by a dicing saw"; (d) form temporary metal structures in the saw street for testing the wafer, the metal structures formed at locations in the saw street selected to avoid cutting stress from the dicing saw.
Independent claim 9 (wafer): same subject matter in apparatus form.

Steps (a)–(c) are old: forming die on a wafer and forming streets between them is the most basic step in semiconductor manufacturing, and step (c)'s "to relieve cutting stress" language is a statement of intended result that adds essentially nothing beyond the formation of a street (cf. the specification's own Figure 5, which achieves "relief" merely by having "no metal structures … placed in the saw street"). The patentable weight therefore resides substantially in (d) — the placement/design of the in‑street test metal relative to the cut.

Note a drafting asymmetry worth recording: the Summary and Detailed Description present a third embodiment — "a dicing saw … comprising at least two leading edges … and a trailing edge" — but no independent claim is drawn to that dicing saw; it appears in the claims only as a method step in claim 8. That embodiment therefore has no independent claim protection and is largely irrelevant to the § 103 analysis of claims 1–18 except through claim 8.

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5. Combinations that render the claims obvious

Combination A (primary): Fetterman + Akram '9024 + Intel '452 → claims 1 and 9

Mapping.

• Claim 1(a)–(c) / claim 9 (die + street between die): Fetterman claim 1 literally claims "at least two die areas formed on the wafer, the at least two die areas defining a street therebetween"; Intel and US 6,951,801 likewise show die areas separated by scribe/saw areas.
• Claim 1(d) / claim 9 ("temporary metal structures in the saw street for testing the wafer"): Fetterman discloses exactly this — a metal (aluminum thin‑film) test runner in the street between die areas used for wafer‑level testing. US 6,951,801 independently discloses "conductive structures … located in saw path … utilized for testing and alignment guides during manufacture." Akram '9024 confirms in‑street probe‑test elements as the known practice.
• Claim 1(d) ("locations … selected to avoid cutting stress from the dicing saw"): Akram '9024 (kerf deliberately narrower than the street/channel, leaving marginal material intact) and Intel '452 (metal in the cutting path is deliberately included or excluded, patterned, and volume‑fraction‑controlled to obtain a clean cut) supply the "select the location relative to the cut" teaching. US 6,951,801 supplies the why: metal in the saw path causes blade loading and "cracking, chipping, or other damage."

Motivation to combine (KSR rationales A, C, D, G).

1. Known problem, known remedy. US 6,951,801 and Akram '9024 both expressly attribute chipping/cracking/tearing during singulation to what the blade or beam encounters in the street; both propose geometry/材料 remedies. Placing in‑street metal where the cut will not stress it (or where a clean cut is enabled) is the "predictable use of prior art elements according to their established functions" (KSR, 550 U.S. at 417).
2. Direct design incentive. In‑street test structures exist to conserve die real estate (Akram '9024 Background; Fetterman). Once one has decided to keep test structures in the street, the only remaining question is where in the street — and the art (Intel '452; Akram '9024; US 6,951,801) makes clear that the relationship of structures to the cut path is the controlling variable. "If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious" (KSR).
3. No teaching away and no field barrier. Every reference is in wafer fabrication/singulation; none teaches away from in‑street test structures; the references collectively encourage them.
4. Predictable result. Avoiding metal in the kerf (or confining/harvesting it) to reduce blade loading and chipping is a mechanical result that follows directly from the references' own reasoning; the specification itself asserts no unexpected result beyond the expected reduction in chip‑outs.

Conclusion A: claims 1 and 9 are obvious over Fetterman in view of Akram '9024 and Intel '452, further in view of US 6,951,801. High confidence.

Combination B: claims 2 and 10 (metal structures lie completely outside the cut path)

Akram '9024 requires the singulating cut to be narrower than the channel/street so that material remains on the channel sidewalls after cutting — i.e., structures/materials at the street margins are by definition outside the kerf. Intel '452 expressly contemplates a cutting path "without any metal patterns," with metal structures located elsewhere. US 6,951,801 teaches that the metal in the saw path is what damages the wafer, reinforcing the desire to keep metal out of the cut. Motivation: keep the blade out of metal entirely to eliminate the blade‑loading/chipping mechanism the art identifies.

Conclusion B: claims 2 and 10 are obvious over Akram '9024 in view of Intel '452 (and US 6,951,801), depending from claim 1/9. High confidence.

Combination C: claims 3 and 11 (metal structures lie completely inside the leading edges of the cut path, to prevent cracks propagating outside the path)

Here the metal is entirely within the kerf. The art supplies the placement but with a different stated objective:

• US 6,951,801 discloses test/alignment "conductive structures … located in saw path 111," i.e., in the very region the blade will traverse, and identifies that metal as the source of blade loading and chipping.
• Intel '452 affirms that the cutting path "may include primarily metal structures" when the cutting process favors it (absorption of the cutting energy in the metal).
• A PHOSITA reading these together would recognize that if metal must remain in the street at all, confining it to the intended kerf (rather than letting it straddle the kerf edge) keeps the blade from tearing metal at the die edge — which is the mechanism the patent itself identifies ("the dicing saw drags the copper along"). This is a "finite number of identified, predictable solutions" situation (KSR at 421): place the metal outside the kerf, or confine it within the kerf.

Conclusion C: claims 3 and 11 are obvious over US 6,951,801 in view of Intel '452, in further view of Fetterman; the rationale is slightly less clean than for claims 2/10 because US 6,951,801's preference is to remove the in‑path metal altogether. Medium‑to‑high confidence.

Combination D: claims 4 and 12 (from zero to no more than about 50% of the metal structures between the near side of the street and each leading edge)

This is a numeric relationship between the street margin and the kerf. Two threads support obviousness:

• US 6,951,801 discloses a 100 µm scribe area with a 50–55 µm saw path and notes the saw path is blade width "plus tolerances for alignment and placement (5 microns)" — i.e., metal‑bearing scribe area outside the kerf is on the order of half the scribe width; and it discloses an 80 µm scribe width for a wire‑bond wafer, again with a much narrower blade.
• Intel '452 frames the material/metal volume fraction of the cutting path as an optimization variable.

A 50% figure is a result‑effective, quantitative design choice within the artisan's routine optimization, and the record contains no evidence that 50% is critical (no data in the specification tying chip‑out suppression to this threshold, so no unexpected‑results rebuttal is available). The patent itself argues only that less metal in the cut is better — an optimization continuum.

Conclusion D: claims 4 and 12 are obvious as design choices/obvious to try over US 6,951,801 and Intel '452. Medium confidence — a numeric limit in a rejection is always somewhat vulnerable, and the record does not show the 50% value expressly.

Combination E: claims 5, 6, 13, 14 (pattern the metal structures to reduce their metal density — striping/slotting/cross‑hatching)

• Intel '452 expressly discloses patterns within the cutting path, controlled volume fraction of metal in that path, and states that "shapes and sizes of the patterns within the laser cutting paths are merely exemplary as other shapes and sizes are also within the scope," including "metal walls" structures and designs varied layer‑by‑layer.
• US 6,951,801 supplies the motivation to reduce metal in the saw path (less blade loading, less chipping), and by removing only portions of the metal it effectively achieves a reduced metal density in the path.
• Slotting/hatching metal to reduce density is itself a conventional metal‑fill/density‑control technique in the art.

Conclusion E: claims 5, 6, 13 and 14 are obvious over Intel '452 in view of US 6,951,801. Medium‑to‑high confidence, with the caveat that Intel's stated motivation (laser absorption/clean cut) differs from the patent's (chip‑out avoidance); the artisan must be able to bridge "clean laser cut" to "clean blade cut." Since both are about what the singulation process encounters in the street, that bridge is available but should be articulated in the rejection.

Combination F: claim 7 (saw street width at least about 80 µm)

• US 6,951,801 discloses "the scribe area width of a wire bond wafer can be 80 µm," and elsewhere a 100 µm scribe area with a 50–55 µm saw path.
• Akram '9024 states the general rule that "the streets must be of sufficient width to allow any such anticipated damage occurring during dicing to remain clear of the functional integrated circuit elements of the dice."
• "About 80 µm" is squarely within the range the art already uses; the specification's asserted benefit ("a longer path for any microcracks to propagate") is the inherent consequence of a wider street and is not shown to be unexpected.

Conclusion F: claim 7 is obvious over US 6,951,801 (alone or with Akram '9024). High confidence.

Combination G: claims 15–18 (replace a portion of the copper in the saw street with an electrically conductive metal having higher absorption energy than copper — e.g., aluminum)

• US 6,951,801 is the key reference. It not only removes copper from the scribe area, it expressly states: "the conductive structures of the scribe area may be made of other types of metal such as gold, silver, or aluminum." It also frames the problem in mechanical terms consistent with the patent: copper in the saw path causes blade buildup and "cracking, chipping, or other damage."
• Fetterman discloses a saw‑street test runner made of aluminum.
• The claim's "higher absorption energy than copper" is an inherent, known, result‑effective property of the substituted material: substituting aluminum for copper in the street metal is (i) a simple substitution of one known element for another (KSR rationale B), (ii) expressly suggested by US 6,951,801, and (iii) produces the property the specification itself relies on (Al deforms less than Cu under cutting). Nothing in the record shows that the absorption‑energy advantage was unknown or unexpected; the specification states it as a matter of known material behavior.

Conclusion G: claims 15–18 are obvious over US 6,951,801, further in view of Fetterman. High confidence for claim 16/18 ("replace with aluminum," expressly named) and high‑to‑medium for claim 15/17's functional "higher absorption energy" limitation, which should be addressed as an inherent property of the recited substitution.

Combination H: claim 8 (separating the die with a dicing saw having leading edges that leave 0–≤50% of the metal structures between the near side of the street and each leading edge, and a trailing edge that harvests the remaining metal)

This is the weakest claim in the set, and it is the one I would not assert as obvious without more.

• The multi‑edge/dual‑blade, cut‑then‑harvest geometry (a leading narrower/outer cut followed by a trailing wider/inner cut that removes the metal left between the leading cuts) is a specific tool configuration.
• The examiner's five citations do not, on the record I can see, disclose a dicing saw with distinct leading edges and a trailing edge that "harvests" metal. Akram '9024 does describe recognized multi‑pass/alternate singulation approaches — a beveled‑blade partial cut followed by a narrower blade cut within it, and "multiple, laterally spaced lasers … in combination during a single pass" — and Intel '452 addresses cutting‑path material design, but those are not the same as an edge arrangement defined by the 0–50% metal‑retention geometry.
• A defensible § 103 position would need either (i) the beveled‑double‑cut technique as discussed in Akram '9024 combined with the metal‑harvesting motive drawn from US 6,951,801/Fetterman, on the theory that sequentially cutting the street with blades of different widths is a known way to control what material the final cut encounters, or (ii) additional art on multi‑blade/multi‑edge dicing. Both are plausible, but this is a combination I would characterize as medium‑to‑low confidence on the present record, and I would want to search multi‑blade dicing art before asserting it. I cannot verify additional art beyond the page's references at this time.

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6. Claims where the obviousness case is thin, and residual § 112 exposure

• Claim 8 — see above; the specific leading‑edge/trailing‑edge saw geometry is not squarely shown by the five citations.
• Claims 4/12 (the ~50% limit) — numeric, not expressly disclosed; needs a design‑choice/obvious‑to‑try rationale and a search for express disclosures.
• Claim 3/11 — the "metal inside the leading edges" placement is shown (US 6,951,801 has metal in the saw path) but the purpose articulated in the claim ("prevent dicing cracks from propagating outside the path") is not the purpose articulated by that reference.
• US 2003/0162368 A1 (Connell) should be used only cumulatively; it is about die‑warp/passivation stress and does not support the "cutting stress" mechanism.
• US 2002/0098623 A1 (Akram) — I could not verify its substance in this session; I would not rely on it.

Related § 112 vulnerability (not § 103, but relevant to overall validity): claim 1(c)'s "forming a saw street … to relieve cutting stress" and claim 1(d)'s "locations … selected to avoid cutting stress" are functional/result‑oriented recitations. If a challenger successfully argues they recite only a result, the claims collapse to the bare idea of placing in‑street test metal where the blade will not stress it — which is exactly the concept the prior art renders obvious. Conversely, the specification provides little in the way of measured data (no chip‑out yield numbers, no criticality of the 80 µm or 50% figures), which weakens any unexpected‑results rebuttal.

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7. Motivation‑to‑combine summary (and absence of rebuttal)

A compact statement of the motivation, suitable for a rejection:

At the 2005 priority date, it was well known to place test structures in the wafer streets between die to conserve die area (Fetterman; Akram '9024 Background; US 6,951,801's test/alignment structures in the saw path). It was equally well known that cutting through the metal in those streets caused chipping, cracking, blade loading, and tearing (US 6,951,801; Akram '9024 Background). The prior art further taught that the relationship between structures and the cut path is a controllable design variable — metal may be excluded from the cut path, confined within it, patterned, or its volume fraction controlled (Intel '452), and the kerf may be made narrower than the street so that edge material survives (Akram '9024). A person of ordinary skill, seeking to keep in‑street test structures while avoiding the documented chipping/blade‑loading problem, would have had both the motivation and the predictable means to locate and shape those structures relative to the intended cut (claims 1–7, 9–14), to widen the street to the known 80 µm value (claim 7), and to substitute the known alternative scribe metal aluminum for copper in the street metal (claims 15–18). The results are the predictable consequences of each reference's own teaching; no reference teaches away.

Secondary considerations. The record supplies nothing that overcomes the prima facie case. The specification does not report unexpected results, and there is no evidence of commercial success nexus, licensing, or praise tied to the claimed features. To the extent a "long‑felt need" for chip‑out avoidance can be argued, the counter‑evidence is on this very page: the same assignee's later application US 2011/0006389 A1 ("Suppressing fractures in diced integrated circuits") and third‑party documents such as US 10,056,339 B2 show that the industry continued to attack the problem with ordinary engineering iterations rather than treating it as a breakthrough.

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8. Bottom line

Net assessment: 17 of the 18 claims appear vulnerable to a § 103 challenge on the references already of record, with claim 8 the principal hold‑out and claims 4/12 requiring a design‑choice rationale. If I were drafting a rejection, I would lead with Fetterman as to the "test structures in the street" element and Intel '452 + US 6,951,801 as to the "located/shaped to avoid cutting stress" element, and I would supplement the record with multi‑blade dicing art before challenging claim 8.

Verification caveats. (1) I did not retrieve the text of US 2002/0098623 A1, so nothing in this analysis rests on it. (2) For US 7,087,452 B2, I relied on the text of its publication US 2004/0212047 A1 as surfaced at https://patents.google.com/patent/US20040212047A1/en; the quoted cutting‑path material is attributed there, and I have not independently confirmed paragraph numbering. (3) US 2006/0079024 A1's appearance as an examiner citation is notable because its publication date (2006‑04‑13) post‑dates the priority date; its availability as prior art depends on its 2004‑03‑10 effective filing date under pre‑AIA § 102(e), which should be confirmed against the file history before relying on it in a formal rejection. (4) All dates and § 102 characterizations above are drawn from the citations and family data on the patent page and the referenced public databases; they are assumptions, not legal conclusions.