US 5591678

I'll verify the patent's current status and check for any recent litigation activity before summarizing.

Let me verify the litigation outcomes and check for any 2026 activity specifically involving this patent number.

Let me do one final check for any 2026 activity specifically tied to this patent number.

US Patent 5,591,678 — Analyst Summary

Verification note: I searched for the exact number 5591678 / 5,591,678 and did not find any 2026 Federal Circuit docket, appeal, or new litigation involving this patent. The only CAFC activity on record is from 2017–2018, and the patent's term has expired. Details below.

Bibliographic Data

Note: the Google Patents assignment history lists the inventors' original assignment to Hughes Aircraft Company, effective 1993-05-06. The "Original Assignee: HE Holdings Inc" label is the post-merger holding company, not the entity that took the inventors' assignment.

Abstract

A microelectronic device is fabricated by furnishing a first substrate (40) having a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the silicon layer (42), and a single-crystal silicon wafer (46) overlying the etch-stop layer (44), the wafer (46) having a front surface (52) not contacting the etch stop layer (44). A microelectronic circuit element (50) is formed in the single-crystal silicon wafer (46). The method further includes attaching the front surface (52) of the single-crystal silicon wafer (46) to a second substrate (58), and etching away the silicon layer (42) of the first substrate (40) down to the etch-stop layer (44). The second substrate (58) may also have a microelectronic circuit element (58′) therein that can be electrically interconnected to the microelectronic circuit element (50).

Independent Claims — Plain-Language Overview

The patent has three independent claims (1, 11, 13), all method claims.

Claim 1 — the base transfer-and-etch method. Three steps:

1. Start with a three-layer stack: an etchable layer, an etch-stop layer on top of it, and a wafer on top of that.
2. Build the circuit on the front of the wafer — specifically on the exposed side that faces away from the etch-stop layer.
3. Glue the wafer to a second substrate (a new handle/support), then etch the etchable layer all the way down to the etch-stop layer.

In essence: build the device while a thick, sacrificial substrate provides mechanical support, transfer the thin device to a permanent carrier, then dissolve the original substrate away and let the etch-stop layer define where the etching halts. This is the core "thin-film transfer / substrate removal" idea.

Claim 11 — transfer plus interconnection plus back-side access. Builds on the Claim 1 steps but adds:

• The second substrate already contains its own microelectronic circuit element;
• The attaching step includes making an electrical contact between the two circuit elements; and
• After the etch, an electrical connection is formed to the first circuit element through the etch-stop layer (i.e., from the back side).

This is the "stack two 2-D devices into a 3-D device and wire them together" claim.

Claim 13 — the silicon/SiO₂ species claim. Same scheme, narrowed to specific materials:

• Silicon etchable layer; silicon dioxide etch-stop layer; single-crystal silicon wafer whose front surface does not touch the SiO₂;
• Circuit formed in the front surface; front surface attached to a first side of a second substrate; and
• The silicon layer etched away with an etchant that attacks silicon but not silicon dioxide (specification: 5–10 molar KOH or NaOH at ~60 °C).

The dependent claims add: patterning the etch-stop layer (2, 14); forming a back-side connection through the etch-stop layer and wafer to the circuit element (3, 15); forming a connection to the wafer through the etch-stop layer (4, 16); epoxy attach + degas/cure (8, 18); temporary mounting to an etch-resistant base (9); liquid etchant with differential etch rates (10); and thicknesses of ~500 µm silicon / ~1 µm SiO₂ / 30 nm–50 µm wafer (17).

Substantive Context

• The specification frame is three-dimensional stacking of 2-D devices. The stated problem is that interconnecting stacked wafers by edge leads or plug interconnects is "clumsy, space consuming, and impossible… for highly complex circuitry requiring many interconnects."
• The workaround described: fabricate on a thick temporary substrate, transfer to a permanent second substrate (e.g., via epoxy 60 and indium bumps 61), then remove the first substrate by selective etch against a buried SiO₂ stop.
• Figures 2–4 show (a) a three-element stack (50, 50a, 50b), (b) external wire-bonded leads, and (c) a "smart board" configuration in which a separate device is epoxy-attached and wire-bonded to the back-side metallization.
• The prosecution/practice caveat to keep in mind: the specification expressly disclaims that "standard" or "well known" means the combination was known — "mean that individual process steps are known generally, not that they are known in the present context or combination."

Litigation and Post-Grant History (important caveat to any reliance on this patent)

The patent is expired and its claims were cancelled. It should not be treated as live property.

• District court: Raytheon Co. v. [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), No. 2:15-cv-00341 (E.D. Tex.); Raytheon Co. v. Sony Kabushiki Kaisha (No. 2:15-cv-00342, E.D. Tex.).
• PTAB (all four consolidated into the appeal):
  • IPR2015-01201 — Sony, filed 2015-05-14, instituted 2015-12-02.
  • IPR2016-00209 — Sony, filed 2015-11-18, instituted 2016-03-29.
  • IPR2016-00739 — Samsung, filed 2016-03-10.
  • IPR2016-00962 — Samsung, filed 2016-04-28 (instituted on the same grounds as IPR2016-00209).
• Final Written Decisions (Nov. 30, 2016): the Board determined that claims 1–18 are unpatentable — anticipation by Bertin and/or Liu as to several claims, and obviousness under pre-AIA § 103 over Liu, Bertin, Morimoto, and combinations with Oldham/Riseman/Wen/Ying/Kusunoki.
• Federal Circuit: Raytheon Co. v. Sony Corp., Nos. 2017-1554, 2017-1556, 2017-1557, decided April 2, 2018 (nonprecedential), 727 F. App'x 662 — affirmed. The court affirmed the obviousness determinations over Liu and rejected Raytheon's arguments regarding Bertin; the "second substrate" construction issue (Morimoto's temporary support substrate) was found erroneous but moot.
• IPR certificate: the USPTO issued an inter partes review certificate under 35 U.S.C. § 318(b) on/about May 31, 2019, cancelling the claims. Google Patents lists the reassignment/expiration event as 2014-01-07 (anticipated expiration).

2026 docket check: My searches returned no 2026 CAFC or district-court activity naming US 5,591,678. The only "Raytheon 2026" materials that surfaced (Krick v. Raytheon, the Spain/ICSID enforcement filings, MDL 2873, SEC/ITAR matters) are unrelated to this patent.

Stated Uncertainty

1. Assignee naming. Google Patents labels the "Original Assignee" as HE Holdings Inc. while the assignment records show the inventors assigned to Hughes Aircraft Company. I have reported both rather than reconciling them.
2. Appellant identity on appeal. One secondary source phrasing ("Sony appealed with respect to claims 5, 13–14, and 16–18 only") is inconsistent with the caption Raytheon Co. v. Sony Corp., where Raytheon would be the appellant. I did not retrieve the full opinion text to resolve this; treat the appellant identity as approximate, though the affirmance result is consistent across sources.
3. Claim 17 typo. As reproduced, claim 17 recites the wafer thickness as "from about 30 nanometers to about micrometers" — the unit is missing. The specification says "about 30 nanometers to 50 micrometers." I am flagging this as an apparent typographical/OCR defect rather than silently correcting it.
4. No authoritative evidence exists that this patent was ever assigned to any entity other than as recorded above; a third-party aggregator listing an inventor at "Litel Instruments" is a data artifact, not an assignment record.

Bottom line: US 5,591,678 is a 1993-priority, 1997-issued Raytheon (originally Hughes Aircraft) method patent on transfer-and-back-etch fabrication of thin microelectronic devices using a buried etch-stop — a significant early articulation of layer-transfer/3D-stacking technique — but it is expired and all 18 claims were cancelled following adverse PTAB decisions affirmed by the Federal Circuit in 2018, with no 2026 activity found.

I'll research litigation involving US patent 5591678. Let me search several sources.

Let me gather more detail on the district court cases and their outcomes.

Let me confirm the district court case outcomes and check for any additional litigation.

Litigation Involving U.S. Patent No. 5,591,678

I searched the specific number 5,591,678 (the "’678 patent," US 08/482,172, titled "Process of manufacturing a microelectric device using a removable support substrate and etch-stop"). It was asserted by Raytheon Company (owner) in a coordinated campaign against image-sensor makers and handset OEMs in 2015, which triggered a parallel wave of IPRs. Below are the known proceedings. Per your instruction, I've kept to this exact patent number and excluded look‑alikes.

A. District Court Litigation (E.D. Tex., Marshall Division)

Both cases were filed the same day and were litigated before Judge Rodney Gilstrap and Magistrate Judge Roy S. Payne. The ’678 patent was asserted under 35 U.S.C. § 271(g) (process patent – importation of products made abroad by the patented process).

1. Raytheon Co. v. Samsung Electronics Co., Ltd. et al.

• Case No.: 2:15-cv-00341 (E.D. Tex.)
• Filed: March 6, 2015
• Plaintiff: Raytheon Company
• Defendants: [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.; Samsung Electronics America, Inc.; Samsung Semiconductor, Inc.; Samsung Telecommunications America LLC (Samsung's U.S. entities)
• Accused products (representative): Samsung S5K2P1 and S5K3H2 back-illuminated CMOS image sensors (Raytheon complaint)
• Status/Outcome: Case stayed pending resolution of the co-pending IPRs (stay entered, extended Dec. 20, 2016, pending the 1201/0209/0739 IPRs and appeals). After the patent's claims were cancelled in the IPRs, the parties filed a joint motion to dismiss, granted by Magistrate Judge Payne on June 8, 2018. Case disposed/closed; AO 120 termination form filed June 12, 2018. (UniCourt docket; Docket Alarm docket entries)

2. Raytheon Co. v. Sony Kabushiki Kaisha et al.

• Case No.: 2:15-cv-00342 (E.D. Tex.)
• Filed: March 6, 2015
• Plaintiff: Raytheon Company
• Defendants: Sony Kabushiki Kaisha; Sony Corporation of America; Sony Semiconductor Corporation; Sony EMCS Corporation; Sony Electronics, Inc.; Sony Mobile Communications (USA), Inc.; Sony Mobile Communications AB/Inc.; Apple, Inc.; and OmniVision Technologies, Inc.
• Status/Outcome: Answers/counterclaims filed spring 2015 (Apple and Sony counterclaimed against Raytheon). Also stayed pending the IPRs and ultimately dismissed in the same 2018 joint-dismissal episode as the companion case. (Justia docket)
• Note on consolidation: The two 2015 actions were treated together. The PTAB and the Federal Circuit both referred to the consolidated district-court matter as "Raytheon Co. v. Sony Corp., No. 2:15-cv-00342 (E.D. Tex.)," with Samsung/Sony/Apple/OmniVision collectively referred to as appellees/"Sony." (IPR2016-00962 institution decision)

B. PTAB Inter Partes Reviews (all against the ’678 patent)

These are "litigation" in the broad sense and were decisive. Google Patents lists four PTAB cases on this patent:

Result: The Board held all claims 1–18 unpatentable (obviousness over Liu, Bertin, Morimoto, and others) in IPR2015-01201 and IPR2016-00209/-00962, and the remaining claims were cancelled by adverse judgment in IPR2016-00739. IPR certificates reflecting the cancellations issued May 31, 2019. (Google Patents "Legal Events," IPRC entries.)

C. Court of Appeals for the Federal Circuit

Raytheon Co. v. Sony Corp., Nos. 2017-1554, 2017-1556, 2017-1557

• Court: U.S. Court of Appeals for the Federal Circuit
• Filed: Feb. 1, 2017 (appeal from the PTAB IPR final decisions)
• Panel: Judges Lourie, O'Malley, Wallach (O'Malley writing)
• Decided: April 2, 2018 – nonprecedential, 727 F. App'x 662
• Appellant: Raytheon Company; Appellees: Sony Corporation, Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor, Inc.
• Origin: PTAB Nos. IPR2015-01201, IPR2016-00209, IPR2016-00962
• Outcome: Affirmed. The court upheld the Board's obviousness holdings (rejecting Raytheon's Liu-inoperability, Bertin-reduction-to-practice, and claim-construction challenges). (CAFC opinion PDF; CAFC docket listing; RPX case page)

Summary Table

Caveats and Notes

• Timing/lapse: The ’678 patent issued Jan. 7, 1997, and expired before the IPRs were filed (Raytheon's suit was limited to § 271(g) past-infringement damages). Google Patents lists an anticipated expiration of Jan. 7, 2014.
• No other district-court suits: Based on the searches, the only district-court actions asserting 5,591,678 are the two 2015 E.D. Tex. cases above (which were effectively consolidated). I did not find any ITC Section 337 investigation, any non-U.S. litigation, or any later infringement suits on this patent. (Google Patents' Darts-IP "first worldwide family litigation" link points back to the same E.D. Tex. campaign.)
• Precision on party naming: Public docket databases sometimes aggregate the two 2015 cases (e.g., listing Sony/Apple/OmniVision defendants under the 00341 docket and vice-versa), reflecting consolidation. I've reported the case numbers and the originally named defendants as docketed.
• One uncertainty: The exact filing date of the Samsung case's ultimate dismissal order is stated as June 8, 2018 (Magistrate Judge Payne); the AO 120 termination form is dated June 12, 2018. I could not independently confirm the precise disposition mechanics of the 00342 case beyond that it was dismissed in the same 2018 episode, so I've flagged that rather than state it definitively.

If you need the actual PTAB petition exhibits, the IPR certificates, or PACER-level docket documents for the two district-court cases, I can pull those next.

I'll flag immediately that there's a conflict between the canonical "no PTAB activity" block and the litigation/PTAB data embedded in the patent text. Let me verify via web search before writing anything.

Let me pin down the IPR2016-00739 termination (adverse judgment per the patent-page data) and the Federal Circuit disposition.

PTAB proceedings on US 5,591,678 — analyst report

⚠️ Data-conflict flag (read first). The structured "PTAB proceedings on file" block in this prompt states the USPTO ODP returned no AIA trial proceedings and directs a default of "no PTAB activity." That default is wrong for this patent. The patent's own Google Patents record lists four IPRs and an IPR certificate, and web sources confirm the same. This looks like an ODP ingest gap for these legacy (2015–2017) proceedings, not an absence of activity. I am therefore reporting the four proceedings I can verify, with sources, and treating the ODP block as under-inclusive.

Proceedings overview

Four AIA trials (all Inter Partes Reviews) are on file; all four ended with the claims canceled, and the patent now has zero surviving claims. Breakdown: 0 active, 3 claims-invalidated (IPR2015-01201, IPR2016-00209, IPR2016-00739), 1 joined/subsumed (IPR2016-00962), 0 settled, 0 institution-denied. Each of the three substantive proceedings (1201, 209, 739) resulted in cancellation — 1201 and 209 invalidated all claims 1–18; 739 canceled claims 1–4 and 8–10 by adverse judgment. A PTAB IPR certificate issued 2019-05-31 covering all four trial numbers, after the Federal Circuit affirmed on 2018-04-02. Bottom line for a defendant: this patent is dead — all 18 claims are canceled. Any demand letter citing claim 1, 11, or 13 (or any dependent claim) is asserting a canceled claim, and the assertion has no case.

IPR2015-01201 — Sony Corporation v. Raytheon Company

• Type: Inter Partes Review
• Filed: 2015-05-14
• Status: Final Written Decision — all challenged claims held unpatentable. Plain English: patent owner lost on every claim.
• Judge panel: Jo-Anne M. Kokoski, Jennifer Meyer Chagnon (opinion author), Jeffrey W. Abraham
• Petition grounds: challenged claims 1–18. Instituted grounds (35 U.S.C. § 314(a), 2015-12-02): § 102 anticipation by Bertin (claims 1, 6, 7, 10, 11); § 103 Bertin + Morimoto (claims 5, 12, 13); § 103 Bertin + Ying (claim 9); § 103 Morimoto alone (claims 1, 2, 4, 5, 10, 13, 14, 16, 17); § 103 Morimoto + Oldham (claims 8, 18); § 103 Morimoto + Bertin (claims 3, 15).
• Institution decision: Instituted 2015-12-02 on claims 1–18 across all asserted grounds; the Board found the petition's § 102/§ 103 showings sufficient under § 314(a).
• Final Written Decision: 2016-11-30 ("we determine that Petitioner has shown, by a preponderance of the evidence, that claims 1–18 of U.S. Patent No. 5,591,678 … are unpatentable"). The Federal Circuit summarized the Board's holding as "all claims unpatentable under pre-AIA 35 U.S.C. § 103 as obvious over the prior art of record." Canceled: all claims 1–18 (including independent claims 1, 11, 13 and all dependents). No claim was held patentable.
• Settlement / termination: None — decided on the merits.
• Appeal: Yes — Fed. Cir. No. 2017-1554 (consolidated with 2017-1556 and 2017-1557), Raytheon Co. v. Sony Corp., decided 2018-04-02 (nonprecedential). Raytheon argued (1) the Board failed to address its inoperability argument about using silicon in Liu, (2) the Board erred in finding Raytheon failed to antedate Bertin, and (3) the Board misconstrued "second substrate." Disposition: affirmed as to the obviousness determinations; the court agreed Raytheon's "second substrate" construction argument had merit but held the issue moot. Slip op.: https://cases.justia.com/federal/appellate-courts/cafc/17-1554/17-1554-2018-04-02.pdf ; https://www.courtlistener.com/opinion/[4482890](/patent/4482890)/raytheon-company-v-sony-corporation/
• Defensive value: Total. Claims 1–18 are canceled and the affirmance is final. Any infringement theory built on this patent's claims is baseless — a plaintiff who asserts it today is asserting canceled claims.

IPR2016-00209 — Sony Corporation (joined by Samsung) v. Raytheon Company

• Type: Inter Partes Review
• Filed: 2015-11-18
• Status: Final Written Decision — all challenged claims held unpatentable.
• Judge panel: Jo-Anne M. Kokoski, Jennifer Meyer Chagnon (opinion author), Jeffrey W. Abraham
• Petition grounds: challenged claims 1–18. Instituted grounds (2016-03-29): § 102 anticipation by Liu (claims 1–4, 6, 7, 10, 11); § 103 Liu + Black (claims 2–4, 11); § 103 Liu + Riseman (claims 5, 12–16); § 103 Liu + Oldham (claim 8); § 103 Liu + Wen (claim 10); § 103 Liu + Wen + Ying (claim 9); and additional § 103 combinations directed to claims 17 and 18 for which the institution table in the sources is partially truncated. (References include U.S. Pat. 4,422,091 (Liu); 4,426,768 (Black); 4,106,050 (Riseman); 4,681,718 (Oldham); 3,846,198 (Wen).)
• Institution decision: Instituted 2016-03-29 on claims 1–18 on the Liu-based grounds above.
• Final Written Decision: 2016-11-30 — "claims 1–18 … are unpatentable." Canceled: all claims 1–18. No claim was sustained. Joined IPR2016-00962 was decided within this FWD (see footnote 1 to the decision).
• Settlement / termination: None.
• Appeal: Yes, consolidated into the same Fed. Cir. appeal captioned Raytheon Co. v. Sony Corp. (2017-1554/-1556/-1557, decided 2018-04-02) and affirmed.
• Defensive value: Redundant kill of all claims under a different primary reference (Liu) than the 1201 IPR (Bertin/Morimoto). Even if one obviousness theory were vulnerable, the other independently canceled every claim.

IPR2016-00739 — Samsung Electronics, et al. v. Raytheon Company

• Type: Inter Partes Review
• Filed: 2016-03-10
• Status: Terminated — Request for Adverse Judgment After Institution (37 C.F.R. § 42.73(b)); the judgment "constitutes a final written decision under 35 U.S.C. § 318(a)."
• Judge panel: Jo-Anne M. Kokoski, Jennifer Meyer Chagnon (opinion author), Jeffrey W. Abraham
• Petition grounds: challenged claims 1–4 and 8–10 (the Board's institution covered that scope).
• Institution decision: Instituted 2016-09-15 as to claims 1–4 and 8–10.
• Final Written Decision / judgment: On 2017-02-01 Raytheon filed a Request for Adverse Judgment asking the Board to cancel claims 1–4 and 8–10. The Board granted it on 2017-02-03: "claims 1–4 and 8–10 of U.S. Patent No. 5,591,678 are canceled," and entered adverse judgment against Raytheon. This is a discretionary refusal to defend the claims, not a merits win by petitioner.
• Settlement / termination: Termination by adverse judgment, not settlement; no settlement terms.
• Appeal: None on this record.
• Defensive value: Independent, binding cancellation of claims 1–4 and 8–10. It is the cleanest proof that the patent's drafting group (claims 1–4) was abandoned by its own owner after institution.

IPR2016-00962 — Samsung Electronics, et al. v. Raytheon Company

• Type: Inter Partes Review (instituted and joined with IPR2016-00209)
• Filed: 2016-04-28
• Status: Institued and joined with IPR2016-00209 (Google Patents lists the disposition as an adverse judgment via the consolidated certificate — because the joined proceeding was resolved by the 209 FWD).
• Judge panel: Jo-Anne M. Kokoski, Jennifer Meyer Chagnon (opinion author), Jeffrey W. Abraham
• Petition grounds: challenged claims 1–18; the Board found Samsung's petition "substantively identical to the Sony [209] Petition, containing only minor differences related to formalities," with "no changes to the facts, citations, evidence, or arguments."
• Institution decision: Instituted and joinder granted 2016-08-24. The Board instituted on the same grounds as the Sony 209 IPR and granted Samsung's motion for joinder under 37 C.F.R. § 42.122(b).
• Final Written Decision: None of its own — resolved by the IPR2016-00209 FWD of 2016-11-30 canceling claims 1–18.
• Settlement / termination: None.
• Appeal: Covered by the consolidated Fed. Cir. appeal.
• Defensive value: Minimal independent value; its significance is that it demonstrates the same petitioner group (Samsung) filed two IPRs on this patent (739 and 962) and that the Board consolidated rather than ran parallel trials.

Strategic summary

Claim status. Every claim of US 5,591,678 is canceled. Claims 1–18: CANCELED. Claims sustained: NONE. Claims untested: NONE. IPR2015-01201 and IPR2016-00209 each independently held all eighteen claims unpatentable as obvious (pre-AIA § 103), and those holdings were affirmed by the Federal Circuit on 2018-04-02; IPR2016-00739 separately canceled claims 1–4 and 8–10 by adverse judgment on 2017-02-03. The PTAB's IPR certificate (K1) issued 2019-05-31 covering trials IPR2015-01201, IPR2016-00209, IPR2016-00962, and IPR2016-00739 confirms cancellation took effect; the Google Patents record shows the patent as "Expired – Lifetime" with no live claims.

Estoppel landscape. Because no claim survives, § 315(e)(2) estoppel is largely academic for a defendant — there is nothing left to invalidate and nothing to infringe. For completeness: Sony (IPR2015-01201, IPR2016-00209/962) and Samsung (IPR2016-00739, IPR2016-00962) and their privies are estopped in the E.D. Tex. actions from re-raising grounds they raised or reasonably could have raised. A new defendant is not itself bound, but it also gains nothing from filing an IPR: there are no claims to challenge, and the Office will not institute against canceled claims. The cleanest defense is simply the certificate and the FWDs.

Pattern signals. This was a coordinated, multi-front attack: Samsung filed two IPRs (739 and 962) and Sony filed two (1201 and 209), with the Board joining the two Samsung/Sony parallel petitions (962 into 209) to avoid duplicate trials. On the patent-owner side, Raytheon litigated hard — it defended claims 1–18 across both 1201 and 209, submitted an expert declaration (Dr. Eugene A. Fitzgerald) and a Patent Owner Response, and argued at an oral hearing on 2016-10-13 — but then abandoned claims 1–4 and 8–10 by adverse judgment in 739 and lost the rest. Raytheon appealed and lost at the Federal Circuit. No defensive aggregator (e.g., Unified Patents) appears in the chain — the petitioners were operating defendants (Sony and Samsung) responding to the parallel E.D. Tex. suits (Raytheon v. Samsung, 2:15-cv-00341; Raytheon v. Sony, 2:15-cv-00342, both filed 2015-03-06 under Judge Gilstrap / Magistrate Judge Payne). Those suits were stayed pending the IPRs (stay extended 2016-12-20) and dismissed on 2018-06-08.

Recommended next steps

• If you are a defendant being asserted against today, the dispositive artifact is the PTAB IPR certificate issued 2019-05-31 (Google Patents legal events, kind code K1; USPTO PTAB E2E), which cancels the claims in view of the final written decisions in IPR2015-01201, IPR2016-00209, IPR2016-00962, and IPR2016-00739. Underline the FWD dispositions: IPR2016-00209 FWD ("claims 1–18 … are unpatentable" — link above) and IPR2015-01201 FWD (same), plus the IPR2016-00739 judgment ("claims 1–4 and 8–10 … are canceled"). There is no live claim to infringe.
• If a plaintiff cites claims 1, 11, or 13 (the three independent claims) or any dependent claim, quote the Federal Circuit affirmance (Raytheon Co. v. Sony Corp., Nos. 2017-1554/-1556/-1557, Fed. Cir. 2018-04-02, nonprecedential) and the cancellation certificate. Asserting a canceled claim is frivolous and can support fees/sanctions.
• If you were considering filing your own IPR, don't — there are no claims to challenge and the statutory § 311 window is irrelevant to a canceled patent. Preserve instead the invalidity record (Liu, Bertin, Morimoto, Black, Riseman, Oldham, Wen, Ying) for any related-family or continuation patents.
• No active proceedings are pending, so there are no § 316(a)(11) trial-deadline milestones to track.
• Caveat on the record: the Federal Circuit opinion's procedural-history sentence attributes the limited-scope appeal (claims 5, 13–14, 16–18) to "Sony," while the caption names Raytheon as appellant — a likely OCR/appellant-mapping ambiguity in the search excerpt. I did not retrieve the final disposition sentence verbatim; the reliable, independently corroborated facts are (a) the court affirmed the Board's obviousness determinations and (b) it found the "second substrate" construction error moot. Treat the precise appellant-to-claim mapping on appeal with caution until the slip op. is read in full.

I'll research the assignment record and litigation history for US 5591678.

Let me try to pull the specific assignment recording details and correspondents.

US 5,591,678 — Assignment & Ownership Reconstruction

Patent: US 5,591,678 A — "Process of manufacturing a microelectric device using a removable support substrate and etch-stop"
App. No.: 08/482,172 (continuation of 08/006,120, filed 1993‑01‑19, abandoned) · filed 1995‑06‑07 · issued 1997‑01‑07 · priority 1993‑01‑19
Anticipated expiration: 2014‑01‑07 (expired; status "Expired – Lifetime")
Source of record data: Google Patents legal‑events / assignment tables for US5591678A (https://patents.google.com/patent/US5591678/en), which mirror the USPTO Assignment Center entries.

Data limitation up front: I could retrieve the three recorded assignment entries with reel/frame, conveyance type, assignor, assignee, effective date and recording date, but I could not retrieve the correspondent of record (recording attorney/agent) for any of the three entries from the sources available to me. The USPTO Assignment Center UI is not fully indexed by the search tools I have. Every "Correspondent" field below is therefore marked [not retrieved] — treat signal #3 as unclear, not absent. The reel/frame numbers are reported exactly as they appear in the Google Patents legal‑events table (REEL/FRAME:031501/0422, 031508/0958, 031501/0703); I did not independently re‑verify them against the Assignment Center image.

Inventors

Basis for employer: the only inventor‑signed instrument in the record is the assignment of interest executed 1993‑05‑06 in which all three named inventors (Bendik, Joseph J.; Malloy, Gerard T.; Finnila, Ronald M.) conveyed to Hughes Aircraft Company (reel 031501/0422). All three appear on that single instrument, so all three were working under the same obligation‑to‑assign regime — consistent with a Hughes Aircraft / Hughes Electronics engineering team. The subject matter (backside‑illuminated detector / stacked‑wafer processing) is consistent with Hughes' electro‑optical work; note that two of the cited prior‑art references in the patent's own file (US 4,783,594 and US 5,179,283) are Hughes‑family Santa Barbara Research Center patents, though SBRC is not itself a party to any recorded assignment on the '678 patent.

Unusual-pattern check: No evidence that the inventors departed within 12 months of filing, and no evidence of an inventor‑driven portfolio sale. The inventors' conveyance was a routine employment‑era assignment executed ~7 months after the 1993‑01‑19 priority filing. I cannot date any inventor departure — that is not in the assignment record, and I will not speculate.

Original assignee

• Assignee of record on the inventors' instrument: Hughes Aircraft Company (assignee address of record listed as California), per reel 031501/0422.
• Assignee named on the issued patent / bibliographic original assignee: HE Holdings, Inc. (Hughes Aircraft Company's Delaware corporation was renamed HE Holdings, Inc. as part of the 1997 Hughes reorganization — see the SEC-filed Amended and Restated Certificate of Incorporation of HE Holdings, Inc., which recites that the corporation "was originally incorporated under the name 'Hughes Aircraft Company'"). So Hughes Aircraft → HE Holdings is a corporate identity/reorganization event, not an arm's‑length sale.
• Business at the time of filing: Hughes Aircraft Company was a major aerospace and defense electronics contractor — airborne/ground radar, electro‑optical and infrared sensor systems, missiles (Falcon, Phoenix, Maverick, AMRAAM), satellites. Its parent (Hughes Electronics Corporation) was a GM subsidiary after GM's 1985 acquisition of Hughes Aircraft.
• Did they ship a product embodying the claims? The '678 claims recite a process (transfer a thin device from a first substrate to a second support, then backside etch). Hughes was a vertically integrated builder of focal‑plane arrays and EO sensors and had the in‑house capability to practice such a process; I have no documentary confirmation of a specific Hughes product built by the claimed method. Treat as plausible but unproven.
• Current status: Hughes Aircraft Company no longer exists as such. Its defense‑electronics business was spun out of GM as HE Holdings, Inc. and merged into Raytheon (announced/DOJ‑cleared October 1997; $5.1B deal value per DOJ, $9.5B per press accounts of the asset sale). Raytheon is operating (now RTX Corporation after the 2020 United Technologies merger). No bankruptcy of Hughes Aircraft/Raytheon is implicated.

Assignment timeline

Three recorded assignments exist. All three were recorded on 2013‑10‑29 — a single‑day, chain‑of‑title cleanup batch filed roughly 20 years (inventor assignment) and 16 years (the two merger entries) after the underlying executions, and roughly 16 months before Raytheon's March 2015 infringement suits. There are no post‑issuance assignments, security interests, licenses, or releases in the record.

1.

• 1993‑05‑06 (executed) / recorded 2013‑10‑29 — Reel 031501/0422
  • Conveyance: Assignment of interest (inventor → employer)
  • Assignor: Bendik, Joseph J.; Malloy, Gerard T.; Finnila, Ronald M. (individually)
  • Assignee: Hughes Aircraft Company (California)
  • Correspondent: [not retrieved]
  • Context: Inventor employment assignment of the original 1993 application — acquisition of title by the operating employer.

2.

• 1997‑12‑16 (effective) / recorded 2013‑10‑29 — Reel 031508/0958
  • Conveyance: Merger
  • Assignor: Hughes Aircraft Company
  • Assignee: HE Holdings, Inc. (California)
  • Correspondent: [not retrieved]
  • Context: Internal corporate reorganization (the 1997 Hughes reorganization / GM spin‑off structure) — recorded as a merger; substantively a renaming/identity transfer, not an arm's‑length sale.

3.

• 1997‑12‑17 (effective) / recorded 2013‑10‑29 — Reel 031501/0703
  • Conveyance: Merger
  • Assignor: HE Holdings, Inc.
  • Assignee: Raytheon Company (Massachusetts)
  • Correspondent: [not retrieved]
  • Context: Internal reorganization — completion of the $5.1B Raytheon/Hughes defense‑electronics merger; no third‑party licensing entity introduced. Raytheon (now RTX) remains assignee of record to this day.

Post‑chain prosecution/litigation events (for completeness — not assignments): IPRs filed by Sony (IPR2015‑01201, eff. 2015‑05‑14; IPR2016‑00209, eff. 2015‑11‑18) and Samsung (IPR2016‑00739, eff. 2016‑03‑10; IPR2016‑00962, eff. 2016‑04‑28); PTAB final written decisions Nov 30, 2016 holding all claims 1–18 unpatentable; Federal Circuit appeals 17‑1554 / 17‑1556 / 17‑1557 affirmed 2018‑04‑02; IPR certificates issued 2019‑05‑31 cancelling the claims.

Timeline diagram

timeline
    title Ownership of US 5591678
    1993 : Priority application filed
         : Inventors assign to Hughes Aircraft
    1995 : Continuation application filed
    1997 : Patent issues to HE Holdings
         : Hughes renamed HE Holdings
         : HE Holdings becomes Raytheon
    2013 : Three assignments recorded same day
    2014 : Patent term expires
    2015 : Raytheon sues Sony and Samsung
    2016 : PTAB cancels all claims
    2018 : Federal Circuit affirms
    2019 : IPR certificates issued

NPE / troll-pattern signals

1. Shell‑entity transfer — NOT PRESENT.
The chain never leaves operating defense‑industrial corporations: Hughes Aircraft Company → HE Holdings, Inc. → Raytheon Company. No "IP / Patents / Licensing / Holdings / Ventures" licensing vehicle appears as an assignee anywhere in reels 031501/0422, 031508/0958 or 031501/0703. Caveat: "HE Holdings, Inc." contains the word "Holdings," but it is a 1953‑incorporated Delaware operating corporation that was literally the renamed Hughes Aircraft Company (per its SEC‑filed restated certificate of incorporation) and was the surviving entity in the Raytheon merger — it is a corporate holding‑company artifact of a $5B defense merger, not a single‑purpose licensing LLC. This is exactly the situation where naming alone would mislead, so I have not scored it.

2. Known asserter in the chain — NOT PRESENT.
No assignee in the chain matches Acacia, Marathon, Intellectual Ventures, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or any Spangenberg entity. The terminal assignee is Raytheon Company — a Fortune‑500 prime defense contractor. Raytheon does not appear in RPX/Unified NPE directories as a patent plaintiff‑for‑hire; its activity here is a single assertion campaign in its own field.

3. Repeat correspondent across the chain — UNCLEAR / INSUFFICIENT DATA.
I could not obtain the correspondent of record for any of the three recordings, so I can neither confirm nor rule out a single attorney/firm having filed all three on 2013‑10‑29. What the record does show structurally: the three recordings share the recording date 2013‑10‑29 and two of them sit in the same 031501 reel series (frames 0422 and 0703), which is strong circumstantial evidence they were filed as one batch by one filer. If a single correspondent recurs across 031501/0422, 031508/0958 and 031501/0703, that is administratively expected (in‑house or one outside firm perfecting title) and would not, standing alone, be an NPE tell here, because the batch is a title‑cleanup by an operating company, not a shell‑LLC pipeline. To close this signal, pull the correspondent fields directly through the Assignment Center for patent 5,591,678.

4. Cascading transfers — NOT PRESENT.
Three transfers spanning 1993‑05‑06 to 1997‑12‑17 (~4.6 years), all intra‑group reorganizations tied to documented GM/Hughes/Raytheon transactions. No chain of consecutive LLC assignees, no <24‑month LLC cascade, no common‑principal shell ladder.

5. Pre‑litigation transfer — NOT PRESENT (but note the recording timing).
Raytheon's suits were filed 2015‑03‑06; nothing was transferred within six months of that date. The last transfer of title was effective 1997‑12‑17, eighteen years earlier. What happened near the lawsuits is recordation, not conveyance: all three instruments were recorded 2013‑10‑29, ~16 months before the complaints. That is a title‑perfection administrative step (done well before, not within, the 6‑month window and before the 2014‑01‑07 expiration), which I flag as context rather than score as a signal.

6. Bankruptcy fire‑sale — NOT PRESENT.
Hughes Aircraft's defense business exited via a solvent ~$5.1B (DOJ figure) / reported $9.5B merger with Raytheon in 1997. No Chapter 7/11, no §363 sale, no credit‑bid. Raytheon has not been in bankruptcy.

7. Privateering — NOT PRESENT.
No operating company conveyed the patent to an NPE to assert on its behalf. Raytheon itself is the named plaintiff in both E.D. Tex. actions and the named patent owner in all four IPRs (Sony Corp. v. Raytheon; Samsung v. Raytheon). No SEC 8‑K/10‑K monetization vehicle, no Patent Progress/EFF privateering coverage identified for this patent.

8. Defensive aggregator — NOT PRESENT.
The chain ends at Raytheon/RTX. It does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. The patent was not neutralized by acquisition into a defensive pool; it was neutralized judicially (all claims cancelled via IPR, affirmed on appeal, certificates issued 2019‑05‑31).

Verdict

Operating-company assertion.

Raytheon Company — a large operating defense/EO manufacturer and the terminal assignee under reel 031501/0703 — is the named plaintiff that asserted the '678 process patent under 35 U.S.C. § 271(g) against Sony, Samsung, OmniVision and Apple in E.D. Tex. (2:15‑cv‑00341 and 2:15‑cv‑00342, filed 2015‑03‑06) alleging § 271(g) infringement by imported back‑illuminated CMOS image sensors made abroad by the patented process — i.e., suits against actual competitors/suppliers in its own sensor field, not a licensing shell monetizing a purchased portfolio. Every link in the chain (reels 031501/0422, 031508/0958, 031501/0703) is an operating industrial corporation, with the two 1997 entries being internal reorganizations (Hughes → HE Holdings → Raytheon) of the GM/Hughes/Raytheon merger; there is no shell LLC, no NPE, no pre‑suit conveyance, and no defensive‑pool acquisition. Two caveats: (i) I could not retrieve the correspondent of record, so signal #3 is unresolved; and (ii) the asserted claims were ultimately cancelled (PTAB final written decisions 2016‑11‑30; Fed. Cir. affirmed 2018‑04‑02; IPR certificates 2019‑05‑31), so the patent is now unenforceable and expired (2014‑01‑07) — the chain's "value" was litigated away, not sold.

Links for verification:

• USPTO Assignment Center — search by patent number 5591678: https://assignment.uspto.gov/patent/index.html (and https://assignmentcenter.uspto.gov/)
• Mirror of the three recorded entries: https://patents.google.com/patent/US5591678/en (Legal Events / Assignment tables: REEL/FRAME 031501/0422, 031508/0958, 031501/0703)
• Litigation dockets: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A15-cv-00341 · https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A15-cv-00342
• PTAB: https://portal.unifiedpatents.com/ptab/case/IPR2015-01201 · https://portal.unifiedpatents.com/ptab/case/IPR2016-00209 · https://portal.unifiedpatents.com/ptab/case/IPR2016-00739 · https://portal.unifiedpatents.com/ptab/case/IPR2016-00962
• Merger context: DOJ press release, 1997‑10‑16 (https://www.justice.gov/archive/atr/public/press_releases/1997/1256.htm) · Raytheon/Hughes proxy (https://www.sec.gov/Archives/edgar/data/[1047122](/patent/1047122)/000095013097004926/0000950130-97-004926.txt)

I'll verify the patent record and spot-check the key cited references before building the analysis.

Let me pull abstracts for the remaining cited references so the §102 mapping is grounded in actual disclosure rather than titles alone.

Prior‑Art Analysis — US 5,591,678

Scope note (per your strict rules): everything below concerns US 5,591,678 only. I did not treat any similar string (e.g., 5,591,876, 5,916,678, or family members) as this patent. Where the record spells the title "microelectric," I reproduce that spelling literally.

Sourcing note: I retrieved the bibliographic record and full text from Google Patents (https://patents.google.com/patent/US5591678/en) and cross‑checked against the USPTO‑derived mirrors FreePatentsOnline (https://FreePatentsOnline.com/5591678.html) and the issued‑front‑page PDF (https://patentimages.storage.googleapis.com/3a/90/28/46e9e7d66c8a16/US5591678.pdf). The consistent front‑page data is: US 5,591,678 A; Appl. No. 08/482,172; filed 1995‑06‑07; continuation of Ser. No. 006,120 filed 1993‑01‑19 (now abandoned); priority 1993‑01‑19; published/granted 1997‑01‑07; inventors Bendik, Malloy, Finnila; assignee chain Hughes Aircraft → HE Holdings → Raytheon; status "Expired – Lifetime" (anticipated expiration 2014‑01‑07). I could not open a live USPTO PatentCenter query in this session (search budget exhausted), so treat the mirrors as the source of record.

1. Critical dates and the § 102 framework

Because this application was filed in 1995 as a continuation of a 1993 parent, pre‑AIA § 102 governs:

This matters for exactly three of the twenty cited references, which I flag individually below:

2. What must be disclosed to anticipate — element decomposition

Claim 1 requires, in order:

• E1 a first substrate having an etchable layer, an etch‑stop layer overlying the etchable layer, and a wafer overlying the etch‑stop layer;
• E2 a microelectronic circuit element formed in the exposed side of the wafer (i.e., the side opposite the etch‑stop);
• E3 attaching the wafer of the first substrate to a second substrate — i.e., transfer to a new support after circuit formation;
• E4 etching away the etchable layer down to the etch‑stop layer.

Claim 11 adds E6 (second substrate carries a second circuit element) and E7 (making electrical contact between the two elements) and E5 (an electrical connection formed through the etch‑stop layer after the etch).

Claim 13 is the material‑specific species: silicon etchable layer / silicon dioxide etch‑stop / single‑crystal silicon wafer with a front surface not contacting the oxide; circuit element in that front surface; front surface attached to a first side of a second substrate; then etch the silicon with an etchant that attacks Si but not SiO₂.

Dependent claims 2–4 and 14–16 (patterning the etch‑stop; through‑connections to the circuit element and to the wafer), 5/12 (Si/SiO₂/single‑crystal Si), 8/18 (epoxy attach, vacuum degas + cure), 9 (fixing to an etchant‑resistant support), 10 (liquid etchant), 17 (≈500 µm / ≈1 µm / ≈30 nm–50 µm) each add a further limitation.

3. The twenty examiner‑cited references

Tier 1 — Closest art (§ 103 primary references against claims 1, 5, 11, 13)

1. US 5,034,343 A — "Manufacturing ultra‑thin wafer using a handle wafer," Harris Corporation. Filed 1990‑03‑08; published 1991‑07‑23. Confidence: high — full text verified (https://patentimages.storage.googleapis.com/cd/29/61/2e012e94173296/US5034343.pdf).
Discloses bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer, thinning the device wafer to ≤ 7 mils, performing device formation steps in an epitaxial layer on the exposed surface of the device wafer, then removing the handle wafer with an etch that stops on the intermediate oxide layer (grind + etch). A double‑bond variant adds a third device wafer to form SOI.

• Potentially reads on: claims 1, 5, 10, 13, 17.
• § 102 assessment — the single most dangerous reference, but not a clean anticipation. E1 (etchable handle / oxide etch‑stop / device wafer), E2 (devices formed on the exposed side before removal) and E4 (etch‑back stopping on the oxide) all appear. The gap is E3: claims 1 and 13 require attaching the wafer (claim 13: "the front surface of the single‑crystal silicon wafer") to a second substrate before the etch, whereas US 5,034,343 removes the handle and produces a self‑supporting 7‑mil wafer. A § 102 rejection would have to read its "handle wafer" as the claimed "second substrate" — but the handle is the layer that is removed, not the layer the wafer is attached to, and its SOI variant bonds the third wafer after, not before, thinning. I judge a single‑reference § 102 rejection unlikely; § 103 is strong and this is the natural primary reference.
• Note: its disclosed ranges (device wafer 2–6 mils; oxide 1–3 µm) are pertinent to claim 17.

2. US 4,829,018 A — "Multilevel integrated circuits employing fused oxide layers," Wahlstrom, Sven E. Filed 1986‑06‑27; published 1989‑05‑09. Confidence: high — full text verified (https://patents.google.com/patent/US4829018).
Epitaxial layer grown on a substrate, oxidized; the oxidized surface fused to the oxidized surface of a second substrate at 800–1200 °C; "the individual circuits are fabricated in the wafers before fusion"; thereafter one substrate is removed by chemical etching exploiting etch‑rate dependence on resistivity, leaving the thin epitaxial layer; conductive vias interconnect the layers.

• Potentially reads on: claims 1 (E2, E3, E4 in part), 6, 7, 11.
• § 102 assessment. This is the closest art on the sequence "form circuit → bond to second substrate → etch away original substrate," and it expressly contemplates circuits formed before fusing. It fails literal anticipation of claim 1 because the etch stop is a doping/resistivity contrast inside the same wafer, not a discrete etch‑stop layer overlying the etchable layer with the wafer overlying the etch‑stop layer (its stacking order is Si(substrate)/epi/fused oxide/epi/Si(substrate) — the oxide lies between the two device layers, not between the etchable layer and the device layer). It also uses oxide fusion, not the epoxy of claim 8. § 103: primary.

3. US 5,024,723 A — "Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning," Goesele, Ulrich M. Filed 1990‑05‑07; published 1991‑06‑18. Confidence: high — full text verified (https://patents.google.com/patent/US5024723).
Carbon ions implanted into a silicon wafer create a buried etch‑stop layer; the wafer is bonded to a support wafer carrying an oxide or nitride insulating layer; the pair is annealed; the substrate is removed by grinding plus alkaline etching (EDP or KOH) that stops on the carbon layer; the remaining carbon‑implanted silicon forms the thin film.

• Potentially reads on: claims 1 (E1, E4), 5, 10, 13.
• § 102 assessment — no. Its pre‑etch stack does contain an etchable silicon layer with an overlying etch‑stop; but (a) no circuit element is formed (E2 absent), and (b) the support is bonded before any device formation, so the claimed ordering (E3 after E2) is absent; (c) the layer that becomes the "wafer" is the etch‑stop layer, not a wafer overlying it. § 103: strong secondary reference — and it is directly probative of claim 10, since it names KOH and EDP as the liquid etchant.

4. US 4,612,083 A — "Process of fabricating three‑dimensional semiconductor device," NEC Corporation (Yasumoto et al.). Filed 1984‑07‑20; published 1986‑09‑16. Confidence: high — full text verified (https://patentimages.storage.googleapis.com/f8/14/f8/c440b141518119/US4612083.pdf).
Prepare ≥ 2 multilayer structures, each with a substrate, a functional layer, at least one semiconductor element, and a conductor with an exposed end; align and integrally unite them while providing electrical connections between the semiconductor elements.

• Potentially reads on: claims 6, 7, and the "making an electrical contact" element of claim 11; also the attaching step E3 of claim 1.
• § 102 assessment — no full anticipation. The verified text does not disclose the claim‑1 stack (E1: etchable layer / etch‑stop overlying it / wafer overlying the etch‑stop) nor the "etching away the etchable layer … down to the etch‑stop layer" step (E4); its union is by integral bonding/heat, not selective etch‑back. It does read squarely on the second‑element interconnect (claims 6–7) — but those are dependent claims, so no independent claim falls.

Tier 2 — Relevant to specific dependent claims or to individual elements

5. US 4,815,208 A — "Method of joining substrates for planar electrical interconnections of hybrid circuits," Texas Instruments. Filed 1987‑05‑22; published 1989‑03‑28. Confidence: medium (title/front‑page record only; full text not retrieved).
Joining substrates with planar interconnections between hybrid circuits.

• Potentially reads on: claims 7 and 11 ("making an electrical contact … to the second microelectronic circuit element") and the attachment technique of claim 8.
• § 102: no — it lacks E1 and E4 entirely, so nothing anticipates; § 103 secondary reference for the attach‑and‑interconnect elements.

6. US 4,943,491 A — "Structure for improving interconnect reliability of focal plane arrays," Honeywell Inc. Filed 1989‑11‑20; published 1990‑07‑24. Confidence: medium (title/record only).
Interconnect structures improving reliability of focal‑plane‑array connections.

• Potentially reads on: claims 3, 4, 9, 15, 16 (back‑side connections formed through a layer to a device/pad).
• § 102: no. § 103 secondary reference bearing on the back‑side through‑connection subject matter.

7. US 4,131,909 A — "Semiconductor integrated circuit isolated through dielectric material and a method for manufacturing the same," Tokyo Shibaura Electric Co., Ltd. Filed 1975‑10‑25; published 1978‑12‑26. Confidence: medium (title/record only).
Dielectric isolation of IC elements.

• Potentially reads on: claim 1 (E1 — dielectric layer sandwiched between silicon regions), claim 5/12 (Si/SiO₂/Si genus), claim 10.
• § 102: no — no second‑substrate transfer after device formation, no etch‑back‑to‑etch‑stop sequence as claimed. § 103 secondary reference for the "dielectric layer between two silicon layers" element.

8. US 4,169,000 A — "Method of forming an integrated circuit structure with fully‑enclosed air isolation," International Business Machines Corp. Filed 1976‑09‑02; published 1979‑09‑25. Confidence: medium (title/record only).
Air isolation formed by etching and enclosure.

• Potentially reads on: claim 1 (isolation via etching), claim 10.
• § 102: no. § 103 background for etch‑selective removal/enclosure.

9. US 3,332,137 A — "Method of isolating chips of a wafer of semiconductor material," RCA Corp. Filed 1964‑09‑28; published 1967‑07‑25. Confidence: medium (title/record only).
Separating individual chips from a wafer by mounting and material removal.

• Potentially reads on: claim 9 (fixing to an etching support) and the general E4 removal notion.
• § 102: no — nothing resembling the buried etch‑stop stack or the after‑device second‑substrate transfer. § 103/background only.

10. US 3,623,219 A — "Method for isolating semiconductor devices from a wafer of semiconducting material," RCA Corp. Filed 1969‑10‑22; published 1971‑11‑30. Confidence: medium (title/record only).
Same lineage as item 9; device isolation by material removal.

• § 102: no. § 103/background only.

11. US 4,980,308 A — "Method of making a thin film transistor," Sony Corporation. Filed 1987‑01‑30; published 1990‑12‑25. Confidence: medium (title/record only).
Fabrication of a TFT, including transfer/thinning relative to an insulating substrate.

• Potentially reads on: claims 1, 5, 13 (device in a thin crystalline layer on an insulator).
• § 102: no. § 103 background.

12. EP 0 371 862 A2 — "Method of forming a nonsilicon semiconductor on insulator structure," The University of North Carolina at Chapel Hill. Filed 1988‑11‑29; published 1990‑06‑06. Confidence: medium (title/record only).
Bonded semiconductor‑on‑insulator with substrate removal.

• Potentially reads on: claim 1 (E1 genus); claims 5/12/13 for the material‑system genus.
• § 102: no. § 103 secondary reference for the generic bond‑and‑remove‑substrate SOI technique.

13. US 4,467,340 A — "Pre‑multiplexed Schottky barrier focal plane," Rockwell International Corp. Filed 1981‑11‑16; published 1984‑08‑21. Confidence: medium (title/record only).
IR focal plane with on‑focal‑plane multiplexing.

• Potentially reads on: claims 6, 7, 11 (two‑element hybrid interconnect).
• § 102: no. § 103 background for detector/readout hybridisation.

14. US 4,670,653 A — "Infrared detector and imaging system," Rockwell International Corp. Filed 1985‑10‑10; published 1987‑06‑02. Confidence: medium (title/record only).
IR detector and imaging system.

• § 102: no. § 103 background (detector hybrid art).

15. US 4,783,594 A — "Reticular detector array," Santa Barbara Research Center. Filed 1987‑11‑20; published 1988‑11‑08. Confidence: medium (title/record only). Note: SBRC was a Hughes Aircraft subsidiary — the same corporate family as the applicant.

• Potentially reads on: claims 6, 7, 11.
• § 102: no. § 103 background; possibly relevant to the common‑ownership/inventive‑entity picture rather than to novelty.

16. JP S63‑308970 A — "Hybrid type infrared detector," Nikon Corp. Filed 1987‑06‑11; published 1988‑12‑16. Confidence: medium (record only).
Hybrid IR detector (detector array joined to readout).

• Potentially reads on: claims 6, 7.
• § 102: no — and as a foreign published application it is prior art only as of its 1988‑12‑16 publication date. § 103 background.

17. US 5,043,582 A — "X‑ray imaging system and solid state detector therefor," General Imaging Corporation. Filed 1985‑12‑11; published 1991‑08‑27. Confidence: medium (title/record only).
Solid‑state x‑ray detector array and system.

• § 102: no. § 103 background.

18. US 5,179,283 A — "Infrared detector focal plane," Santa Barbara Research Center. Filed 1989‑08‑07; published 1993‑01‑12. Confidence: medium (title/record only).
IR focal plane array.

• Potentially reads on: claims 6, 7.
• § 102: no. Date caution: publication was seven days before the 1993‑01‑19 priority date, so it is not § 102(b) art; only § 102(a) (publication) and § 102(e) (application filed 1989‑08‑07) are available.

19. US 5,182,624 A — "Solid state electromagnetic radiation detector FET array," Minnesota Mining and Manufacturing Co. Filed 1990‑08‑08; published 1993‑01‑26. Confidence: medium (title/record only).
FET‑based solid‑state radiation detector array.

• § 102: no. Date caution: published after the priority date → § 102(e) only, as of the 1990‑08‑08 filing.

20. US 5,227,656 A — "Electro‑optical detector array," Cincinnati Electronics Corporation. Filed 1990‑11‑06; published 1993‑07‑13. Confidence: medium (title/record only).
Electro‑optical detector array.

• § 102: no. Date caution: published after the priority date → § 102(e) only, as of the 1990‑11‑06 filing.

4. The non‑patent citations (8 entries)

5. Bottom line

On the twenty examiner citations, I do not see a clean single‑reference § 102 anticipation of any of independent claims 1, 11 or 13. The citations divide into:

• § 103 primary references (the real threat): US 5,034,343 (bond + oxide etch‑stop + device formation + etch‑back), US 4,829,018 (circuits first, fuse/bond, etch away one substrate, via‑interconnect), US 5,024,723 (buried etch‑stop + bond + alkaline etch), US 4,612,083 (bond two device structures and interconnect).
• § 103 secondary references on discrete elements: US 4,815,208 and US 4,943,491 (bonding/interconnect), US 4,131,909 and US 4,169,000 (dielectric/air isolation and etch‑selective removal), EP 0 371 862 A2 (generic bonded SOI), US 3,332,137 and US 3,623,219 (support + substrate removal), US 4,980,308 (TFT transfer).
• Background detector/focal‑plane art: US 4,467,340; US 4,670,653; US 4,783,594; US 5,179,283; US 5,043,582; US 5,182,624; US 5,227,656; JP S63‑308970 A.

The reason no independent claim falls is consistently the same: E3 (attaching the device wafer's front/exposed side to a second substrate after circuit formation) combined with E1 (a discrete etch‑stop layer overlying the etchable layer with the wafer overlying the etch‑stop layer). Prior art supplies one or the other, never both in the claimed order. Claims 6–7 and the interconnect element of claim 11 are the most exposed, but they are dependent/subelement limitations.

Two important caveats you should carry forward:

1. Confidence is not uniform. I verified full text for US 4,612,083, US 4,829,018, US 5,024,723 and US 5,034,343. The other sixteen references and the non‑patent items are characterised from the patent's own citation table plus their titles/assignees; I was unable to retrieve their full texts before my search budget ran out. Any of them could disclose more than the title suggests, and a competent § 102 analysis requires their actual disclosure.

2. The examiner citations are not where the litigated art lives. This patent carries IPR petitions from Sony (IPR2015‑01201, filed 2015‑05‑14; IPR2016‑00209, filed 2015‑11‑18) and Samsung (IPR2016‑00739, filed 2016‑03‑10; IPR2016‑00962, filed 2016‑04‑28), plus Texas E.D. Tex. cases 2:15‑cv‑00341 and 2:15‑cv‑00342 and Federal Circuit appeals 17‑1554, 17‑1556 and 17‑1557 (per https://portal.unifiedpatents.com/ptab/case/IPR2016-00209 and the litigation links on the Google Patents page). Inter partes review certificates were issued 2019‑05‑31 covering all four trial numbers. Those petitions necessarily relied on prior art beyond the twenty examiner citations. I do not have the certificate contents in this session and will not speculate on which claims were cancelled or confirmed — that record, not the front page, is where the dispositive § 102 art sits, and I'd need the IPR final written decisions and the 2019 certificates to complete the picture.

I'll ground this obviousness analysis in the actual prosecution record and the cited prior art. Let me pull the IPR outcomes and confirm the content of the key references.

The PTAB record is decisive here. Let me gather the details of the key references and the motivation-to-combine reasoning.

Obviousness Analysis — U.S. Patent No. 5,591,678 (35 U.S.C. § 103)

Patent: US 5,591,678 A — "Process of manufacturing a microelectric device using a removable support substrate and etch-stop"
Inventors: Bendik, Malloy, Finnila | Granted: 1997‑01‑07 | Priority: 1993‑01‑19 (parent Ser. No. 006,120, now abandoned) | Filed (as filed): 1995‑06‑07
Governing law: pre‑AIA § 103 (priority before 2013‑03‑16), so Graham v. John Deere factors + KSR Int'l v. Teleflex (flexible, expansive motivation standard; TSM is not the exclusive test).

0. Bottom line up front

Every one of claims 1–18 was held unpatentable under § 103 (and § 102 for several claims) by the PTAB in four inter partes reviews, and the Federal Circuit affirmed on 2018‑04‑02. The Board's Final Written Decisions in IPR2015‑01201 and IPR2016‑00209 both state that "claims 1–18 of U.S. Patent No. 5,591,678 … are unpatentable." The Google Patents page itself records the resulting IPR certificates (kind code K1, effective 2019‑05‑31), i.e., cancellation of the challenged claims.

So this is not a close call to be predicted from first principles — it is a decided case. Two important notes before the analysis:

• Two different prior-art sets exist. (i) The 20 patent citations + 8 non‑patent citations listed on the page — these are the examiner‑considered references. (ii) The references actually used by Sony/Samsung at the PTAB — Liu (US 4,422,091), Bertin (US 5,202,754), Morimoto (JP 64‑18248), Riseman (US 4,106,050), Oldham (US 4,681,718), Wen (US 3,846,198), Black (US 4,426,768), Ying, Kusunoki — which are NOT on the page's citation lists. I analyze both, because the page-listed art alone is sufficient for most claims, and the IPR art is dispositive for all of them.
• Do not confuse the two "Liu"s. The NPL citation on the page ("Liu, C. N., Matching the Thermal Coefficients of Expansion of Chips to Module Substrate, IBM TDB vol. 19, No. 12, May 1977") is a different document by a different author than "Liu, U.S. Patent No. 4,422,091" relied on by the PTAB/Federal Circuit. Same surname, unrelated disclosures.

1. The invention in one paragraph, and the specification's own admissions

The claims are directed to a substrate-transfer / handle-wafer process: furnish an etchable layer / etch‑stop layer / device wafer sandwich; build the circuit on the exposed face of the wafer (opposite the etch‑stop); attach that face to a second substrate; then etch the etchable layer away down to the etch‑stop; then optionally pattern the etch‑stop and form back‑side connections to the circuit element (through the wafer) and/or to the wafer itself.

The specification contains admissions that do most of the § 103 work:

• The starting substrate "can be purchased commercially."
• "All references herein to 'standard' or 'well known' techniques … mean that individual process steps are known generally, not that they are known in the present context or combination."
• The etch‑stop/handle scheme is described as ordinary: oxidize bulk silicon at 1100 °C, bond a wafer "by direct interdiffusion," thin by "lapping followed by a chem‑mechanical polish," use "well‑known patterning and etching techniques."
• KOH/NaOH silicon etching with SiO₂ as a stop, and wax mounting on a sapphire base, are all recited as known expedients.

Under KSR, a recitation of known elements performing their known functions with predictable results, plus an admitted commercial availability of the starting material, is the paradigm of obviousness.

2. The prior art of record — dates and status

2A. Page-listed references (examiner‑cited)

Non‑patent citations: Hayashi et al., CUBIC (Cumulatively Bonded IC) Devices Stacking Thin Film Dual‑CMOS Functional Blocks, Semiconductor International, Dec. 1991 (§ 102(b)) — stacking and interconnecting thin‑film functional blocks; Liu (IBM TDB, May 1977); Patent Abstracts of Japan vol. 13/270 (JP,A,01 061 056, NEC) and vol. 16/79 (JP,A,03 266 478, Fujitsu).

2B. IPR references (not on the page)

3. Combination #1 (page-listed art): Harris '343 + NEC '083 (+ Goesele '723)

This is the strongest combination built entirely from the references on the page, and it maps onto claims 1–8 and 13–18 almost element‑for‑element.

3.1 Harris, US 5,034,343 — what it actually says (verified full text)

• Device wafer 10 (single‑crystal silicon) bonded to handle wafer 20 by a bonding oxide layer 30 (1–3 µm); oxide may be formed on either bonding surface.
• "The device wafer 10 is then thinned to less than 7 mils and is generally in the range of 2 to 6 mils"; handle 20 is "in the range of 19 to 25 mils" (≈483–635 µm).
• "An epitaxial silicon layer 15 of opposite conductivity type N is grown on the surface of P device wafer 10 for device formation … Device formation and isolation steps are performed on the exposed surface 12 of the epitaxial layer 15."
• "Once the device processing is concluded, the handling wafer 20 … is removed. This includes grinding … until a substantial portion of the handle wafer 20 has been removed. The remaining portion is then removed by etching down to the bonding oxide layer 30 which acts as an etching stop."
• To make SOI, a third device wafer is bonded and thinned, with the buried oxide becoming part of the isolation.

3.2 NEC, US 4,612,083 — what it actually says (verified full text / claims)

• A process for a 3‑D device by "first preparing two or more multilayer structures each having at least one semiconductor element formed therein and thereafter integrally uniting the multilayer structures together while providing electrical connections between the semiconductor elements."
• Claim 8 recites a first and second semiconductor structure, each with a functional layer containing a semiconductor element, an insulating layer, an insulating adhesive layer (claim 14: "a polyimide resin"), and conductors extending through the insulating/adhesive layers with exposed surface portions substantially flush with the adhesive surface.
• Step (5): heat "at a temperature which will substantially not affect the performance characteristics of the semiconductor element" to thermally fuse the adhesive layers with the elements electrically connected.
• Step (6): "removing the substrate from said second semiconductor structure for allowing said third conductor to be exposed at one end thereof," where the third conductor "extend[s] through said second functional layer and [is] electrically connected at one end to the semiconductor element … the other end thereof located at the interface between the substrate and the second functional layer and being electrically isolated from said second functional layer."
• Distinguished prior art (Kawamura's laser‑crystallized polysilicon stacking; Etchells' thermomigration feed‑throughs) — NEC frames its contribution as low‑temperature bonding so as not to disturb already‑formed devices, plus parallelizable processing and stage‑by‑stage inspectability.

3.3 Element chart for claim 1

Claim 1 is met by Harris '343 in view of NEC '083. Motivation: NEC's own stated object is that already‑fabricated semiconductor elements must not be disturbed by the joining step; Harris supplies precisely the "handle + buried etch‑stop" architecture that lets you join, handle, and then strip a support without touching the device face. Both are in the same art (semiconductor wafer processing), seek the same ends (thin/stacked active layers with intact devices), and their combination is a rearrangement of known parts with no change in principle of operation (KSR; Sakraida).

3.4 Dependent claims

4. Combination #2 (actual IPR grounds, IPR2015‑01201): Morimoto + Bertin (+ Oldham, Ying)

The Board's institution order in IPR2015‑01201 recites:

• claims 1, 6, 7, 10, 11 — § 102 anticipated by Bertin;
• claims 5, 12, 13 — § 103 obvious over Bertin + Morimoto;
• claim 9 — § 103 obvious over Bertin + Ying;
• claims 1, 2, 4, 5, 10, 13, 14, 16, 17 — § 103 obvious over Morimoto;
• claims 8, 18 — § 103 obvious over Morimoto + Oldham;
• claims 3, 15 — § 103 obvious over Morimoto + Bertin.

The Federal Circuit describes Morimoto (JP 64‑18248, 1989) as disclosing a multi‑layer semiconductor manufacturing method in which a "supporting silicon substrate" is bonded to an insulating film, further steps are performed, and then "removing the supporting silicon substrate" — i.e., a temporary handle removed after device formation, which is the core of independent claims 1/11/13. Bertin (US 5,202,754) discloses a "fabrication method and resultant three‑dimensional multichip package" containing several layers of silicon‑based material — supplying the Si/SiO₂/single‑crystal‑Si limitations of claims 5/12 and the stacked‑package context of claims 6/11.

Motivation: Raytheon did not contest that Bertin and Morimoto collectively disclose every limitation of the claims or that a skilled artisan would be motivated to combine them; the only dispute was whether Bertin qualified as prior art under § 102(e) (inventor's alleged prior reduction to practice), which Raytheon lost. That concession is itself strong evidence the combination is technically sound.

5. Combination #3 (actual IPR grounds, IPR2016‑00209): Liu + Riseman / Oldham / Wen / Black

The Board's institution order in IPR2016‑00209 (and the substantively identical Samsung petition joined in IPR2016‑00962):

Liu's disclosure (verified text) is decisive on several elements: the CCD layers 8/10 are bonded to support 12 by a sealing layer 14 which is "a bonding material such as a non‑conducting epoxy or bonding alloy"; and in a third embodiment "support 12 is a GaAs or Si chip, having its own circuit for signal conditioning and amplification already fabricated and with appropriate connecting pads aligned to the corresponding pads on circuit layer 10" — a second substrate containing a second circuit element with aligned electrical contacts (claims 6 and 7), attached by epoxy (claim 8). The substrate 18 is removed after the layer transfer.

The Federal Circuit affirmed the Board's Liu‑based obviousness findings for claims 5 and 13–18, rejecting Raytheon's "teaching away/inoperability" argument about silicon in a GaAs CCD. Two holdings are worth quoting for their § 103 significance:

• "[A] modification to a prior art reference that makes the resulting structure less efficient or less desirable does not necessarily result in inoperability or a teaching away."
• "Liu's statement that silicon can hamper performance in CCDs for 'some specific applications' — i.e., for star sensors — does not teach away from using silicon in CCDs for other applications."

That is the KSR/In re Fulton principle: an artisan's preference in one narrow use does not remove the reference from the prior art for other uses.

6. Why a person of ordinary skill would have combined these references

The motivations are concrete, contemporaneous, and mostly stated inside the references themselves:

1. The problem was known and articulated. The '678 background concedes that stacking 2‑D devices into 3‑D structures was desirable; NEC '083's second paragraph opens with precisely that framing (integration density limited by design‑rule reduction). Hayashi's CUBIC paper (Dec. 1991) shows the industry was already stacking thin‑film CMOS functional blocks. Same problem ⇒ same field ⇒ combinable.
2. The references supply the missing pieces for each other. Harris '343 supplies the handle/buried‑oxide/burn‑back‑to‑etch‑stop recipe; NEC '083 supplies the permanent second substrate with its own circuitry and aligned conductors plus low‑temperature adhesive joining; Morimoto supplies temporary‑support‑substrate bonding and removal; Liu supplies epoxy bonding and a second chip with own circuitry disposed on pads.
3. Known technique used to improve a similar device in the same way (KSR): thinning a wafer by lapping/polishing and stopping on a buried oxide was standard SOI practice (Goesele '723; Harris '343). Applying it to the transferred‑device context is a predictable application, not an inventive leap.
4. Predictable results, finite number of identified solutions. The claimed parameter space (etchant selectivity, epoxy vs. polyimide adhesive, etch‑stop material, temporary carrier material) is small and the results are predictable — the claimed KOH/NaOH + SiO₂ pairing is the textbook pair, and sapphire/molybdenum/glass carriers are enumerated in the art itself.
5. Non‑disturbance of finished devices is the explicit design constraint in both NEC '083 and the '678 patent, giving a strong reason to adopt adhesive, low‑temperature joining.
6. Reasonable expectation of success. Every step was individually performed in the same industry on the same substrates; the Board found all steps present in single references (Liu alone anticipated claims 1–4, 6, 7, 10, 11).

7. Anticipated § 103 counterarguments, and why they failed

8. Litigation/administrative record (per the page + verified decisions)

• E.D. Tex.: Raytheon v. Sony, No. 2:15‑cv‑00342; Raytheon v. Samsung, No. 2:15‑cv‑00341.
• IPRs: IPR2015‑01201 (Sony, filed 2015‑05‑14; instituted 2015‑12‑02; FWD 2016‑11‑30); IPR2016‑00209 (Sony, filed 2015‑11‑18; instituted 2016‑03‑29; FWD 2016‑11‑30); IPR2016‑00739 (Samsung); IPR2016‑00962 (Samsung, joined to 209). All four FWDs: claims 1–18 unpatentable.
• CAFC Nos. 17‑1554, 17‑1556, 17‑1557 — affirmed 2018‑04‑02 (non‑precedential).
• IPR certificates (K1) issued 2019‑05‑31 covering all four trial numbers; Google Patents lists two certificate entries (2019‑06‑04, 2020‑06‑02) with the same effective date.
• The page's "Anticipated expiration: 2014‑01‑07" reflects a 17‑year term from the 1997‑01‑07 grant (pre‑URAA), consistent with a pre‑GATT patent — and, given the IPR certificates, is a status artifact rather than evidence of surviving claims.

9. Honesty / confidence caveats

• High confidence: the identity of the IPR grounds and reference numbers; that all 18 claims were held unpatentable; that the Fed. Cir. affirmed; the full texts of US 4,612,083, US 5,034,343, and US 4,422,091 (all quoted above from retrieved primary PDFs/text).
• Moderate confidence: the exact internal mapping the Board used to read "etch‑stop layer" onto Liu and Morimoto. I did not retrieve the full FWD body text; my account of the grounds comes from the institution orders and the Federal Circuit opinion, and my rationale for how each element maps is my own reconstruction, not a verbatim quote from the Board. Treat the element chart in § 3 as my analysis; treat the ground tables in §§ 4–5 as record.
• Low confidence / not verified in this session: the full disclosures of US 5,024,723 (Goesele), US 4,829,018 (Wahlstrom), US 4,106,050 (Riseman), US 4,681,718 (Oldham), US 3,846,198 (Wen), US 4,426,768 (Black), Morimoto JP 64‑18248, and Bertin US 5,202,754. My § 3 treatment of Goesele and Wahlstrom rests on their titles/abstracts and general knowledge; my §§ 4–5 treatment rests on the PTAB/CAFC record rather than my own reading of those documents. Verify before relying on them in a filing.
• Two anomalies in the printed document that I am flagging rather than correcting, per the literal‑interpretation rule: (a) claim 17 recites "from about 30 nanometers to about micrometers" — the upper numeric bound is missing (the specification says "about 30 nanometers to 50 micrometers"), a literal‑reading indefiniteness defect; (b) the specification has internal reference‑numeral inconsistencies ("wafer layer 45" vs. 46; "interconnects 55 and 55′" vs. "56 and 56′"; "indirect front‑side interconnects 96" vs. 56). Neither changed the outcome, but both are proper § 112 discussion points.