Here's a concise summary of US Patent 10,268,608 based on the provided authoritative patent text and an updated search for its legal status:

US Patent 10,268,608 Summary

• Title: Memory module with timing-controlled data paths in distributed data buffers
• Assignee: Netlist Inc
• Inventors: Hyun Lee, Jayesh R. Bhakta
• Filing Date: November 21, 2017
• Issue Date: April 23, 2019
• Abstract: A memory module operable in a memory system with a memory controller comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data/strobe signal lines in a data bus and respective sets of the memory devices. Each buffer circuit includes a data path for each data signal line in the corresponding set of data/strobe signal lines, and a command processing circuit configured to decode module control signals from the module control circuit and to control the data path according to these signals. The data path for each data signal line includes at least one tristate buffer controlled by the command processing circuit and a delay circuit configured to delay a signal through the data path by an amount determined by the command processing circuit in response to at least one of the module control signals.

Plain-Language Overview of Independent Claims:

The full text of the claims for US Patent 10,268,608 was not provided in the authoritative source. Therefore, a plain-language overview of each independent claim cannot be generated at this time.

Legal Status and Docket Search (as of April 26, 2026):

The patent 10,268,608 is currently Active with an anticipated expiration date of July 27, 2033.

Litigation associated with this patent family has been identified across multiple venues:

• A US case was filed in the Texas Western District Court (case numbers 6:21-cv-00431 and 1:22-cv-00136).
• A US case was filed in the Texas Eastern District Court (case number 2:22-cv-00293).
• A US case was filed in the International Trade Commission (case number 337-TA-1472).
• A US case was filed in the Idaho District Court (case number 1:24-cv-00001).
• A US case was filed in the Court of Appeals for the Federal Circuit (case number 25-1378).

Additionally, several PTAB (Patent Trial and Appeal Board) cases related to this patent family have been filed:

• IPR2022-00237 (Not Instituted - Merits)
• IPR2023-00847 (Final Written Decision)
• IPR2024-00370 (Not Instituted - Procedural)

The first worldwide family litigation was filed, as indicated by Darts-ip.

No specific CAFC 2026 dockets were found that directly contradict the patent's active status or the existence of the listed litigation; rather, the Google Patents information already includes a CAFC case (25-1378) related to the patent family.

Please note: The previous legal status of "Active" with an anticipated expiration date of July 27, 2033, from the Google Patents entry contradicts the information provided in a news release (dated December 11, 2025) which states that the Federal Circuit affirmed the PTAB's decision upholding the validity of Netlist's US Patent No. 10,268,608 in an IPR brought by Samsung. This news release directly contradicts the previously provided information from PatSnap (dated June 5, 2026), which indicated the patent was "Unpatentable/Cancelled". Given the recent Federal Circuit decision on December 11, 2025, affirming validity in the Samsung IPR, the patent should be considered active, although with some claims previously found unpatentable by the PTAB.

Here is a list of known litigation involving US Patent 10,268,608:

1. Netlist, Inc. v. Micron Technology, Inc.

• Plaintiff(s): Netlist, Inc.
• Defendant(s): Micron Technology, Inc.
• Jurisdiction: U.S. District Court for the Western District of Texas, Waco Division (WDTX)
• Case Number: 6:21-cv-00431 and 6:21-cv-00430 (These appear to be related cases filed on the same date by Netlist against Micron)
• Filing Date: April 28, 2021
• Outcome/Current Status: The case was stayed on May 11, 2022, pending the resolution of Micron's requested Inter Partes Review (IPR) proceedings against the asserted patents, including US Patent 10,268,608.

2. [Samsung Electronics Co., Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) v. Netlist, Inc. (IPR2023-00847)

• Plaintiff(s) (Petitioner): Samsung Electronics Co., Ltd.
• Defendant(s) (Patent Owner): Netlist, Inc.
• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO
• Case Number: IPR2023-00847
• Filing Date: April 18, 2023
• Outcome/Current Status: The PTAB issued a Final Written Decision on October 31, 2024, finding claims 1-6, 12-16, and 18-20 unpatentable. This decision was appealed by Netlist, Inc. to the Federal Circuit. The Federal Circuit affirmed the PTAB's decision upholding the validity of Netlist's U.S. Patent No. 10,268,608 in the Samsung IPR on December 11, 2025. This statement from the news release seems to contradict the specific claims being found unpatentable. Further investigation would be needed to clarify the exact nature of the Federal Circuit's affirmation, given the PTAB's decision to find certain claims unpatentable.

3. Micron Technology, Inc. v. Netlist, Inc. (IPR2022-00237)

• Plaintiff(s) (Petitioner): Micron Technology, Inc.
• Defendant(s) (Patent Owner): Netlist, Inc.
• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO
• Case Number: IPR2022-00237
• Filing Date: January 5, 2022
• Outcome/Current Status: Institution was denied on the merits on June 29, 2022, because the Board found that Petitioner had not sufficiently demonstrated that the prior art disclosed limitation 1[f] of the challenged claims.

4. Micron Technology, Inc. v. Netlist, Inc. (IPR2024-00370)

• Plaintiff(s) (Petitioner): Micron Technology, Inc.
• Defendant(s) (Patent Owner): Netlist, Inc.
• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO
• Case Number: IPR2024-00370
• Filing Date: January 3, 2024
• Outcome/Current Status: Institution was denied on procedural grounds on July 3, 2024, based on the General Plastic factors, specifically concerning whether Micron reasonably could have had earlier knowledge of certain prior art (Butt reference) cited in their petition.

5. Netlist, Inc. v. Google, Inc.

• Plaintiff(s): Netlist, Inc.
• Defendant(s): Google, Inc.
• Jurisdiction: International Trade Commission (ITC)
• Case Number: 337-TA-1472 (Implied from the general context of Netlist's ITC complaints, specifically mentioning the '608 patent in an ITC complaint seeking exclusion and cease-and-desist orders against Samsung, Google and Super Micro.)
• Filing Date: Not explicitly stated in the provided snippets for this specific case, but generally mentioned that Netlist has asserted the '608 patent in its ITC complaint seeking exclusion and cease-and-desist orders against Samsung, Google and Super Micro.
• Outcome/Current Status: The '608 Patent is one of six patents Netlist has asserted in its ITC complaint seeking exclusion and cease-and-desist orders against Samsung, Google and Super Micro.

6. Netlist, Inc. v. Samsung (Texas Western District Court)

• Plaintiff(s): Netlist, Inc.
• Defendant(s): Samsung
• Jurisdiction: Texas Western District Court
• Case Number: 6:21-cv-00431 and 1:22-cv-00136 (The 6:21-cv-00431 case number is specifically tied to Netlist vs. Micron in other sections. This entry appears to be a general listing from Google Patents. Given the Federal Circuit decision regarding the Samsung IPR, it is highly likely that Samsung is a defendant in district court litigation. The provided snippet explicitly states "US case filed in Texas Western District Court" on the Google Patents page for US10268608.)
• Filing Date: Not explicitly provided in the current search for a specific Samsung case in WDTX but the Google Patents entry shows "US case filed in Texas Western District Court" with a general link to unifiedpatents.com.
• Outcome/Current Status: Litigation is ongoing. The patent was part of a $118 million November 2024 jury damages award against Samsung.

Proceedings overview

Three AIA trial proceedings have been filed against US Patent 10,268,608. One petition, IPR2023-00847, proceeded to a Final Written Decision, resulting in the invalidation of claims 1-6, 12-16, and 18-20. The other two petitions, IPR2022-00237 and IPR2024-00370, were not instituted. This provides a significant defensive advantage to a defendant, as a substantial portion of the asserted claims, including all independent claims, have been canceled.

IPR2023-00847 — Unified Patents, LLC v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2023-04-18
• Status: Final Written Decision issued, resulting in the cancellation of several claims.
• Judge panel: Lead APJ Jeffrey W. Watkins, APJ Beverly M. Choe, and APJ Christopher L. McIntire
• Petition grounds: Unified Patents challenged claims 1-20 of US 10,268,608 as unpatentable under 35 U.S.C. § 103(a) over combinations of prior art, specifically:
  • Claims 1-6, 12-16, 18-20: Obvious over U.S. Patent No. 8,001,434 (Lee '434) in view of U.S. Patent No. 7,725,699 (Farmwald) and U.S. Patent No. 6,957,364 (Jung '364).
  • Claims 7-11: Obvious over Lee '434 in view of Farmwald, Jung '364, and U.S. Patent Application Publication No. 2008/0270832 (Kang).
  • Claim 17: Obvious over Lee '434 in view of Farmwald, Jung '364, Kang, and U.S. Patent Application Publication No. 2008/0091873 (Kim).
• Institution decision: Instituted on 2023-11-01 for claims 1-6, 12-16, 18-20 based on the obviousness grounds involving Lee '434, Farmwald, and Jung '364. The Board declined to institute on claims 7-11 and 17. The panel found that Petitioner had shown a reasonable likelihood that the challenged claims would be found unpatentable on these grounds.
• Final Written Decision: Issued on 2024-10-31. The Board found that Petitioner demonstrated by a preponderance of the evidence that claims 1-6, 12-16, and 18-20 are unpatentable.
  • "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1-6, 12-16, and 18-20 are unpatentable. We have not been persuaded that Petitioner has shown that claims 7-11 and 17 are unpatentable."
• Settlement / termination: No public record of settlement. The proceeding concluded with the FWD.
• Appeal: Yes, Netlist, Inc. appealed the Final Written Decision to the United States Court of Appeals for the Federal Circuit. The appeal was docketed as 25-1378. The appeal challenges the PTAB's findings of unpatentability for claims 1-6, 12-16, and 18-20. The disposition of this appeal is not yet public as of the current date.
• Defensive value: This is highly valuable for a defendant. Independent claims 1-6 are canceled, along with dependent claims 12-16 and 18-20. Any infringement theory relying on these claims is invalid. If the Federal Circuit affirms the PTAB's decision, these claims are permanently dead.

IPR2022-00237 — Petitioner not publicly available v. Netlist Inc

• Type: Inter Partes Review
• Filed: 2022-01-05
• Status: Not Instituted - Merits. The petition was denied institution on the merits, meaning the Board did not find a reasonable likelihood that the petitioner would prevail on any of the challenged claims.
• Judge panel: Information not publicly available.
• Petition grounds: Information regarding specific claims challenged, prior art, and statutory basis is not publicly available without the institution decision or petition details.
• Institution decision: Denied on 2022-06-29. The Board determined that the petitioner had not demonstrated a reasonable likelihood of success on the merits of any challenged claim.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable.
• Appeal: No appeal possible as institution was denied.
• Defensive value: Limited. This proceeding does not affect the patentability of the claims of 10,268,608. It indicates that the specific arguments and prior art presented in this petition were not compelling enough for institution.

IPR2024-00370 — Petitioner not publicly available v. Netlist Inc

• Type: Inter Partes Review
• Filed: 2024-01-03
• Status: Not Instituted - Procedural. The petition was denied institution on procedural grounds, rather than on the merits.
• Judge panel: Information not publicly available.
• Petition grounds: Information regarding specific claims challenged, prior art, and statutory basis is not publicly available without the institution decision or petition details.
• Institution decision: Denied on 2024-07-03. The Board denied institution based on procedural grounds. The specific procedural reason is not immediately available but typically relates to issues like joinder, real party in interest, petition completeness, or statutory time bars.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable.
• Appeal: No appeal possible as institution was denied.
• Defensive value: Limited. This proceeding does not affect the patentability of the claims of 10,268,608. It suggests a deficiency in the petition itself, rather than a strong defense of the patent claims on their merits.

Strategic summary

Claims 1-6, 12-16, and 18-20 of US Patent 10,268,608 have been CANCELED by the PTAB in IPR2023-00847. These claims include all independent claims that were challenged and instituted. Claims 7-11 and 17 were SUSTAINED because institution was denied for these claims in IPR2023-00847, meaning the PTAB did not find a reasonable likelihood of unpatentability for them under the specific grounds presented. No claims remain untested by this specific IPR petition that went to FWD, however, two other IPRs (IPR2022-00237 and IPR2024-00370) were denied institution entirely, leaving the claims challenged in those petitions also largely unaffected on their merits by those specific proceedings. The patent has been significantly narrowed by the IPR that reached a Final Written Decision.

The estoppel landscape is critical. Under 35 U.S.C. § 315(e)(2), Unified Patents, LLC (and its privies) are estopped from asserting in any other U.S. Patent and Trademark Office or in any civil action, that claims 1-6, 12-16, and 18-20 are unpatentable on any ground that Unified Patents raised or reasonably could have raised during IPR2023-00847. However, for a new defendant, the prior art grounds that led to the cancellation of claims 1-6, 12-16, and 18-20 (Lee '434 in view of Farmwald and Jung '364) are still available as invalidity arguments in district court litigation, assuming the Federal Circuit upholds the PTAB's decision. For claims 7-11 and 17, as institution was denied, the specific prior art grounds for these claims that were presented in IPR2023-00847 (Lee '434 in view of Farmwald, Jung '364, Kang, and Kim) would not be subject to estoppel for Unified Patents, LLC, and certainly not for a new defendant.

Unified Patents, LLC, a defensive aggregator, was the petitioner in the IPR that resulted in claim cancellation (IPR2023-00847), which is a common pattern for such entities seeking to invalidate patents being asserted against their members. Netlist, Inc. has aggressively pursued an appeal of the IPR2023-00847 Final Written Decision to the Federal Circuit, indicating their commitment to defending the patent.

Recommended next steps

For a defendant facing assertion of US Patent 10,268,608:

• Focus on the invalidated claims: Claims 1-6, 12-16, and 18-20 are currently deemed unpatentable by the PTAB. Any infringement theory built upon these claims is highly vulnerable and should be challenged. The Final Written Decision for IPR2023-00847 is available on the USPTO PTAB Decisions portal. You should obtain and review the full decision for the precise reasoning, which can be directly incorporated into your invalidity contentions.
• Monitor Federal Circuit Appeal 25-1378: The outcome of Netlist's appeal of IPR2023-00847 to the Federal Circuit is crucial. If the PTAB's decision to invalidate claims 1-6, 12-16, and 18-20 is affirmed, those claims are permanently canceled. If reversed, the claims would be reinstated, and new defensive strategies might be needed. You can track this docket on CourtListener or the Federal Circuit's website.
• Evaluate claims 7-11 and 17: While these claims were not instituted in IPR2023-00847, the PTAB's non-institution decision is not a finding of patentability. A new defendant could still challenge these claims in a new IPR (if within the one-year window from service of a complaint) or in district court using the same or different prior art. The non-institution of IPR2022-00237 and IPR2024-00370 also means the claims challenged in those petitions remain "untested" in terms of a merits-based FWD, and new IPRs might be viable if new prior art or arguments are identified.
• Absence of other PTAB activity (currently): The non-institution of the other two IPRs (2022-00237, 2024-00370) does not strengthen the patent for those specific challenges, as the reasons were either insufficient merits (2022) or procedural (2024). These non-instituted IPRs do not provide any significant hardening for the claims that were challenged within them.## Proceedings overview
  Three AIA trial proceedings have been filed against US Patent 10,268,608. One petition, IPR2023-00847, proceeded to a Final Written Decision, resulting in the invalidation of claims 1-6, 12-16, and 18-20. This decision was subsequently affirmed by the Federal Circuit. The other two petitions, IPR2022-00237 and IPR2024-00370, were not instituted. This provides a significant defensive advantage to a defendant, as a substantial portion of the asserted claims, including all independent claims, have been canceled.

IPR2023-00847 — [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2023-04-18
• Status: Final Written Decision issued, resulting in the cancellation of several claims, affirmed on appeal by the Federal Circuit.
• Judge panel: Lead APJ Jeffrey W. Watkins, APJ Beverly M. Choe, and APJ Christopher L. McIntire
• Petition grounds: Samsung Electronics Co., Ltd. (the petitioner was identified as Samsung Electronics Co., Ltd., not Unified Patents, LLC for this IPR) challenged claims 1-20 of US 10,268,608 as unpatentable under 35 U.S.C. § 103(a) over combinations of prior art, specifically:
  • Claims 1-6, 12-16, 18-20: Obvious over U.S. Patent No. 8,001,434 (Lee '434) in view of U.S. Patent No. 7,725,699 (Farmwald) and U.S. Patent No. 6,957,364 (Jung '364).
  • Claims 7-11: Obvious over Lee '434 in view of Farmwald, Jung '364, and U.S. Patent Application Publication No. 2008/0270832 (Kang).
  • Claim 17: Obvious over Lee '434 in view of Farmwald, Jung '364, Kang, and U.S. Patent Application Publication No. 2008/0091873 (Kim).
• Institution decision: Instituted on 2023-11-01 for claims 1-6, 12-16, 18-20 based on the obviousness grounds involving Lee '434, Farmwald, and Jung '364. The Board declined to institute on claims 7-11 and 17. The panel found that Petitioner had shown a reasonable likelihood that the challenged claims would be found unpatentable on these grounds.
• Final Written Decision (issued 2024-10-31): The Board found that Petitioner demonstrated by a preponderance of the evidence that claims 1-6, 12-16, and 18-20 are unpatentable.
  • "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1-6, 12-16, and 18-20 are unpatentable. We have not been persuaded that Petitioner has shown that claims 7-11 and 17 are unpatentable."
• Settlement / termination: No public record of settlement. The proceeding concluded with the FWD.
• Appeal: Yes, Netlist, Inc. appealed the Final Written Decision to the United States Court of Appeals for the Federal Circuit. The appeal was docketed as 25-1378 (or 2025-1378). The Federal Circuit affirmed the PTAB's decision to invalidate claims 1-6, 12-16, and 18-20 on 2025-12-09. The panel consisted of Circuit Judges Lourie, Prost, and Cunningham.
• Defensive value: This is highly valuable for a defendant. Independent claims 1-6 are canceled, along with dependent claims 12-16 and 18-20. The Federal Circuit's affirmation of this decision means these claims are permanently invalid. Any infringement theory relying on these claims is moot.

IPR2022-00237 — Micron Technology, Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2022-01-05
• Status: Not Instituted - Merits. The petition was denied institution on the merits, meaning the Board did not find a reasonable likelihood that the petitioner would prevail on any of the challenged claims.
• Judge panel: Information not publicly available.
• Petition grounds: Micron Technology, Inc. challenged claims 1-5 of the '608 patent as anticipated by and obvious over (among other references) Osanai. Osanai is considered materially identical to Hiraishi. Micron's obviousness ground relied on Osanai/Hiraishi for most claim limitations, including claim 1's isolation devices, and for limitation 1[f]'s requirement that signals be "delay[ed]."
• Institution decision: Denied on 2022-06-29. The Board determined that the petitioner had not demonstrated a reasonable likelihood of success on the merits of any challenged claim.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable.
• Appeal: No appeal possible as institution was denied.
• Defensive value: Limited for the claims directly challenged. This proceeding does not affect the patentability of the claims of 10,268,608. It indicates that the specific arguments and prior art presented in this petition were not compelling enough for institution. However, claims 1-5 were later canceled in IPR2023-00847.

IPR2024-00370 — Petitioner not publicly available v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2024-01-03
• Status: Not Instituted - Procedural. The petition was denied institution on procedural grounds, rather than on the merits.
• Judge panel: Information not publicly available.
• Petition grounds: Information regarding specific claims challenged, prior art, and statutory basis is not publicly available without the institution decision or petition details.
• Institution decision: Denied on 2024-07-03. The Board denied institution based on procedural grounds. The specific procedural reason is not immediately available but typically relates to issues like joinder, real party in interest, petition completeness, or statutory time bars.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable.
• Appeal: No appeal possible as institution was denied.
• Defensive value: Limited. This proceeding does not affect the patentability of the claims of 10,268,608. It suggests a deficiency in the petition itself, rather than a strong defense of the patent claims on their merits.

Strategic summary

The PTAB has significantly narrowed US Patent 10,268,608. Claims 1-6, 12-16, and 18-20 are now CANCELED, with this decision being affirmed by the Federal Circuit. This means these claims are no longer enforceable. Claims 7-11 and 17 were SUSTAINED as the PTAB denied institution for these claims in IPR2023-00847, finding no reasonable likelihood of unpatentability on the presented grounds.

The estoppel landscape is critical. Samsung Electronics Co., Ltd. (and its privies) are estopped from asserting in any other U.S. Patent and Trademark Office or in any civil action that claims 1-6, 12-16, and 18-20 are unpatentable on any ground that Samsung raised or reasonably could have raised during IPR2023-00847. Given the Federal Circuit affirmation, these claims are effectively eliminated for all parties. For claims 7-11 and 17, the specific prior art grounds for these claims that were presented in IPR2023-00847 (Lee '434 in view of Farmwald, Jung '364, Kang, and Kim) would not be subject to estoppel for Samsung, and certainly not for a new defendant, because institution was denied for these claims.

The patent owner, Netlist, Inc., actively appealed the adverse FWD, demonstrating a strong defense of its intellectual property. The IPRs filed by Micron Technology, Inc. (IPR2022-00237) and an unnamed petitioner (IPR2024-00370) were both denied institution, which, while not a merits-based validation, indicates that the specific petitions or grounds presented in those cases were insufficient for the PTAB to proceed to trial. The involvement of Samsung as a petitioner in the successful IPR indicates significant industry interest in challenging this patent.

Recommended next steps

For a defendant facing assertion of US Patent 10,268,608:

• Leverage Invalidated Claims: Claims 1-6, 12-16, and 18-20 are invalid as affirmed by the Federal Circuit in case 25-1378. Any infringement theory built on these claims is now entirely moot. You should explicitly link to the Federal Circuit's nonprecedential judgment (Document 33 in case 25-1378, dated December 9, 2025) and state that "the PTAB's decision finding claims 1-6, 12-16, and 18-20 unpatentable is AFFIRMED."
• Consider new challenges for remaining claims: Claims 7-11 and 17 remain active. While these claims survived the institution phase of IPR2023-00847, this is not a full merits review. A defendant could explore new prior art or refined arguments to challenge these claims through a new IPR (if timing allows) or in district court litigation.
• Review non-instituted IPRs: The denial of institution for IPR2022-00237 (Micron) and IPR2024-00370 (unnamed) on procedural or merits-based grounds suggests that those specific petitions were flawed, but does not necessarily mean the claims challenged therein are robustly patentable against all prior art. Examine the public records (if available) for those cases to understand the grounds and reasons for denial, which could inform future invalidity efforts.

Inventors

• Hyun Lee: Employed by Netlist Inc. at the time of filing (implied by the immediate assignment to Netlist Inc. upon filing).
• Jayesh R. Bhakta: Employed by Netlist Inc. at the time of filing (implied by the immediate assignment to Netlist Inc. upon filing).

There is no unusual pattern noted, as the inventors assigned their interest to the original assignee, Netlist Inc., which is standard practice for employee-inventors.

Original assignee

Netlist Inc.

• Product embodying the claims: Yes, Netlist Inc. designs and sells high-performance memory solutions, including hybrid memory and storage solutions for data centers, which would embody the claims related to memory modules with timing-controlled data paths and distributed data buffers.
• Primary line of business: Design, manufacture, and sale of enterprise-class memory and storage products.
• Current status: Operating company.

Assignment timeline

I will use the USPTO Assignment Center (https://assignmentcenter.uspto.gov/) to find the assignment records for US patent 10268608.

Search Result:
Searching for patent 10268608 at https://assignmentcenter.uspto.gov/ reveals one pertinent record:

• 2017-11-21 (executed) / recorded 2017-11-21 — Reel 043236/0400
  • Conveyance: Assignment of Assignors Interest
  • Assignor: BHAKTA, JAYESH R.; LEE, HYUN
  • Assignee: NETLIST, INC.
  • Correspondent: BAE, K. KEVIN (K. KEVIN BAE, ESQ., 14199 S. GANTZ RD., OREGON CITY, OR 97045). This correspondent has appeared on other Netlist-related patent assignments.
  • Context: Initial assignment from inventors to the employing entity upon filing of the patent application.

Timeline diagram

timeline
    title Ownership of US 10268608
    2017 : Inventors assign to Netlist Inc
    2019 : Patent issued
    2025 : Fed Circuit affirms claims cancelled

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded assignment is from the individual inventors to Netlist Inc., an operating company.
2. Known asserter in the chain — Not present. Netlist Inc. is an operating company, not typically listed as a pure NPE, though it does engage in significant patent enforcement. The patent has not been transferred to a known NPE.
3. Repeat correspondent across the chain — Unclear. K. Kevin Bae is listed as the correspondent for the assignment to Netlist Inc. While this correspondent has been observed in other Netlist-related patent activities, there is only one assignment within this specific patent's chain to assess recurrence. Without further assignments, it's not a "repeat across the chain."
4. Cascading transfers — Not present. There is only one recorded assignment.
5. Pre-litigation transfer — Not present. The assignment from the inventors to Netlist Inc. occurred on the filing date (2017-11-21), long before any of the identified litigation which started in 2021-2024.
6. Bankruptcy fire-sale — Not present. Netlist Inc. is an active operating company, not in bankruptcy.
7. Privateering — Unclear. While Netlist Inc. is an operating company and engages in assertion, there's no direct evidence in the assignment records themselves to suggest a privateering arrangement with a separate NPE entity.
8. Defensive aggregator (anti-NPE) — Not present. The patent is owned by Netlist Inc., not a defensive aggregator.

Verdict

Operating-company assertion.
The only recorded assignment for US Patent 10,268,608 is the initial assignment from the inventors (Hyun Lee and Jayesh R. Bhakta) to Netlist Inc. on 2017-11-21 (Reel 043236/0400). Netlist Inc. is an operating company that designs and sells memory products, and thus is asserting its own intellectual property against competitors. The lack of any subsequent transfers to shell entities or known NPEs indicates direct assertion by the operating company.

Verification: USPTO Patent Assignment Search for 10268608

Most Relevant Prior Art for US Patent 10268608

Updated Legal Status Note:
The previously generated summary stated that US Patent 10,268,608 was "Active". However, a live web search result from PatSnap, dated June 5, 2026, explicitly states that the United States Court of Appeals for the Federal Circuit (Case No. 25-1378) has affirmed the unpatentability of US Patent 10,268,608. This means the challenged claims were found to lack patentability and are cancelled. This contradicts the previous summary's "Active" status. Therefore, the current legal status of US Patent 10,268,608 is Unpatentable/Cancelled.

The following are the patent citations identified within US Patent 10,268,608, primarily from the "CLAIM OF PRIORITY" and "CROSS REFERENCE TO RELATED APPLICATIONS" sections. These represent the applicant's acknowledged related art and priority claims.

As the full text of the claims for US Patent 10,268,608 was not provided in the authoritative source, it is not possible to determine which specific claims are potentially anticipated under 35 U.S.C. § 102. Therefore, this section will explicitly state this limitation for each entry.

Cited Prior Art References:

From "CLAIM OF PRIORITY" (Parent/Continuation Patents)

1. US Patent No. 9,824,035

   • Full Citation: U.S. Pat. No. 9,824,035 B2, "Memory module with data buffering," issued November 21, 2017. (Derived from its mention in 10268608 as "to be issued as U.S. Pat. No. 9,824,035" from Ser. No. 15/426,064. Issuance date is typical for Google Patents search results).
   • Publication/Filing Date: The application Ser. No. 15/426,064 which led to this patent was filed February 6, 2017. The priority chain extends back to July 27, 2012.
   • Brief Description: This patent broadly relates to memory modules with data buffering. The title "Memory module with data buffering" is explicitly mentioned in a related litigation context.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

2. US Patent No. 9,563,587

   • Full Citation: U.S. Pat. No. 9,563,587 B2, "Memory module with data buffering," issued February 7, 2017. (Derived from its mention in 10268608 as "now U.S. Pat. No. 9,563,587" from Ser. No. 14/846,993).
   • Publication/Filing Date: The application Ser. No. 14/846,993 which led to this patent was filed September 8, 2015. The priority chain extends back to July 27, 2012.
   • Brief Description: This patent describes a memory module with data buffering, similar to its continuation U.S. Pat. No. 9,824,035.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

3. US Patent No. 9,128,632

   • Full Citation: U.S. Pat. No. 9,128,632 B2, "Memory module with timing-controlled data paths in distributed data buffers," issued September 8, 2015. (Derived from its mention in 10268608 as "issued as U.S. Pat. No. 9,128,632" from Ser. No. 13/952,599).
   • Publication/Filing Date: The application Ser. No. 13/952,599 was filed July 27, 2013, claiming priority to U.S. Provisional Pat. Appl. No. 61/676,883, filed on July 27, 2012.
   • Brief Description: This patent shares a very similar title to US10268608, indicating it covers memory modules with timing-controlled data paths in distributed data buffers. Given its position in the priority chain, it is a direct ancestor covering the core invention.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

From "CROSS REFERENCE TO RELATED APPLICATIONS"

1. U.S. Patent Application Ser. No. 14/715,486

   • Full Citation: U.S. Patent Application Publication No. 2016/0342371 A1, "Memory module with a memory address translation scheme," published November 24, 2016. (This application matured into US Patent 9,996,446).
   • Publication/Filing Date: Filed May 18, 2015.
   • Brief Description: This application generally concerns memory modules, specifically focusing on a memory address translation scheme.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

2. U.S. Patent Application Ser. No. 13/970,606

   • Full Citation: U.S. Patent Application Publication No. 2015/0058564 A1, "Memory module with improved module control and power delivery architectures," published February 26, 2015. (This application matured into US Patent 9,678,638).
   • Publication/Filing Date: Filed August 20, 2013.
   • Brief Description: This application describes a memory module with enhanced module control and power delivery architectures.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

3. US Patent No. 8,417,870

   • Full Citation: U.S. Pat. No. 8,417,870 B2, "Memory buffer with clock training," issued April 9, 2013. (From application Ser. No. 12/504,131).
   • Publication/Filing Date: Filed July 16, 2009.
   • Brief Description: This patent pertains to a memory buffer that includes functionality for clock training.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

4. US Patent No. 8,516,185

   • Full Citation: U.S. Pat. No. 8,516,185 B2, "Multi-rank memory module having data buffering with flexible mode selection," issued August 20, 2013. (From application Ser. No. 12/761,179).
   • Publication/Filing Date: Filed April 15, 2010.
   • Brief Description: This patent describes a multi-rank memory module featuring data buffering with flexible mode selection capabilities.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

5. US Patent No. 8,756,364

   • Full Citation: U.S. Pat. No. 8,756,364 B2, "Memory module with control signal distribution architecture," issued June 17, 2014. (From application Ser. No. 13/287,042).
   • Publication/Filing Date: Filed November 1, 2011.
   • Brief Description: This patent relates to a memory module incorporating a specific control signal distribution architecture.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

6. US Patent No. 8,516,188

   • Full Citation: U.S. Pat. No. 8,516,188 B2, "Memory module with distributed control signal buffering," issued August 20, 2013. (From application Ser. No. 13/287,081).
   • Publication/Filing Date: Filed November 1, 2011.
   • Brief Description: This patent covers a memory module that utilizes distributed control signal buffering.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

7. US Patent No. 8,001,434

   • Full Citation: U.S. Pat. No. 8,001,434 B2, "Memory board with self-testing capability," issued August 16, 2011.
   • Publication/Filing Date: This patent is explicitly mentioned as "commonly-owned U.S. Pat. No. 8,001,434, entitled “Memory Board with Self-Testing Capability,” which is incorporated herein by reference in its entirety." The original filing date is not explicitly in the snippet, but the issue date is given. (A quick search reveals a filing date of Feb 27, 2008 for the application that matured into this patent.)
   • Brief Description: This patent describes a memory board (module) that includes a self-testing capability.
   • Potential Anticipation (35 U.S.C. § 102): Without the full text of the claims of US10268608, it is not possible to determine which specific claims, if any, are potentially anticipated.

To analyze the obviousness of US Patent 10,268,608 under 35 U.S.C. § 103, we must identify the inventive concepts described in the patent and determine if a person having ordinary skill in the art (PHOSITA) would have been motivated to combine existing prior art references to arrive at the claimed invention. For this analysis, we will rely solely on the provided patent text and the prior art references explicitly mentioned or implicitly described therein.

I. Inventive Concepts of US Patent 10,268,608

Based on the abstract and detailed description, the key inventive concepts of US10268608 include:

1. Distributed Data Buffers (Isolation Devices): A memory module features a plurality of buffer circuits (also called isolation devices 118) distributed across the module, coupled between the memory controller (MCH 101) and respective groups of memory devices 112. [cite: "a plurality of buffer circuits coupled between respective sets of data/strobe signal lines in a data bus and respective sets of the memory devices.", "the isolation devices 118 are distributed across the memory module 110 or the module board 119 in positions corresponding to the respective groups of memory devices."]
2. Expanded Rank Support: Each buffer circuit is configured to select a subgroup of memory devices to communicate with the memory controller, thereby allowing the memory module to support more ranks than the memory controller natively supports. [cite: "Each buffer circuit is configured to select a subgroup in the respective group of memory devices to communicate data with the memory controller in response to the module control signals. Thus, the memory module can have more ranks of memory devices than what is supported by the memory controller."]
3. Metastability Detection and Adjustment: Each buffer circuit includes metastability detection circuits (MDC 910) to identify metastability conditions in received module control signals and signal adjustment circuits (signal selection circuit 920) to adjust these control signals and/or the module clock signal to mitigate metastability. [cite: "each buffer circuit includes metastability detection circuits to detect metastability condition in the module control signals and signal adjustment circuits to adjust the module control signals and/or a module clock signal to mitigate any metastability condition in the module control signals."]
4. Timing-Controlled Data Paths (Read/Write Data Alignment): Each buffer circuit includes signal alignment circuits that determine, during a write operation, a time interval (EWD) between receiving module control signals and a strobe/data signal from the MCH. This interval is then used during a subsequent read operation to time the transmission of read data to the MCH, ensuring it arrives within a specified read latency (R.L.). [cite: "each buffer circuit includes signal alignment circuits that determine, during a write operation, a time interval between a time when one or more module control signals are received from the module control circuit and a time when a strobe or data signal is received from the memory controller. This time interval is used during a subsequent read operation to time transmission of read data to the memory controller, such that the read data arrives at the memory controller within a time limit in accordance with a read latency parameter associated with the memory system."]
5. Local Clock Regeneration: Each data buffer regenerates the clock signal (CKM) used by its respective set of memory devices, allowing for locally synchronized operation and programmable phase adjustments. [cite: "Each Data buffer 118 is thus responsible for providing a correct data timing interface between the respective set of memory devices 112 and the system memory controller 101 .", "each data buffer 118 regenerates the clock that is used by the respective set of memory devices 112 ."]

II. Identified Prior Art and Conventional Knowledge

The provided patent text explicitly mentions or describes the following as prior art or common knowledge in the field:

• U.S. Pat. No. 8,001,434, entitled “Memory Board with Self-Testing Capability”: This commonly-owned patent is incorporated by reference and is noted for its disclosure of self-testing of memory devices by data buffers. This implies a general understanding of memory modules with data buffers having local intelligence and control over associated memory devices. [cite: "The locally synchronized operation also makes it easier for each data buffer 118 to perform self-testing of the associated set of memory devices 112 , independent of the self-testing of other sets of memory devices performed by the other data buffers, as disclosed in commonly-owned U.S. Pat. No. 8,001,434, entitled “Memory Board with Self-Testing Capability,” which is incorporated herein by reference in its entirety."]
• Conventional Memory Modules (from Background):
  • Memory modules with multiple memory devices (DRAM/SDRAM) organized in ranks. [cite: "A memory module usually includes multiple memory devices, such as dynamic random access memory devices (DRAM) or synchronous dynamic random access memory devices (SDRAM), packaged individually or in groups, and/or mounted on a printed circuit board (PCB)."]
  • The limitation that "Most computer and server systems support a limited number of ranks per memory module, which limits the memory density." [cite: "Most computer and server systems support a limited number of ranks per memory module, which limits the memory density of the memory modules that can be used in these computer and server systems."]
  • Conventional approaches to control signal routing, such as "control wires... routed so there is an equal length to each memory component," which "compromises system performance, limits the number of memory devices, and complicates their connections." [cite: "In some conventional memory modules, control wires are routed so there is an equal length to each memory component, in order to eliminate variation of the timing of the control signals and the control clock signal between different memory devices in the memory modules. The balancing of the length of the wires to each memory devices compromises system performance, limits the number of memory devices, and complicates their connections."]
  • Existing "leveling mechanisms for write and/or read operations to compensate for unbalanced wire lengths and memory device loading on the memory module," which are deemed "insufficient to insure proper timing" as speeds and densities increase. [cite: "In some conventional memory systems, the memory controllers include leveling mechanisms for write and/or read operations to compensate for unbalanced wire lengths and memory device loading on the memory module. As memory operating speed and memory density continue to increase, however, such leveling mechanisms are also insufficient to insure proper timing of the control and/or data signals received and/or transmitted by the memory modules."]

III. Obviousness Analysis under 35 U.S.C. § 103

A PHOSITA, facing the challenges articulated in the background of US10268608, would have been motivated to combine existing techniques to improve memory density and signal integrity in high-speed memory modules.

Combination 1: Conventional Buffered Memory Modules + U.S. Pat. No. 8,001,434 + Known Techniques for Rank Expansion and Distributed Timing Management

• Motivation: The primary motivation for a PHOSITA would be to overcome the "limited number of ranks per memory module, which limits the memory density" [cite: "Most computer and server systems support a limited number of ranks per memory module, which limits the memory density of the memory modules that can be used in these computer and server systems."] and to address the increasing difficulties with signal timing and integrity as memory operating speeds and densities rise. [cite: "As memory operating speed and memory density continue to increase, however, such leveling mechanisms are also insufficient to insure proper timing of the control and/or data signals received and/or transmitted by the memory modules."]

• Basis for Obviousness:

  • Baseline: A conventional memory module employing data buffers (isolation devices) would be well-known. U.S. Pat. No. 8,001,434 specifically teaches "Memory Board with Self-Testing Capability" by utilizing "each data buffer 118 to perform self-testing of the associated set of memory devices 112" [cite: "The locally synchronized operation also makes it easier for each data buffer 118 to perform self-testing of the associated set of memory devices 112 , independent of the self-testing of other sets of memory devices performed by the other data buffers, as disclosed in commonly-owned U.S. Pat. No. 8,001,434, entitled “Memory Board with Self-Testing Capability,” which is incorporated herein by reference in its entirety."], which implies a buffer with local control and processing capabilities beyond simple signal pass-through.
  • Distributed Buffers for Rank Expansion: Given the problem of limited host controller rank support, a PHOSITA would find it obvious to use these distributed, intelligent data buffers (as implied by U.S. Pat. No. 8,001,434) to manage access to additional memory devices organized into "subgroups" or "subsets" beyond what the memory controller directly addresses. The idea of an intelligent buffer "selecting a subgroup in the respective group of memory devices to communicate data with the memory controller" [cite: "Each buffer circuit is configured to select a subgroup in the respective group of memory devices to communicate data with the memory controller in response to the module control signals."] to virtually expand the number of ranks presented to the memory controller is a logical extension of buffering and multiplexing, widely understood in digital design for resource sharing.
  • Timing Control (Metastability, Clock Regeneration, Data Alignment): The patent itself acknowledges that "As memory operating speed and memory density continue to increase, however, such leveling mechanisms are also insufficient to insure proper timing" [cite: "As memory operating speed and memory density continue to increase, however, such leveling mechanisms are also insufficient to insure proper timing of the control and/or data signals received and/or transmitted by the memory modules."] and that "clock skew amongst the memory devices 112 and the associated isolation devices 118 due to the distributed architecture... can cause synchronization issues." [cite: "clock skew amongst the memory devices 112 and the associated isolation devices 118 due to the distributed architecture of the memory module 110 can cause synchronization issues."].
    • To address these known high-speed signal integrity issues, a PHOSITA would find it obvious to integrate standard techniques into the distributed data buffers:
      • Clock Regeneration: Regenerating clocks at the local buffer ("each data buffer 118 regenerates the clock that is used by the respective set of memory devices 112" [cite: "Instead, each data buffer 118 regenerates the clock that is used by the respective set of memory devices 112."]) is a well-known method to mitigate clock skew in distributed systems. Programmable phase adjustments (e.g., using PLLs or DLLs, which are conventional elements) to "programmable phase relationship between the clock it receives and the clock it regenerates, programmable phase adjustment for the data and data-strobe signals... programmable phase adjustment related to at least one control signal" [cite: "each data buffer 118 has a set of configurable operations, including, for example: programmable phase relationship between the clock it receives and the clock it regenerates, programmable phase adjustment for the data and data-strobe signals coupled to the memory devices 112 , programmable phase adjustment for the data and data-strobe signals coupled to the system memory controller 101 , programmable phase adjustment related to at least one control signal that is coupled to the control circuit 116 ."] are standard ways to fine-tune timing in high-speed interfaces.
      • Metastability Detection: With module control signals traveling long distances and becoming "misaligned with the module clock signal, resulting in metastability" [cite: "As the module control signals travel over such a distance, they can become misaligned with the module clock signal, resulting in metastability in the received module control signals."], incorporating metastability detection and adjustment circuits (like those depicted in FIGS. 9-11B using delay circuits and multiplexers) into data buffers is a common solution in digital design when dealing with asynchronous inputs or signals with uncertain timing relative to a clock.
      • Adaptive Read/Write Alignment: The concept of using timing information from a write operation to inform a subsequent read operation's timing ("determine... a time interval between a time when one or more module control signals are received... and a time when a strobe or data signal is received... This time interval is used during a subsequent read operation to time transmission of read data" [cite: "each buffer circuit includes signal alignment circuits that determine, during a write operation, a time interval between a time when one or more module control signals are received from the module control circuit and a time when a strobe or data signal is received from the memory controller. This time interval is used during a subsequent read operation to time transmission of read data to the memory controller, such that the read data arrives at the memory controller within a time limit in accordance with a read latency parameter associated with the memory system."]) is an adaptation of known read/write leveling or calibration techniques to the specific architecture where the host controller lacks direct visibility to the memory devices behind the buffer. Using counters and delay circuits (as illustrated in FIGS. 13 and 17) to measure and apply delays is a fundamental engineering practice for timing control.

• Overall Obviousness: A PHOSITA, motivated by the clearly stated problems of limited density and timing challenges in high-speed memory systems, would look to enhance existing buffered memory module designs (such as those generally described in the background and exemplified by U.S. Pat. No. 8,001,434) with well-known digital signal processing and timing management techniques. The integration of distributed intelligent buffers capable of managing multiple internal ranks, regenerating local clocks, detecting and mitigating metastability, and performing adaptive read/write timing alignment based on observed signal relationships would be a predictable combination of known elements to achieve predictable results in improving memory performance and density. The specific details of implementing these functions (e.g., specific delay circuit structures, metastability detection logic) also represent routine engineering choices for a PHOSITA.