US 10168233

I'll search for this specific patent number across USPTO and litigation sources.

Let me run a couple more targeted searches to check for any litigation or PTAB activity specific to this patent.

Let me do one final check for any PTAB proceedings or district court assertions of this exact patent.

US Patent 10,168,233 — Analyst Summary

Search scope note: I searched for the exact number 10,168,233 (and "10,168,233") across general web, patent aggregators, PTAB-hosted petition documents, and CAFC docket material. Search results for the numeric string are dominated by unrelated hits (a Colombian land-reform file, a Brazilian exam roster, a Lee County, FL property folio) — none patent-related. That is itself a finding I report below.

1. Bibliographic identification

Sources: Google Patents US10168233B2; FreePatentsOnline US2015/0330845; Justia US2015/0330845; Justia US11274977.

2. Abstract (verbatim)

"Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes."

3. Plain-language overview of the disclosure

The invention addresses a race / metastability problem when a DRAM reports chip temperature on demand.

The problem: A DRAM has a temperature sensor (52) driven by a free-running oscillator (51) whose cycle is ~16 ms in the described embodiment. Periodically the sensor re-measures temperature and, while doing so, its 3-bit output (TEMPOP) is temporarily undefined, signaled by a low-going monitoring signal TSREADY. Separately, an external mode register read command (MMRR) causes the DRAM to output that temperature data externally via a detection signal (COP). If the external read command happens to land at the same moment the sensor is updating its output, the DRAM could latch and export garbage.

The fix: The chip keeps two versions of the temperature word:

• A "fresh" copy (T1) latched the instant the sensor finishes (control signal TRAN).
• An "older/snapshot" copy (T2) captured earlier, at the start of the mode register read sequence (control signal MMRR1), via a delay circuit (55).

A selector (53), steered by a control signal (MMRRFAST) generated by an SR latch circuit (54), chooses between them. The SR latch is set by MMRR1 and reset by the sensor's monitoring signal TSREADY. In effect: if the external read request arrives while the sensor is mid-update (TSREADY low overlapping MMRR1 high), the selector switches to the safe, already-settled snapshot T2 instead of the possibly-undefined T1. If no such overlap exists, the fresh T1 is exported. A third latch (63) captures the selected word on the later control signal MMRR4. The specification walks through four timing scenarios (FIGS. 5–8) — including one (FIG. 8) where the selection window opens only after the export latch has already closed, in which case T1 is used and nothing is corrupted.

The specification notes the technique applies to "physical quantity sensors" generally, not just temperature, and that the device "is a DRAM" though SRAM/ReRAM/flash/CPU/DSP are contemplated.

4. Independent claim — plain-language reading

Only claim 1 is independent. The remaining 13 claims all depend (directly or indirectly) on claim 1, so claim 1 defines the enforceable scope; the dependents add the temperature-sensing and control-logic specifics.

Claim 1 — "An apparatus comprising"

Four elements, all required:

1. A sensor with a plurality of sense nodes — i.e., the sensor's output is multi-bit/parallel (the embodiment's 3-bit TEMPOP).
2. A plurality of first latch circuits, each having an input and an output, with the inputs coupled to respective sense nodes — one first-stage latch per sensor bit (element 61; clocked by TRAN).
3. A plurality of second latch circuits, each having an input coupled to a respective first-latch output — i.e., a second, cascaded rank of latches storing a copy of the first rank's contents (element 62).
4. A selector with (a) third input nodes coupled to the first-latch outputs, (b) fourth input nodes coupled to the second-latch outputs, and (c) third output nodes — a multiplexer that can pass through either the first-rank or the second-rank data.

Scope observation (important for any validity/infringement read): independent claim 1 is structurally broad. It does not recite a temperature sensor, a monitoring signal, a mode-register-read command, an oscillator, an SR latch/selector-control circuit, delay circuits, output buffers, external terminals, or a DRAM. It covers essentially any two-rank parallel latch tree feeding a 2:1 selector — combinatorial rather than timing-limited. All of the distinguishing timing/state-machine subject matter of the specification sits in the dependent claims.

Dependent claims (what they add)

• 2 — delay circuits between first-latch outputs and second-latch inputs (the delay element 55).
• 3 — a third rank of latch circuits on the selector's output (element 63).
• 4 — external terminals plus data output buffers between the third-rank outputs and those terminals.
• 5 — the sensor has a monitoring node carrying a monitoring signal whose logic level changes with sensor state; adds a selector control circuit with an input on the monitoring node, a further input, and an output to the selector (the SR latch 54 concept).
• 6 — command decoder plus logic circuit feeding the selector control circuit's seventh input (element 39).
• 7 — the logic circuit also drives the third-latch control gates in common.
• 8 — an oscillator coupled to the sensor to activate it intermittently per the oscillation cycle.
• 9 — the logic circuit provides a first control signal commonly to the third-latch control gates after providing a second control signal to the selector-control input (MMRR4 after MMRR1).
• 10 — the second control signal is issued responsive to a mode register read command.
• 11 — the sensor is a temperature sensor supplying a temperature measurement to the sense nodes; the first and second latches latch that measurement.
• 12 — adds a control circuit coupled to the selector and to the second latches, providing a first control signal; the temperature sensor provides a second control signal and a monitoring signal.
• 13 — defines the latch/select behavior in response to the first and second control signals and the monitoring signal.
• 14 — the control circuit is a memory's command decoder and the first control signal is a mode register read command.

Flagged claim-drafting oddities (interpreted literally, not corrected): claim 12 recites "the temperature sensor" even though it depends only on claim 1, which recites no temperature sensor; claim 13 refers to "the first command signal" although claim 12 recites a "first control signal"; and claim 14's phrase "the control circuit is command decoder of a memory" is grammatically incomplete. These are as-published.

5. Prior art cited on the face of the patent

Cited by the examiner/applicant (4 references):

• US 5,378,950 A (Toshiba, 1995-01-03) — Semiconductor integrated circuit for producing activation signals at different cycle times
• JP 2002-343079 A (Melco Inc., 2002-11-29) — DRAM device and DRAM device refresh method (the reference cited in the Background section)
• US 2006/0109225 A1 (NEC, 2006-05-25)
• US 2013/0242674 A1 (Elpida Memory, 2013-09-19)

Family-level citations include KR 100854463B1, JP 2011-170943A, KR 2013-0042334A, KR 101885857B1, KR 2014-0006219A, KR 101974108B1, KR 102170333B1, and JP 2015-219927A. Citing documents: US 11,274,977 B2 (the Micron divisional) and US 11,274,972 B2 (Denso, 2018 priority). Forward family citations include KR 102533236B1 (Samsung), KR 102463924B1 (SK hynix), and CN 115132239B.

6. USPTO / PTAB / CAFC litigation search result

Negative finding: I found no district court complaint, no PTAB (IPR/PGR) petition, and no CAFC appeal or 2026 Federal Circuit docket entry asserting or challenging US 10,168,233 specifically.

• The Micron-related 2026 CAFC and district court activity my searches surfaced concerns other patents — principally the Netlist v. Micron matters (e.g., CAFC Nos. 24-2281, 2025-1936, 2025-1286, 2025-1296; C.D. Cal. 8:26-cv-02167; D. Del. 1:26-cv-01014; ITC Inv. No. 337-TA-3930) and the Micron v. YMTC IPR cluster. The patent numbers in those matters are U.S. 10,217,523; 12,675,407; 11,016,918; 11,232,054; 10,860,506; 10,949,339; 9,318,160; 8,787,060; 8,301,833; 9,824,035; 10,268,608; 10,489,314, etc. None of these is 10,168,233.
• I did not locate any USPTO PatentCenter/Assignment record beyond the chain already reflected in the Google Patents legal-events log (Micron assignment; a series of collateral security interests with U.S. Bank, Morgan Stanley, and JPMorgan Chase, all subsequently released in 2018–2019).

Confidence: moderate-to-high that the patent has not been a litigation vehicle as of this date, but this reflects the limits of my search tooling, not a certificate of non-litigation. A definitive check requires a paid docket service (Docket Navigator, LexisNexis, or PACER/PTAB E2E by patent number) — I cannot verify this exhaustively from open web search alone.

7. Explicit uncertainties and caveats

1. Contradictory third-party attribution. An aggregator page, patentleaderboard.com, lists inventor Kiyohiro Furutani under "Mitsubishi Electric" with 126 US patents and includes patent 10168233 in that list. This conflicts with the authoritative assignment records on the patent itself (Furutani → Micron Technology, Inc.). Per your instruction I am not auto-correcting either source; I flag the discrepancy. The most likely explanation is an aggregator artifact (name-clustering rather than assignee-based grouping), but I state that as inference, not fact.
2. Issue-date convention. Google Patents lists the publication/grant date as 2019-01-01, and the legal-events log records a "patent grant" status entry dated 2018-12-12. The official grant date on the printed patent face may differ by a day or two from the date field I was given. Treat 2019-01-01 as the record I was provided.
3. Text artifacts in the fetched document (not corrected). The fetched full text contains apparent OCR/transcription errors, including "sense amplifier RAMP" where the same figure description elsewhere says "SAMP", "dock input circuit"/"dock signals" for clock-related terms, and "dock" for "clock" throughout. The description also states "FIGS. 7 to 10 are timing charts" even though the drawing list contains only FIGS. 1–8, and one passage says "As shown in FIG. 4, the mode register read command MMRR is specified as a three-clock-cycle command" where the reference should logically be FIG. 2. These are internal inconsistencies in the source text; I report them literally rather than repairing them.
4. Claim independence determination is based on the claim text as reproduced. I count one independent claim (claim 1). If the USPTO record shows a different claim set (e.g., after a certificate of correction), that would supersede this reading.
5. The divisional US 11,274,977 B2 has a materially broader independent claim 1 (reciting the sensor, the first/second read command signals, the monitoring-signal-responsive logic, and the third logic circuit) — relevant if you are evaluating the family, since enforcement value may sit more in the continuation than in the '233 patent's structural claim 1. See Justia US11274977.

8. Sources

• Full patent text (authoritative for this analysis): https://patents.google.com/patent/US10168233/en
• Family/continuation: https://patents.google.com/patent/[US11274977B2](/patent/US11274977B2)/en
• Pre-grant publication mirrors: https://www.freepatentsonline.com/y2015/0330845.html · https://patents.justia.com/patent/20150330845
• Contradictory inventor/assignee aggregator listing: https://www.patentleaderboard.com/mitsubishi-electric/kiyohiro-furutani/[810679](/patent/810679)
• Micron–Netlist 2026 CAFC docket context (not this patent): https://www.courtlistener.com/docket/70803592/micron-technology-inc-v-netlist-inc/

I'll search for litigation involving US patent 10168233 across patent litigation databases and court records.

Initial searches returned irrelevant results. Let me search more targeted litigation databases.

Litigation Search Results for U.S. Patent No. 10,168,233

Summary: I found no litigation involving U.S. Patent No. 10,168,233.

Despite targeted searches across patent-litigation-focused sources (Unified Patents litigation portal, Docket Navigator excerpts, CourtListener/PACER dockets, RPX Insight, and general patent-litigation reporting), I identified no case in which U.S. Patent No. 10,168,233 has been asserted as a patent-in-suit, challenged in a declaratory judgment action, or made the subject of an IPR/PGR proceeding surfaced in these results.

I want to be explicit about the limits of this conclusion, per your instructions:

• Searches for the exact identifier returned unrelated hits — e.g., Colombian national-ID numbers ("10168233"), Brazilian exam records, a European patent search-report annex, and cases involving different patents informally described as the "'233 patent" (Oticon v. SeboTek; iRobot ITC Inv. No. 337-TA-**** involving U.S. Patent Nos. ending in '233; ACS v. Medtronic). None of these concern U.S. Patent No. 10,168,233.
• Broader searches for Micron patent litigation (e.g., the extensive Netlist v. Micron campaign, Advanced Memory Technologies v. Micron) also produced no reference to 10,168,233.
• I could not directly load the Unified Patents case-list portal at https://portal.unifiedpatents.com/litigation/caselist or PACER/CAFC docket records in full, so there is a possibility of a case not indexed by the search engine. I am flagging this rather than asserting a categorical negative.

Context on the patent (non-litigation facts)

U.S. Patent No. 10,168,233 ("Semiconductor device including sensor"):

• Assignee: Micron Technology, Inc. (original and current)
• Inventor: Kiyohiro Furutani
• Priority date: 2014-05-14 (JP 2014-100510); filed: 2015-05-08; granted: 2019-01-01
• Status: Active, adjusted expiration 2037-04-01
• Related family member: U.S. Patent No. 11,274,977 (continuation/divisional, filed 2018-12-20) — also shows no litigation in the results retrieved

If you need a definitive negative

For a high-confidence answer, the following registries should be checked directly (they were not fully loadable via search here):

1. Unified Patents Litigation Portal – https://portal.unifiedpatents.com/litigation (search by patent number)
2. PACER – https://pacer.uscourts.gov (case-number/docket search across districts)
3. CAFC – https://cafc.uscourts.gov (appeals from district courts/PTAB)
4. PTAB / USPTO Patent Center – for any IPR/PGR or assignment/litigation certificates
5. Docket Navigator / RPX Insight (subscription litigation databases)

Conclusion: On the record available to me, there is no known litigation involving U.S. Patent No. 10,168,233. If you require a certified negative, the docket-level searches in items 1–5 above should be run directly, as I could not exhaustively query those systems.

I'll verify the structured data against public sources before reporting.

Proceedings overview

Zero AIA trial proceedings are on file for US 10,168,233. The USPTO Open Data Portal structured block supplied for this patent lists no IPR, PGR, or CBM — no petitioner, no institution decision, no Final Written Decision, no appeal — so the breakdown is 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials, and the cross-checking searches I ran surfaced no proceeding the ODP may simply not have indexed yet. The defensive posture this creates is not the comfortable one. There is no PTAB work product, no narrowing, and no estoppel to exploit: all 14 claims (claims 1–14) stand exactly as they issued on 2019-01-01, and a defendant would be litigating patentability from a blank slate.

A framing note before the details: this is not a troll patent. Current assignee is Micron Technology, Inc., original assignee Micron, inventor Kiyohiro Furutani (US10168233B2). It is a DRAM-internal temperature-sensing architecture patent (priority 2014-05-14; JP2014-100510). A demand letter or assertion on it would come from a large operating semiconductor manufacturer defending a circuit design, not from a shell asserting a paper claim set.

No proceedings to enumerate

I cannot populate the per-proceeding template ({PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner}, grounds, panel, institution, FWD, settlement, appeal) because doing so would require inventing a proceeding number, and the constraint is explicit: do not invent proceeding numbers. Stating the absence plainly is the accurate answer:

• PTAB trial list (canonical, per USPTO ODP): empty.
• Independent web verification: searches for IPR/PGR/CBM petitions against 10168233, 10,168,233, and the family members US 11,274,977 B2 / US 20190120704A1 returned no PTAB filings. The Google Patents record for the patent shows no IPR in its "Cited By" or litigation sections — the only listed cite-by is its own divisional (US 11,274,977 B2, Micron) and Denso's unrelated US 11,274,972 B2.
• Confidence level: high on the canonical list; moderate-to-high on absence globally. I did not have direct query access to PTAB E2E or Docket Navigator in this session, so I cannot rule out a recently filed petition that neither ODP nor the indexed public pages have picked up. Treat "no PTAB activity" as the working assumption and re-verify against PTAB E2E / PTAB Center before relying on it in a brief.

Strategic summary

Claim status: everything is UNTESTED. Unlike most patents that have been in assertion for a decade, there is no claim-level record here at all. Claims 1–14 are all live and uncancelled. Claim 1 is the apparatus claim (sensor with multiple sense nodes → first latch circuits → second latch circuits → selector). Claim 3 adds the third latch stage; claim 5 adds the monitoring node and selector control circuit; claim 7 hangs the third latch control gates off the logic circuit; claims 9–10 tie the MMRR-then-first-control-signal sequencing to a mode-register read command; claim 11 recites the temperature-sensor limitation; claims 12–14 recast the control circuit as a memory command decoder with the first control signal being the mode-register read command. That "logic circuit provides the second control signal after the first control signal" sequencing (claim 9) and the monitoring-signal-driven selector (claim 5) are the likely load-bearing limitations — and they are exactly the kind of specific circuit-architecture limitations that give a defendant room to argue non-infringement even where validity is hard to attack.

Estoppel landscape: none exists, and that cuts both ways. Because no IPR was ever instituted, no petitioner is barred under 35 U.S.C. § 315(e)(2), and there is no Board finding — favorable or unfavorable — that a district court must reckon with. For a defendant being asserted today, that means: (a) all prior-art grounds under § 102 and § 103, including system art and public-use art that cannot be raised in an IPR under § 311(b), remain fully available in district court; (b) an IPR remains available subject only to the § 315(b) clock — one year from service of a complaint alleging infringement — and there is no prior petitioner to be in privity with; and (c) the patent owner will be defending an IPR for the first time, without having stress-tested its claim construction or its objective-indicability story. The face of the patent cites only four references (US 5,378,950 to Toshiba; JP 2002-343079; US 2006/0109225 to NEC; US 2013/0242674 to Elpida), and the listed family citations are largely Korean temperature-management art — none of which is a strong obviousness combination on its own, but the prior-art space for on-die temperature sensing with asynchronous measurement and MMRR readout is dense.

Pattern signals: none. No repeat petitioner, no patent-owner PTAB appeals (there are no decisions to appeal), no defensive aggregator such as Unified Patents, and no related district court case surfaced in my searches in which this patent is asserted. The one structural caveat is the division: continuation application US 16/228,377 (filed 2018-12-20) issued as US 11,274,977 B2 on 2022-03-15 and shares the 2014-05-14 priority date. That divisional has a different claim set and a different § 315(b) and PGR posture, so a defendant facing the family should check both members — a challenge aimed only at the '233 may leave the '977 claims untouched. Also note the patent's adjusted expiration of 2037-04-01, so there is over a decade of exposure left; the 4th-year maintenance fee was paid on 2022-06-21, indicating the owner has no intention of letting it lapse.

Recommended next steps

1. Re-verify the empty docket directly, then rely on it. Query PTAB E2E (https://ptacts.uspto.gov/) for the patent number and for "Micron Technology" as patent owner, and confirm via ODP. If it is genuinely empty, there is no FWD to link to and no disposition to quote — do not build an argument that claims have been cancelled, because none have.
2. Do the invalidity work yourself. With no PTAB record, there is no roadmap. Commission a § 102/§ 103 search against claim 1's multi-node-latch-plus-selector architecture and claim 5's monitoring-node/selector-control combination, including system art (DRAM datasheets, MMRR temperature-readout specifications, integrated temperature-sensor products) that an IPR petition could not use but a district court could.
3. Consider a petition on your own timetable. If you have been served with a complaint asserting the '233, your § 315(b) window closes one year from service; the statutory FWD deadline is one year from institution. Because no prior petitioner exists, you can capture all the first-mover benefits (no adverse estoppel, no prior claim constructions) rather than inheriting someone else's failed record.
4. Check the family. Analyze US 11,274,977 B2 separately; separate petition, separate window, separate claim set.
5. Non-infringement is likely your fastest path. Claims 5, 7, 9 and 10 are narrow and functional — the monitoring-signal-gated selector and the ordered first-control-signal/second-control-signal sequencing are concrete circuit requirements that a competing design may simply not practice. Build the claim chart early; it may moot the validity fight entirely.

Verification sources: USPTO ODP structured "PTAB proceedings on file" block for US 10,168,233 (empty); Google Patents US10168233B2; PTAB Center / E2E at https://ptacts.uspto.gov/; CourtListener at https://www.courtlistener.com/. No proceeding numbers are cited because none exist on the record reviewed.

I'll verify the assignment record and cross-reference the inventor and assignee before building the timeline.

Assignment Record Reconstruction — U.S. Patent No. 10,168,233

Method note / limitation up front: The primary source requested (USPTO Assignment Center, both assignmentcenter.uspto.gov and the assignment.uspto.gov index) was not directly loadable here; I reconstructed the chain from the assignment data as rendered in the patent's legal-events record (Google Patents mirror of the USPTO assignment database) and cross-checked the securitization entries against Micron's SEC filings. The "correspondent of record" field is not exposed in the legal-events rendering, so I could not capture attorney names — I flag this explicitly rather than guess, and give the verification link at the end. Every reel/frame below is a recorded entry, not an inference.

Inventors

Pattern assessment — no fire-sale precursor: This is a single-inventor patent with no co-inventor attrition to track. Furutani's employment continuity (Elpida → Micron) is a retention pattern, not a departure pattern. The JP priority application (JP 2014-100510, filed 2014-05-14) was filed roughly ten months after the Elpida acquisition closed, confirming the work was done under the Micron umbrella. No signal of inventors leaving within 12 months of filing.

Original assignee

Micron Technology, Inc. (Boise, Idaho) — the entity named on the issued patent and, after all recorded liens were released, still the owner.

• Primary line of business: DRAM/NAND semiconductor memory (the patent itself describes "a DRAM" with an on-die temperature sensor feeding refresh control — the claims read on Micron's core products).
• Ships products embodying the claims: Yes. The patent is literally an internal architecture patent for a DRAM temperature-measurement readout (mode-register-read of temperature data), the kind of design used across Micron's commodity DRAM lines.
• Current status: Operating, publicly traded (NASDAQ: MU), large-entity maintenance fee paid 2022-06-21 (4th-year fee, per the record). No bankruptcy; no dissolution; no acquisition of Micron itself.

Assignment timeline

All records below are transcribed from the patent's legal-events record (USPTO assignment data). Title never moved beyond Micron — every post-2015 entry is either a security-interest encumbrance or a release of one.

1. 2015-05-07 (executed) / recorded 2015-05-08 — Reel 035600/0816

   • Conveyance: Assignment
   • Assignor: Kiyohiro Furutani (individual)
   • Assignee: Micron Technology, Inc.
   • Correspondent: not exposed in retrieved record — requires Assignment Center lookup.
   • Context: Original inventor → company assignment (employment/duty-to-assign); the only true transfer of title in the entire chain.

2. 2016-04-26 (executed) / recorded 2016-05-12 — Reel 038669/0001

   • Conveyance: Security Agreement / security interest (grant of collateral, not a title transfer)
   • Assignor: Micron Technology, Inc.
   • Assignee: U.S. Bank National Association, as Collateral Agent
   • Correspondent: not exposed in retrieved record.
   • Context: Securitization — portfolio-wide lien to secure Micron's April 26, 2016 notes indenture (U.S. Bank as collateral agent).

3. 2016-04-26 (executed) / recorded 2016-06-02 — Reel 038954/0001

   • Conveyance: Patent Security Agreement / security interest
   • Assignor: Micron Technology, Inc.
   • Assignee: Morgan Stanley Senior Funding, Inc., as Collateral Agent
   • Correspondent: not exposed in retrieved record.
   • Context: Securitization — second lien under the same April 26, 2016 credit facility (~$750M term loan; Morgan Stanley as admin/collateral agent). Corroborated by Micron Form 8-K EX-10.1/EX-10.2 and EX-4.1 dated 2016-04-26.

4. 2016-04-26 (executed) / recorded 2017-06-08 — Reel 043079/0001

   • Conveyance: Correction (Corrective Assignment)
   • Assignor: Micron Technology, Inc.
   • Assignee: U.S. Bank National Association, as Collateral Agent
   • Correspondent: not exposed in retrieved record.
   • Context: Change of record only — corrective re-recording to replace an erroneously filed patent number (#7,358,718 → #7,358,178) in the original U.S. Bank filing. No change in ownership.

5. 2018-06-29 (executed) / recorded 2018-08-23 — Reel 047243/0001

   • Conveyance: Release (Release by Secured Party)
   • Assignor: U.S. Bank National Association, as Collateral Agent
   • Assignee: Micron Technology, Inc.
   • Correspondent: not exposed in retrieved record.
   • Context: Lien release — extinguishment of the 2016 U.S. Bank encumbrance.

6. 2018-07-03 (executed) / recorded 2018-07-13 — Reel 047540/0001

   • Conveyance: Security Agreement / security interest
   • Assignor: Micron Technology, Inc. and Micron Semiconductor Products, Inc.
   • Assignee: [JPMorgan Chase Bank, N.A., as Collateral Agent](/asserters/jpmorgan-chase-bank-n-a-as-collateral-agent)
   • Correspondent: not exposed in retrieved record.
   • Context: Refinancing securitization — new collateral grant under Micron's 2018 credit facility.

7. 2019-07-31 (executed) / recorded 2019-10-09 — Reel 050937/0001

   • Conveyance: Release
   • Assignor: Morgan Stanley Senior Funding, Inc., as Collateral Agent
   • Assignee: Micron Technology, Inc.
   • Correspondent: not exposed in retrieved record.
   • Context: Lien release.

8. 2019-07-31 (executed) / recorded 2019-11-12 — Reel 051028/0001

   • Conveyance: Release
   • Assignors: JPMorgan Chase Bank, N.A., as Collateral Agent
   • Assignees: Micron Technology, Inc. and Micron Semiconductor Products, Inc.
   • Correspondent: not exposed in retrieved record.
   • Context: Lien release — the last encumbrance is removed; Micron is left as sole unencumbered owner.

Related family event (not an assignment): divisional application US 16/228,377, filed 2018-12-20, issued as US 11,274,977 (2022-03-15). Same inventor, same assignee — this is an internal family continuation, not a transfer.

Net result: One title transfer (inventor → Micron), three security-interest encumbrances, one correction, and three releases. No post-issuance ownership transfer of any kind.

Timeline diagram

timeline
    title Ownership of US 10168233
    2014 : JP priority filed
    2015 : Assigned to Micron Technology
         : US application filed
    2016 : Security interest to US Bank
         : Security interest to Morgan Stanley
    2017 : Corrective recording to US Bank
    2018 : US Bank lien released
         : Security interest to JPMorgan
         : Divisional application filed
    2019 : Patent granted
         : Morgan Stanley lien released
         : JPMorgan lien released

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. No assignee in the chain carries an "IP / Holdings / Licensing / Ventures" suffix, and no single-purpose LLC ever appears. The only non-Micron assignees are three insured depository institutions acting as collateral agents (U.S. Bank, Morgan Stanley Senior Funding, JPMorgan Chase) — none of which takes title. Reels 035600/0816, 038669/0001, 038954/0001, 047540/0001.

2. Known asserter in the chain — Not present. No assignee matches any public NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN/Conversant, Vringo, Pendrell, Round Rock, etc.). Current assignee is an operating semiconductor manufacturer.

3. Repeat correspondent across the chain — Unclear / not retrievable. The correspondent-of-record fields are not exposed in the legal-events rendering I could access, so I cannot confirm or deny recurrence. Structural note (not a finding): the 2016/2018 lien recordings were part of portfolio-wide collateral filings (Espacenet's INPADOC record shows the identical U.S. Bank/Morgan Stanley reel-and-frames — 038669/0001 and 038954/0001 — recorded against other Micron patents, e.g. US 6,884,658), so any correspondent on those entries is lender/securitization counsel working across the entire Micron portfolio, not a patent-assertion lawyer. This pattern is consistent with corporate finance counsel, not NPE counsel — but it needs the correspondent names to be a citable finding.

4. Cascading transfers — Not present. The eight recordings span 2015–2019, but only one is a title transfer; the rest are liens/releases tied to a single borrower's credit facilities. No chained LLCs, no shared shell addresses, no common-principal layering.

5. Pre-litigation transfer — Not present. No infringement suit naming US 10,168,233 was found (see litigation summary), so there is no suit for a transfer to precede. The recordings nearest to any assertion activity are lien releases, which remove encumbrances rather than arrange standing.

6. Bankruptcy fire-sale — Not present. Micron never filed Chapter 7/11; it is a going concern that continued paying large-entity maintenance fees (4th-year fee, 2022-06-21). The 2016–2019 recordings are ordinary secured financing, not distress sales.

7. Privateering — Not present. There is no transfer to any third party, let alone an NPE asserting on Micron's behalf.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates right where it started — at Micron.

Verdict

Operating-company assertion.

Justification (with an explicit caveat): The only transfer of title in the entire record is the inventor→Micron Technology, Inc. assignment at reel 035600/0816 (executed 2015-05-07); every subsequent entry — reels 038669/0001, 038954/0001, 043079/0001, 047540/0001, 047243/0001, 050937/0001, 051028/0001 — is a portfolio-wide security interest or its release, none of which moved ownership. The current assignee is a large operating DRAM manufacturer whose products embody the claimed temperature-sensor/mode-register-read architecture, which is the defining feature of the "operating-company" bucket. Caveat: the taxonomy's "Operating-company assertion" label also presupposes that the holder is suing competitors on the patent; consistent with the earlier litigation section, no infringement suit naming US 10,168,233 was found, so the "assertion" element is unconfirmed — the more precise characterization is a captive, never-transferred, currently non-asserted operating-company patent, i.e. the clean anti-NPE outcome.

Verification: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search "10168233"; cross-index at https://assignment.uspto.gov/patent/index.html). Suggested follow-up to close the one gap: pull the correspondent-of-record for reel/frame 035600/0816 (original assignment) and reels 038669/0001 / 038954/0001 (lien filings) to confirm whether a single securitization counsel recurs — that is the only signal I could not resolve.

I'll research the patent and each of its cited references. Let me run targeted searches.

Search Confirmation — U.S. Patent No. 10,168,233

I searched the USPTO/Google Patents records for the specific identifier 10168233 (not similar numbers). The record resolves unambiguously to:

• Patent: US 10,168,233 B2 — "Semiconductor device including sensor"
• Application: US 14/707,951; filed 2015-05-08
• Priority: JP 2014-100510 (2014-05-14)
• Granted: 2019-01-01; Status: Active, adjusted expiration 2037-04-01
• Inventor: Kiyohiro Furutani; Assignee: Micron Technology, Inc.
• Child/continuation: US 16/228,377 → US 11,274,977 B2 ("Semiconductor device including sensor")

Source: https://patents.google.com/patent/US10168233/en

The patent lists four patent citations. Note their prosecution status (per the Google Patents citation table): three carry the examiner-cited marker (US 5,378,950; US 2006/0109225; US 2013/0242674), while JP 2002-343079 is the applicant's own background citation (it appears in the "Description of Related Art" of the specification). I treat all four as required by the task.

Prior-Art Reference 1 — US 5,378,950 A

• Full citation: US 5,378,950 A — "Semiconductor integrated circuit for producing activation signals at different cycle times" — Kabushiki Kaisha Toshiba. Inventor(s) Toshiba (see PDF, US5378950).
• Dates: Priority 1992-02-03; granted/published 1995-01-03.
• Bibliographic note: More than 20 years before the '233 priority date (2014-05-14) → expired / prior art under § 102(b) (pre-AIA) / § 102(a)(1).
• Brief description: Discloses a semiconductor integrated circuit in which an n number of wirings carry activation signals, driven by a selector drive circuit that sends the activation signals to the respective wirings at different cycle times using delay elements, so that the wirings are not driven simultaneously. The selector drive circuit uses transfer gates made of P-channel/N-channel MOS transistor pairs (Q1/Q2, Q11/Q12) and delay circuits (e.g., 103, 104). The stated goal is to lower current density/mean current on fine metal wiring without widening it. (Sources: https://patents.google.com/patent/[US5378950A](/patent/US5378950A)/en ; https://www.freepatentsonline.com/[5378950](/patent/5378950).html)
• Potentially anticipatory claim(s): None for a full § 102 rejection. It contains no sensor, no sense nodes, and no latch circuits. Its only structural overlap is generic circuit-building blocks — a selector and delay elements — which map loosely to the selector/delay architecture of claims 1 and 2. Under § 102 it cannot anticipate claim 1 (missing the "sensor including a plurality of sense nodes," the first latch circuits, and the second latch circuits). It is best characterized as a possible § 103 secondary reference for the selector-plus-delay concept underlying claims 1–2, if combined with a sensor-based primary reference.

Prior-Art Reference 2 — JP 2002-343079 A

• Full citation: JP 2002-343079 A — "DRAM device and DRAM device refresh method" (DRAM装置およびDRAM装置のリフレッシュ方法). Application No. 2001-148972; applicant listed as Melco Inc. (per Google Patents citation table).
• Dates: Application/filing 2001-05-18; publication 2002-11-29. (Confirmed via J-GLOBAL: https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=200903038279289148)
• Bibliographic note: Published >12 years before the '233 priority date → prior art under § 102(a)(1)/(b).
• Brief description: Discloses a DRAM chip with a temperature sensor (温度センサー 16) that measures the ambient/operating temperature, and a refresh control circuit (リフレッシュ制御回路 12) that generates refresh-request signals based on the measured temperature. Refresh requests are thinned/skipped ("間引いて") to average refresh current and save power. This is the reference cited in the '233 specification's own "Description of Related Art" to establish that DRAM temperature sensors feeding refresh control are known. (Sources: https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=200903038279289148 ; https://patents.google.com/patent/JP2008048384A/en)
• Potentially anticipatory claim(s): None. There is no latch chain and no selector between a sensor and a data output. It is relevant only to claim 11's "sensor is a temperature sensor configured to provide a temperature measurement," and even then only at the level of a generic on-chip temperature sensor — not to the claimed sense-node/latch/selector architecture. A § 102 rejection cannot be based on this reference alone; at most it is § 103 background on the general notion of a DRAM chip temperature sensor.

Prior-Art Reference 3 — US 2006/0109225 A1

• Full citation: US 2006/0109225 A1 — "Semiconductor device, circuit, display device using the same, and method for driving the same" — NEC Corporation.
• Dates: Filing 2004-09-17; publication 2006-05-25.
• Bibliographic note: Published before the '233 priority date → prior art under § 102(a)(1)/(b).
• Brief description: Relates to integrated MOS/SOI (polysilicon TFT) circuits on glass substrates and display-drive architectures. Its figures show, on the display substrate, a latch circuit 105, a selector circuit 107, a data register 3507, a DAC 106, and a level-shifter/timing buffer 108, with an external controller/memory/Q-buffer. The disclosure is about integrating drive and control circuits (including latches and selectors) on the panel. (Sources: https://patents.google.com/patent/US20060109225A1/en ; https://www.patents-review.com/a/20060109225-semiconductor-device-circuit-display-device-same-method.html)
• Potentially anticipatory claim(s): None for a full § 102 rejection. It discloses latch circuits and a selector, but in a display-driving context, and it lacks (a) a sensor with a plurality of sense nodes, (b) a first latch bank coupled to those sense nodes, and (c) a second latch bank interposed between the first latches and a selector. Because every element of a claim must be present in a single reference for § 102, US 2006/0109225 cannot anticipate claim 1 or its dependents. It is at most a § 103 reference evidencing that latches feeding a selector were known circuit blocks, relevant to claims 1–3 as a combination teaching.

Prior-Art Reference 4 — US 2013/0242674 A1 (most relevant)

• Full citation: US 2013/0242674 A1 — "Semiconductor device, method for controlling the same, and semiconductor system" — Elpida Memory, Inc. (inventor Soichiro Yoshida, Tokyo JP).
• Dates: Priority 2009-02-02; publication 2013-09-19.
• Bibliographic note: Prior art under § 102(a)(1)/(b).
• Brief description: Discloses a semiconductor memory device with a temperature measurement circuit 18 comprising a sensor unit 20, a comparator 21, first/second switches 27/26, an encoder 23, latch circuits 25, an offset control circuit, and a measurement controller. The sensor unit produces multi-bit temperature codes (e.g., OP<2:0>, a 3-bit output; temperature thresholds at 25/85/100/115 °C). Temperature measurement is performed repeatedly at intervals tied to refresh circulation, with the measured temperature code used to change the refresh period. It also discusses multiple successive temperature measurements and retaining/using measured values. (Sources: https://patents.google.com/patent/US20130242674A1/en ; US20130242674A1 PDF at patentimages.storage.googleapis.com)
• Potentially anticipatory claim(s): This is the closest reference and the examiner's apparent primary art, but I would not assert clean § 102 anticipation:
  • Claim 1 / claim 11: It discloses a temperature sensor providing a multi-bit measurement and latch circuits for the measured value, which overlaps the "sensor," "sense nodes," and "plurality of latch circuits" concepts. However, the published architecture uses switches (26/27), a comparator, and an encoder feeding the latches, rather than "a plurality of first latch circuits coupled to sense nodes and a plurality of second latch circuits coupled to the first-latch outputs, with a selector having third input nodes coupled to the first-latch outputs and fourth input nodes coupled to the second-latch outputs." On the record I can retrieve, the two-bank latch + common selector arrangement of claim 1 does not appear disclosed. Claim 1's full node-coupling structure is therefore not clearly anticipated; the reference is a stronger § 103 combination base against claims 1, 2, 3, 8, and 11.
  • Claim 8 (oscillator activating the sensor intermittently): The reference measures temperature repeatedly at intervals/circulations. If its measurement controller/clocking is read as an oscillator-driven intermittent activation, it could bear on claim 8 under § 103 (again, § 102 is not clean because the claim specifies an "oscillator coupled to the sensor" providing an "oscillation signal to activate the sensor intermittently in accordance with a cycle").
  • Claims 5–7, 9, 10 (monitoring node, selector control circuit, command decoder/logic circuit, MMRR signaling): Not disclosed; these elements (the SR-latch MMRRFAST selection mechanism and the mode-register-read command path) appear to be the '233 patent's point of novelty and are absent from the Elpida reference.

Bottom Line

Most relevant prior art: US 2013/0242674 A1 (Elpida Memory) — it is the only cited reference that combines a multi-bit temperature sensor, latch circuits, and repeated/intermittent measurement control in a DRAM, and it is the examiner's apparent primary reference.

Honest caveat on § 102: On the references I can retrieve, none is a clean, single-reference § 102 anticipation of independent claim 1. The four citations are, in my assessment, § 103-type art: three are background/architecture references (Toshiba selector-drive, NEC latch/selector, Melco DRAM temp sensor), and Elpida is the closest combination base. The feature that appears to distinguish the '233 patent — the SR-latch selector-control circuit driven by the sensor monitoring signal (TSREADY) and the mode-register-read command signals (MMRR1) to choose between a first-latch and a second-(delayed-latch) output — is not disclosed in any of the four citations. I am flagging the "not clearly anticipates" characterizations explicitly rather than asserting a categorical § 102 rejection, because a definitive anticipation call requires the full figure-level text of each reference, which the retrieved excerpts only partially provide.

Would you like me to (a) pull the complete figure-level disclosure of US 2013/0242674 to firm up the claim-1 element-by-element comparison, or (b) check the prosecution history / file wrapper of US 10,168,233 for the examiner's actual § 102/§ 103 rejections and the applicant's distinguishing arguments?

I'll research the cited prior-art references to ground the §103 analysis, since the obviousness conclusion depends on what each reference actually discloses.

Obviousness Analysis — U.S. Patent No. 10,168,233 under 35 U.S.C. § 103

Building on the earlier litigation section (no asserted cases found), this section addresses patentability over the art. Note that U.S. 10,168,233 and its divisional child U.S. 11,274,977 (filed 2018-12-20) share the same specification, so the § 103 analysis applies substantially to both, and the "Prior Art" dataset below is drawn from the face of U.S. 10,168,233 as fetched from https://patents.google.com/patent/[US10168233](/patent/US10168233)/en.

1. The legal framework applied

Obviousness is assessed under the Graham factual inquiries (scope/content of the claims; scope/content of the prior art; level of ordinary skill; secondary considerations), with the KSR instruction that a claimed combination is obvious where a PHOSITA would have had a reason to combine the references with a reasonable expectation of success (MPEP § 2143). The recurring KSR rationales relevant here are:

• (A) combining prior-art elements according to known methods to yield predictable results;
• (B) simple substitution of one known element for another;
• (C) use of a known technique to improve a similar device in the same way;
• (D) applying a known technique to a known device ready for improvement;
• (F) express design incentives / market forces; and
• (G) teachings, suggestions, or motivations in the art itself.

Caveat on scope of record: I retrieved full text/timing for US 5,378,950, JP 2002-343079, and US 2013/0242674, and bibliographic/abstract-level content for US 2006/0109225 and the family-cited Korean/Japanese documents. I could not fully load the interior disclosure of US 2006/0109225 or the full Japanese-language text of JP 2002-343079. Statements about those two rest on titles, abstract, and classifications and are flagged accordingly.

2. Claimed subject matter (the "scope and content")

Independent claim 1 is a bare architectural claim: (a) a sensor with plural sense nodes; (b) plural first latch circuits whose inputs are coupled to those sense nodes; (c) plural second latch circuits whose inputs are coupled to the first latches' outputs; and (d) a selector having inputs from both the first latches and the second latches. It is deliberately generic — it recites no temperature sensor, no commands, no timing, and no arbitration logic.

The dependents add: delay circuits between the two latch banks (claim 2); a third latch bank (claim 3); output buffers/external terminals (claim 4); a monitoring node from the sensor plus a selector control circuit (claim 5); a command decoder + logic circuit (claim 6); a common control gate for the third latches (claim 7); an oscillator that activates the sensor intermittently (claim 8); sequenced first/second control signals (claim 9); a mode register read command as the trigger (claim 10); the sensor being a temperature sensor (claim 11); a control circuit providing a first control signal with the sensor providing a second control signal and a monitoring signal (claim 12); the latching/selecting timing (claim 13); and the control circuit being a memory command decoder with the first control signal being a mode register read command (claim 14).

3. The prior-art references and what they teach

Family-cited art (from JP/KR counterparts) supplies additional, independent evidence of the state of the art: KR 100854463 B1 (Hynix — "Temperature sensor circuit and semiconductor memory device using same"), US 7,880,661 B2 (on-die thermal sensor that "counts clocks… until the second voltage reaches the first voltage" to output a thermal code), US 7,891,868 B2 (temperature sensor with oscillator + counter generating temperature signals, plus latches), and KR 101974108 B1 (refresh address generator). One further reference surfaced that is highly probative of the MMRR concept but was not on the face of the '233 patent: US 2007/0297260 A1 (https://patentimages.storage.googleapis.com/59/14/93/25f718966527f7/US20070297260A1.pdf), which claims a memory whose "mode register… activates an additional function control signal" so that an additional function (e.g., temperature output) executes concurrently with refresh — i.e., temperature data delivered via a register-read path.

4. Proposed combinations and motivations

Combination A — Claim 1 (and claims 2–4, 11): Elpida '674 + Toshiba '950, optionally + Melco '079 / NIEC '225

• Where each element is found. Elpida '674 teaches a multi-bit temperature code produced by a sensor and held/tracked in a latch/counting unit for temperature measurement — i.e., a sensor with a plurality of output (sense) nodes feeding latches (element a–b). Toshiba '950 teaches a selector (selector drive circuit 100) that receives multiple drive-circuit outputs through transfer gates and routes a selected one to an output (element d) — the same transfer-gate selection topology the '233 patent itself uses (G1/G2). Melco '079 and NEC '225 supply the "semiconductor memory/display device with internal latch + selector" context.
• Motivation / rationale (KSR (A), (C), (D)). Both references are in the same field (semiconductor integrated circuits/memory), addressing the same problem class — getting internally sensed information reliably to an output. A PHOSITA designing a temperature readout for a DRAM would foresee that duplicating the latch bank to hold an earlier captured sample (element c) and providing a selector to choose between samples is a predictable use of known latch-and-multiplex technique. The '233 patent's own stated reason — avoiding capture of "undefined" data — is a familiar race/metastability design concern that supplies an express design incentive (KSR (F)).
• Reasonable expectation of success. Latching a digital bus and selecting between two latched buses is routine; no physiological/chemical unpredictability.

Conclusion: Claim 1 would likely be obvious over Elpida '674 in view of Toshiba '950 (further in view of Melco '079). Claim 2 is strongly supported: Toshiba '950 itself uses delay circuits (103/104) to skew the activation signals — the exact "known technique to improve a similar device in the same way" (KSR (C)). Claim 3 (third latch) and claim 4 (output buffers/external terminals) are conventional pipelining/output staging; Elpida '674 and Melco '079 both contemplate delivering temperature information onward. Claim 11 (sensor is a temperature sensor, latches latch the measurement) is squarely met by Elpida '674 and Melco '079.

Combination B — Claims 5–7, 9, 12–14 (the arbitration/monitoring sub-system): Elpida '674 + Toshiba '950 + US 2007/0297260

• Monitoring node (claim 5). Elpida '674's "flag signal logic decision means" and its discussion of flag signals whose logic level distinguishes a valid/fixed state from a variable state is the functional equivalent of the '233 monitoring signal TSREADY ("indicating that the value of the sense signal TEMPOP is undefined"). Combined with Toshiba '950's selector, the further addition of a selector control circuit driven by that flag is a predictable substitution (KSR (B)).
• Command decoder + logic circuit, common third-latch gate, sequenced signals (claims 6, 7, 9, 10, 14). Mode-register-based delivery of internal data to an external read path is expressly known (US 2007/0297260: "mode register… activates an additional function control signal"; NEC '225 references a mode register). Decoding a mode register read command and generating two sequenced internal control signals is standard DRAM command-decoder routine, and busing one control signal to the gates of parallel latches (claim 7) is ordinary design.
• Oscillator-activated sensor (claim 8). Elpida '674's sampling-clock/clock-generator arrangement and the counter-based temperature sensors in US 7,891,868 / US 7,880,661, plus Toshiba '950's "different cycle times," together render "an oscillator… to activate the sensor intermittently in accordance with a cycle" obvious.

Combination C (alternative primary) — Hynix KR 100854463 + Toshiba '950 + Elpida '674

KR 100854463 (temperature-sensor circuit for a semiconductor memory device) plus Toshiba '950's selector/delay teaching plus Elpida '674's refresh-control integration yields the same elements with essentially the same rationale; this combination is useful as a backup if Elpida '674's flag discussion is characterized as too general on the monitoring-signal point.

5. Anticipated rebuttal (patentee's non-obviousness arguments)

A skilled advocate would argue:

1. No express suggestion of the specific arbitration trigger. The references individually disclose latches, selectors, delays, and temperature flags, but none (on the retrieved record) expressly teaches that the selector is switched when the monitoring signal is low at the moment the command signal goes high, i.e., the set(S)/reset(R) of an SR latch receiving MMRR1 and TSREADY. This is the "heart" of FIGS. 6–8 and claims 5 and 13.
2. Teaching away / different purpose. Toshiba '950's selector exists to reduce wiring current density by non-overlapping activation — a different problem than data-validity arbitration. Melco '079's temperature sensor drives refresh timing, not an output read path.
3. Secondary considerations. If Micron can show copying, commercial success attributable to the feature, or a long-felt need for reliable on-die temperature readout, these could rebut a prima facie case.

Assessment: Argument (1) is the strongest, but under KSR it is unlikely to be dispositive for the broad claims 1–4, 8, 11, which do not recite the arbitration at all. The motivation to avoid latching undefined/mid-update data is a recognized design incentive, and Elpida '674's flag-based validity signaling supplies the missing suggestion; the combination would therefore likely be characterized as "obvious to try" with a predictable result. The specific SR-latch topology of claim 5/13 could support a narrower non-obviousness position, but the claim recites the selector-control circuit functionally ("sixth input node coupled to the monitoring node, a seventh input node and a fifth output node coupled to the selector") rather than as an SR latch, weakening that distinction.

6. Claim-by-claim bottom line (technical, not legal, conclusion)

7. Explicit uncertainties and limits

• I did not exhaustively retrieve the interiors of JP 2002-343079 and US 2006/0109225, nor the full text of the Korean family-cited references KR 100854463, KR 101974108, KR 20130042334, KR 20140006219, KR 102170333, KR 101885857. Any statement mapping those documents to specific claim elements should be re-verified against their native-language full texts before being relied upon.
• Obviousness is a legal conclusion reserved to the examiner, PTAB, or court; the above is a technical prima facie assessment, not an adjudication. No claim has been invalidated or challenged on this record (consistent with the litigation findings in the prior section).
• Claim-drafting flag (non-§ 103): Claim 13 refers to "the first command signal," for which claim 12 provides no antecedent basis (claim 12 recites a "first control signal" and a "second control signal"). This is a potential § 112(b) clarity issue that would independently complicate enforcement, but it does not affect the § 103 analysis.
• Identifier discipline: All numbers above are transcribed literally (e.g., US 5,378,950; US 2013/0242674 A1; JP 2002-343079; KR 100854463 B1; US 11,274,977). US 2007/0297260 A1 is included as corroborating art even though it is not listed in the "Patent Citations" table of US 10,168,233; it surfaced from the reference's citation web and should be treated as supplementary rather than examiner-cited art.