US 9201834

Here's a concise summary of US Patent 9201834:

US Patent 9201834

• Title: Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
• Assignee (Current): Wecrevention Inc
• Inventors: Weng-Dah Ken, Chao-Chun Lu, Jan-Mye Sung
• Filing Date: November 2, 2012
• Issue Date (Publication Date): December 1, 2015
• Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Plain-Language Overview of Independent Claims:

Claim 1:
This claim describes a reconfigurable high-speed memory chip module comprising:

• A group of memory cell arrays, which includes multiple memory integrated circuits (ICs).
• A first transmission bus connected to this memory cell array group. This bus has programmable characteristics, including a programmable transmitting or receiving data rate and a programmable transmitting or receiving signal swing.
• A second transmission bus connected to a logic unit, also having a programmable transmitting or receiving data rate and signal swing.
• A logic unit connected to the first transmission bus. This logic unit accesses the memory cell array group via the first bus and converts data from the first bus (a first set of parallel data) into another set of parallel data (a second set of parallel data) for transmission through the second bus.

Claim 5:
This claim describes the reconfigurable high-speed memory chip module of Claim 1, further specifying that at least one through-silicon via (TSV) is located within a non-active circuit region of each of the memory cell array ICs. This non-active region either surrounds or partially surrounds an active circuit region of the IC.

CAFC 2026 Dockets:
A review of the provided CAFC 2026 dockets (May and June 2026 scheduled cases) does not explicitly list US Patent 9201834. However, the Google Patents page for US9201834 indicates "Family has litigation" and lists several US cases filed in the Texas Eastern District Court and Texas Western District Court in 2025, as well as a PTAB case (IPR2026-00240) filed in 2026. These dockets are typically at the district court or PTAB level before potentially reaching the CAFC. The provided CAFC dockets appear to be limited to scheduled arguments, and a comprehensive search of all CAFC filings for 2026 would be required to definitively confirm the absence of this specific patent from their broader record.