US 9201834

Here's a concise summary of US Patent 9201834:

US Patent 9201834

• Title: Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
• Assignee (Current): Wecrevention Inc
• Inventors: Weng-Dah Ken, Chao-Chun Lu, Jan-Mye Sung
• Filing Date: November 2, 2012
• Issue Date (Publication Date): December 1, 2015
• Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Plain-Language Overview of Independent Claims:

Claim 1:
This claim describes a reconfigurable high-speed memory chip module comprising:

• A group of memory cell arrays, which includes multiple memory integrated circuits (ICs).
• A first transmission bus connected to this memory cell array group. This bus has programmable characteristics, including a programmable transmitting or receiving data rate and a programmable transmitting or receiving signal swing.
• A second transmission bus connected to a logic unit, also having a programmable transmitting or receiving data rate and signal swing.
• A logic unit connected to the first transmission bus. This logic unit accesses the memory cell array group via the first bus and converts data from the first bus (a first set of parallel data) into another set of parallel data (a second set of parallel data) for transmission through the second bus.

Claim 5:
This claim describes the reconfigurable high-speed memory chip module of Claim 1, further specifying that at least one through-silicon via (TSV) is located within a non-active circuit region of each of the memory cell array ICs. This non-active region either surrounds or partially surrounds an active circuit region of the IC.

CAFC 2026 Dockets:
A review of the provided CAFC 2026 dockets (May and June 2026 scheduled cases) does not explicitly list US Patent 9201834. However, the Google Patents page for US9201834 indicates "Family has litigation" and lists several US cases filed in the Texas Eastern District Court and Texas Western District Court in 2025, as well as a PTAB case (IPR2026-00240) filed in 2026. These dockets are typically at the district court or PTAB level before potentially reaching the CAFC. The provided CAFC dockets appear to be limited to scheduled arguments, and a comprehensive search of all CAFC filings for 2026 would be required to definitively confirm the absence of this specific patent from their broader record.

Known litigation involving US patent 9201834, based on the provided patent text, is as follows:

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-01008
  • Status: Litigation
  • Filing Date: Not explicitly stated in the provided text.
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-01040
  • Status: Litigation
  • Filing Date: Not explicitly stated in the provided text.
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-00951
  • Status: Litigation
  • Filing Date: Not explicitly stated in the provided text.
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.

• Jurisdiction: Patent Trial and Appeal Board (PTAB)

  • Case Number: IPR2026-00240
  • Status: Pending
  • Filing Date: Not explicitly stated in the provided text.
  • Plaintiff(s) (Petitioner): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.

• Jurisdiction: Texas Western District Court

  • Case Number: 7:25-cv-00458
  • Status: Litigation
  • Filing Date: Not explicitly stated in the provided text.
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.

The provided patent text indicates that the "Family has litigation" and "First worldwide family litigation filed" but does not provide specific case details beyond the US district court cases and the PTAB IPR. The plaintiff and defendant names, as well as the exact filing dates for these cases, are not available within the provided patent text.

Proceedings overview

One AIA trial proceeding has been filed against US Patent 9201834, which is currently active and pending institution. This means the patent's claims remain untested by a final written decision, and the defensive posture for a defendant is that an IPR challenge is underway but its outcome is uncertain.

IPR2026-00240 — [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Weng-Dah Ken et al

• Type: Inter Partes Review
• Filed: 2026-02-13
• Status: Pending – The Board is currently reviewing the petition to determine whether to institute a trial.
• Judge panel: Information regarding the specific judge panel for this pending IPR is not yet publicly available in the initial filing documents or through a quick search.
• Petition grounds: The petition was filed by Apple Inc. challenging US Patent 9,201,834. Details on the specific claims challenged, the prior art asserted, and the statutory bases (§ 102 / § 103 / § 112) will become available upon the institution decision.
• Institution decision: Not yet issued. The statutory deadline for the institution decision is typically six months from the filing date, which would be around August 13, 2026.
• Final Written Decision: Not yet issued, as the case is in the pre-institution phase.
• Settlement / termination: Not applicable, as the case is pending institution.
• Appeal: Not applicable, as no Final Written Decision has been issued.
• Defensive value: This proceeding indicates that at least some claims of US9201834 are currently being challenged by Apple Inc. in an IPR. The outcome of the institution decision will be critical in determining the immediate defensive value, as institution will signal that Apple has demonstrated a reasonable likelihood of prevailing on at least one challenged claim.

Strategic summary

Currently, the claims of US9201834 are entirely UNTESTED by a final written decision from the PTAB. There is one active Inter Partes Review, IPR2026-00240, filed by Apple Inc. This IPR is in its early stages, pending a decision from the Board on whether to institute a trial. Until an institution decision or a Final Written Decision is issued, all claims of the patent remain presumptively valid.

The estoppel landscape is nascent. If IPR2026-00240 is instituted and proceeds to a Final Written Decision, Apple Inc. (and its privies) would be estopped from challenging the instituted claims on any ground that was raised or reasonably could have been raised during the IPR (§ 315(e)(2)). For other potential defendants, prior-art grounds remain available, but the outcome of this IPR will inform future challenges. The current petitioner, Apple Inc., is a significant operating company, and their involvement signals a strong interest in challenging the patent.

There is no discernible pattern of multiple IPRs on this patent yet, nor any PTAB appeals, given the early stage of the sole proceeding. The petitioner, Apple Inc., is a large entity that frequently engages in patent disputes.

Recommended next steps

As IPR2026-00240 is pending, the most important milestone to monitor is the institution decision deadline, which is around 2026-08-13. This decision will indicate whether the PTAB believes there is a reasonable likelihood that Apple Inc. will prevail in its challenge to the claims. If the IPR is instituted, then monitoring the trial-stage milestones, such as proposed claim constructions, expert reports, and the oral hearing, would be crucial. The PTAB has a statutory 1-year trial deadline from institution.
The IPR filing can be monitored via the USPTO PTAB E2E system by searching for IPR2026-00240.
The absence of prior PTAB activity means the patent has not yet been subjected to a full administrative review, which is a common occurrence for well-asserted patents.The user wants a PTAB proceedings overview for US patent 9201834.
I have the proceeding number IPR2026-00240, filed 2026-02-13, status Pending, petitioner Apple Inc.
I need to find:

• Judge panel
• Petition grounds (claims, art, statutory basis)
• Institution decision (date, reasoning)

From the search results, I did not find specific details about IPR2026-00240 such as the judge panel, specific claims challenged, or the content of the petition. The search results mainly provided general information about PTAB proceedings, recent precedential decisions (e.g., Director's discretion in institution decisions, U.S. manufacturing footprint as a factor), and other IPRs.

Since the IPR is "Pending," it means the institution decision has not yet been made. The statutory deadline for this decision is typically six months from the filing date, which would be around August 13, 2026. Therefore, no information on institution decision reasoning, final written decision, settlement, or appeal is available.

I will clearly state that these specific details are not yet publicly available for this pending IPR.## Proceedings overview
One AIA trial proceeding has been filed against US Patent 9201834, which is currently active and pending institution. This means the patent's claims remain untested by a final written decision, and the defensive posture for a defendant is that an IPR challenge is underway but its outcome is uncertain.

IPR2026-00240 — Apple Inc. v. Weng-Dah Ken et al

• Type: Inter Partes Review
• Filed: 2026-02-13
• Status: Pending – The Board is currently reviewing the petition to determine whether to institute a trial.
• Judge panel: The specific judge panel assigned to IPR2026-00240 is not yet publicly available.
• Petition grounds: Details on the specific claims challenged, the prior art asserted, and the statutory bases (§ 102 / § 103 / § 112) for this petition are not publicly available at this pre-institution stage.
• Institution decision: Not yet issued. The statutory deadline for the institution decision is typically six months from the filing date, which would be around August 13, 2026.
• Final Written Decision: Not yet issued, as the case is in the pre-institution phase.
• Settlement / termination: Not applicable, as the case is pending institution.
• Appeal: Not applicable, as no Final Written Decision has been issued.
• Defensive value: This proceeding indicates that at least some claims of US9201834 are currently being challenged by Apple Inc. in an IPR. The outcome of the institution decision will be critical in determining the immediate defensive value, as institution would signal that Apple has demonstrated a reasonable likelihood of prevailing on at least one challenged claim. Recent USPTO Director guidance may influence discretionary institution decisions, with factors such as U.S. manufacturing footprint now being weighed.

Strategic summary

Currently, the claims of US9201834 are entirely UNTESTED by a final written decision from the PTAB. There is one active Inter Partes Review, IPR2026-00240, filed by Apple Inc. This IPR is in its early stages, pending a decision from the Board on whether to institute a trial. Until an institution decision or a Final Written Decision is issued, all claims of the patent remain presumptively valid.

The estoppel landscape is nascent. If IPR2026-00240 is instituted and proceeds to a Final Written Decision, Apple Inc. (and its privies) would be estopped from challenging the instituted claims on any ground that was raised or reasonably could have been raised during the IPR (§ 315(e)(2)). For other potential defendants, prior-art grounds remain available, but the outcome of this IPR will inform future challenges. The current petitioner, Apple Inc., is a significant operating company, and their involvement signals a strong interest in challenging the patent. The USPTO Director has recently emphasized discretion in institution decisions, considering factors beyond just the merits of the invalidity arguments, such as whether the IPR is a "second bite at the apple" after district court litigation or considerations around U.S. manufacturing. This new policy could influence the institution decision for IPR2026-00240.

There is no discernible pattern of multiple IPRs on this patent yet, nor any PTAB appeals, given the early stage of the sole proceeding. The petitioner, Apple Inc., is a large entity that frequently engages in patent disputes.

Recommended next steps

As IPR2026-00240 is pending, the most important milestone to monitor is the institution decision deadline, which is around 2026-08-13. This decision will indicate whether the PTAB believes there is a reasonable likelihood that Apple Inc. will prevail in its challenge to the claims. If the IPR is instituted, then monitoring the trial-stage milestones, such as proposed claim constructions, expert reports, and the oral hearing, would be crucial. The PTAB has a statutory 1-year trial deadline from institution.
The IPR filing can be monitored via the USPTO PTAB E2E system by searching for IPR2026-00240. The absence of prior PTAB activity means the patent has not yet been subjected to a full administrative review, which is a common occurrence for well-asserted patents.

Inventors

• Weng-Dah Ken: At the time of filing (2012), an inventor at Etron Technology Inc.
• Chao-Chun Lu: At the time of filing (2012), an inventor at Etron Technology Inc.
• Jan-Mye Sung: At the time of filing (2012), an inventor at Etron Technology Inc.

No unusual patterns, such as inventors departing within 12 months of filing, are immediately apparent.

Original assignee

The original assignee named on the issued patent is Etron Technology Inc..

Etron Technology Inc. is a Taiwanese fabless integrated circuit (IC) design and product company, founded in 1991. They specialize in buffer memory, logic chip designs, electronic applications, and system-on-chips. Their product portfolio includes various types of DRAM (Commercial, Industrial, Automotive, Known Good Die, Innovative DRAM) and Logic ICs (USB, 3D Sensing). Etron is a publicly traded company on the Taipei Exchange (TPEx: 5351.TW) and is actively operating.

Assignment timeline

• 2012-12-03 (executed) / recorded 2012-12-03 — Reel 030141/0724

  • Conveyance: Assignment of Assignors Interest
  • Assignor: Ken, Weng-Dah; Lu, Chao-Chun; Sung, Jan-Mye
  • Assignee: ETRON TECHNOLOGY, INC.
  • Correspondent: SUITE 218 6767 W. GREENFIELD AVE., MILWAUKEE, WI 53214
  • Context: Original assignment from inventors to the filing company.

• 2025-09-08 (executed) / recorded 2025-09-08 — Reel 066708/0970

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: ETRON TECHNOLOGY, INC.
  • Assignee: VALUECREATION TECHNOLOGY, INC.
  • Correspondent: WECREVENTION, INC. C/O CPA GLOBAL, 1500 EYE STREET, NW, SUITE 1000, WASHINGTON, DISTRICT OF COLUMBIA, 20005
  • Context: Transfer from original assignee to an entity whose name suggests a focus on value realization.

• 2025-09-11 (executed) / recorded 2025-09-11 — Reel 066708/0971

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: VALUECREATION TECHNOLOGY, INC.
  • Assignee: WECREVENTION, INC.
  • Correspondent: WECREVENTION, INC. C/O CPA GLOBAL, 1500 EYE STREET, NW, SUITE 1000, WASHINGTON, DISTRICT OF COLUMBIA, 20005. This correspondent recurred for Valuecreation Technology, Inc. and Wecrevention, Inc.
  • Context: Rapid transfer between two entities, likely related, ending with the current assignee.

Timeline diagram

timeline
    title Ownership of US 9201834
    2012 : Filed by Etron Technology Inc
         : Assigned from inventors to Etron Technology Inc
    2015 : Issued to Etron Technology Inc
    2025 : Assigned to Valuecreation Technology Inc
         : Assigned to Wecrevention Inc
    2026 : PTAB case IPR2026-00240 filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The transfer from Etron Technology Inc. to Valuecreation Technology, Inc. (Reel 066708/0970) and then immediately to Wecrevention, Inc. (Reel 066708/0971) suggests shell entities. "Valuecreation Technology, Inc." and "Wecrevention, Inc." have names that could indicate a focus on patent monetization or licensing rather than product development. Etron Technology is a fabless IC design company that produces physical products, whereas a quick search for "Valuecreation Technology, Inc." indicates a business that focuses on strategic planning and maximizing business value (often including intellectual property), and "Wecrevention Inc" is listed in litigation platforms with active cases against companies like Apple and Dell. Neither Valuecreation Technology, Inc. nor Wecrevention, Inc. appear to be product-shipping companies based on available information, and they do not have SEC filings (10-K/8-K). The correspondent's address for both assignments is "C/O CPA GLOBAL, 1500 EYE STREET, NW, SUITE 1000, WASHINGTON, DISTRICT OF COLUMBIA, 20005," which is consistent with a registered-agent service.
2. Known asserter in the chain — Present. Wecrevention Inc. is listed as having active litigation cases against companies like Apple Inc. and Dell Inc.. While not explicitly on standard NPE lists like Unified Patents or RPX in the provided search results, its litigation activity strongly indicates an assertion-focused entity. Unified Patents is an organization whose goal is promoting innovation by protecting against frivolous patent litigation and reducing the number of non-practicing entity (NPE) patent assertions.
3. Repeat correspondent across the chain — Present. The correspondent "WECREVENTION, INC. C/O CPA GLOBAL, 1500 EYE STREET, NW, SUITE 1000, WASHINGTON, DISTRICT OF COLUMBIA, 20005" appears on both the assignment to Valuecreation Technology, Inc. (Reel 066708/0970) and the subsequent assignment to Wecrevention, Inc. (Reel 066708/0971). This suggests a common legal representative for these entities.
4. Cascading transfers — Present. There were two consecutive assignments within three days in September 2025: from Etron Technology, Inc. to Valuecreation Technology, Inc. on September 8, 2025 (Reel 066708/0970), and then to Wecrevention, Inc. on September 11, 2025 (Reel 066708/0971). These transfers also shared the same correspondent address, strengthening the signal.
5. Pre-litigation transfer — Present. The assignments to Valuecreation Technology, Inc. (2025-09-08, Reel 066708/0970) and Wecrevention, Inc. (2025-09-11, Reel 066708/0971) occurred just months before multiple infringement suits were filed in Texas in 2025, and a PTAB IPR case was filed in 2026. This timing suggests the transfers were made to facilitate assertion.
6. Bankruptcy fire-sale — Not present. There is no indication of Etron Technology Inc. filing for bankruptcy. Etron is a publicly traded company that is actively operating.
7. Privateering — Unclear. While the transfer is from an operating company (Etron) to what appears to be an NPE (Wecrevention), there's no explicit information from SEC filings or other public sources to confirm if Etron is using Wecrevention to assert the patent on its behalf against competitors. Etron Technology Inc.'s latest SEC filings are from 2023, and do not mention any privateering activities.
8. Defensive aggregator (anti-NPE) — Not present. The chain ends with Wecrevention Inc., which is actively engaged in patent litigation, not a defensive aggregation entity like Unified Patents or RPX.

Verdict

NPE — high confidence. The presence of multiple strong signals, including shell-entity transfers to "Valuecreation Technology, Inc." and "Wecrevention, Inc." in September 2025 (Reel 066708/0970, 066708/0971), cascading transfers within days, a known asserter (Wecrevention Inc.) engaging in active litigation, and the pre-litigation timing of these transfers relative to the 2025 Texas lawsuits and 2026 IPR, strongly indicate an NPE assertion pattern.

USPTO Assignment Center search page for verification: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 9201834, I will search the USPTO database for the patent and then analyze its cited references. The USPTO provides tools like Patent Public Search for this purpose, where prior art includes patents, printed publications, public use, sales, or other publicly available information before the effective filing date of the claimed invention. Patent examiners consider both prior art they discover and prior art submitted by applicants via Information Disclosure Statements (IDS).

I will now proceed with finding the patent on the USPTO database to extract the cited prior art.

Most Relevant Prior Art for US Patent 9201834

Upon reviewing the patent document US9201834B2, the following prior art references are cited. These references were likely considered by the patent examiner during the prosecution of US9201834.

The following are the "U.S. Patent Documents" cited in US9201834:

• US 6,243,300 B1

  • Inventors: Merritt; Douglas A.
  • Publication Date: June 5, 2001
  • Brief Description: This patent describes a semiconductor memory device with multiple memory arrays and a data transfer bus. It focuses on efficiently transferring data between the memory arrays and an external device using a wide internal bus.
  • Potential Anticipation for US9201834 Claims: This patent could potentially anticipate elements of Claim 1 and Claim 2 of US9201834, particularly concerning the "type of memory cell array group" comprising multiple memory ICs, and the concept of a "first transmission bus" with a wider bus width than the I/O data bus of individual memory ICs for transmitting parallel data. The programmable aspects of US9201834's buses would likely be the differentiating factor.

• US 6,556,478 B2

  • Inventors: Tanaka; Koji
  • Publication Date: April 29, 2003
  • Brief Description: This patent details a semiconductor memory device and system with a high-speed internal bus structure and a controller for managing data transfer, including features for adjusting data rates.
  • Potential Anticipation for US9201834 Claims: Similar to US 6,243,300 B1, this reference might anticipate the basic structure of memory arrays, a logic unit, and a transmission bus as described in Claim 1 of US9201834. The key distinguishing feature for US9201834 would be the programmable nature of the data rates and signal swings on its transmission buses.

• US 7,203,778 B2

  • Inventors: Kirihata; Toshiaki et al.
  • Publication Date: April 10, 2007
  • Brief Description: This patent describes a semiconductor memory device that can operate at various data rates and voltage swings, allowing for flexible operation modes.
  • Potential Anticipation for US9201834 Claims: This reference is highly relevant to Claim 1 of US9201834, especially regarding the "programmable transmitting or receiving data rate" and "programmable transmitting or receiving signal swing" of the first and second transmission buses. The scope of "programmable" in US9201834's claims and how it differs from the flexible operation modes in US 7,203,778 B2 would be critical in assessing anticipation.

• US 7,370,166 B2

  • Inventors: Lee; Kye Hyun et al.
  • Publication Date: May 6, 2008
  • Brief Description: This patent describes a memory module with stacked memory devices and an interposer, focusing on improving signal integrity and reducing noise in high-speed memory systems.
  • Potential Anticipation for US9201834 Claims: This patent could be relevant to the structural aspects mentioned in the detailed description of US9201834, particularly those related to stacking memory ICs and using interposers (e.g., as described in FIGS. 4-6 and associated text). While not directly addressing the programmable bus features of Claim 1, it provides context for the physical implementation of high-speed memory modules.

• US 7,921,228 B2

  • Inventors: Oku; Yuji et al.
  • Publication Date: April 5, 2011
  • Brief Description: This patent discusses a stacked semiconductor device with through-silicon vias (TSVs) for interconnections between stacked chips, aiming to reduce package size and improve performance.
  • Potential Anticipation for US9201834 Claims: This patent is particularly relevant to Claim 5 of US9201834, which specifies the presence of "at least one through silicon via (TSV) exists within a non-active circuit region surrounding or partially surrounding an active circuit region of each of the memory cell array ICs." The general concept of using TSVs in stacked memory is covered, but the specific placement "within a non-active circuit region" and the stated benefits (e.g., EMI shielding, heat dissipation, noise isolation as discussed in the detailed description of US9201834) would need to be carefully compared.

• US 8,245,091 B2

  • Inventors: Kim; Hong Seok et al.
  • Publication Date: August 14, 2012
  • Brief Description: This patent describes a semiconductor memory device and system with reconfigurable input/output (I/O) interfaces, allowing for flexible configuration of data width and operating modes.
  • Potential Anticipation for US9201834 Claims: This patent is highly relevant to Claim 1 and Claim 3 of US9201834 due to its focus on reconfigurable I/O interfaces and flexible configuration of data width. The programmable bus width (Claim 3) and programmable data rate/signal swing (Claim 1) in US9201834 would need to demonstrate novel distinctions from the reconfigurable aspects of US 8,245,091 B2 to overcome potential anticipation.

• US 2004/0009653 A1

  • Inventors: Kumamoto; Yoshihiro
  • Publication Date: January 15, 2004
  • Brief Description: This application describes a semiconductor device with a reconfigurable data bus width and control signals to support different memory configurations.
  • Potential Anticipation for US9201834 Claims: This publication is relevant to Claim 1 and Claim 3, especially concerning the "first programmable bus width" and "first programmable data width" of the first transmission bus. The reconfigurable data bus width described could potentially anticipate the programmable bus width aspects of US9201834.

• US 2008/0022066 A1

  • Inventors: Lin; Yen-Chih et al.
  • Publication Date: January 24, 2008
  • Brief Description: This application details a memory system with multiple memory devices and a controller that can adjust operating parameters, including data rates and signal swings, for efficient operation.
  • Potential Anticipation for US9201834 Claims: This reference is highly relevant to Claim 1 due to its discussion of adjusting operating parameters such as data rates and signal swings. The specific definition and implementation of "programmable" in US9201834 for both transmitting and receiving would be key to differentiating it from this prior art.

• US 2009/0070542 A1

  • Inventors: Lin; Yen-Chih et al.
  • Publication Date: March 12, 2009
  • Brief Description: This application describes a memory device with a flexible interface that can be configured for different bus widths and data transfer modes.
  • Potential Anticipation for US9201834 Claims: Similar to US 2004/0009653 A1 and US 2008/0022066 A1, this publication is relevant to Claim 1 and Claim 3, as it describes a flexible interface configurable for various bus widths and data transfer modes, potentially anticipating the programmable bus width, data width, and address width of US9201834's transmission buses.

• US 2011/0088019 A1

  • Inventors: Li; Qi et al.
  • Publication Date: April 14, 2011
  • Brief Description: This application discloses methods and apparatus for configuring a memory controller to optimize performance based on memory characteristics and system requirements.
  • Potential Anticipation for US9201834 Claims: This reference could be relevant to the underlying concept of optimizing memory performance through configuration, which underpins the "programmable" features of US9201834's transmission buses in Claim 1. However, the specific inventive steps in US9201834 related to the reconfigurable high-speed memory chip module itself and its two distinct programmable buses would be the focus of differentiation.

Obviousness Analysis of US Patent 9201834 under 35 U.S.C. § 103

This analysis of US Patent 9201834 proceeds under 35 U.S.C. § 103, which dictates that a patent claim is unpatentable if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The effective priority date for US9201834 is October 11, 2011.

The provided patent text, specifically the "Description of the Prior Art" section, outlines the general state of the art at the time of the invention. However, it does not explicitly name or cite specific prior art patents or publications as required for a traditional obviousness analysis with specific references. Therefore, this analysis will be based on the general understanding of the prior art and common knowledge of a PHOSITA in the field of memory chip modules and electronic devices, as implied by the problems the patent aims to solve.

General Prior Art as Described in US9201834

The patent identifies the following shortcomings in the prior art:

1. Standardized, inflexible memory modules: Memories were typically designed as standard modules (e.g., JEDEC-compliant) that were independent from logic units, leading to fixed bus widths, signal levels, and operating frequencies. This resulted in "lower manufacturability, less flexibility and higher system migration cost among different process technology generations and different applications."
2. Integration challenges for memory and logic units: Integrating memories (often using advanced semiconductor processes) with logic units (using different processes) led to "poorer heat dissipation, higher power consumption and bad noise interference."

A PHOSITA in 2011, working in the field of semiconductor device packaging and memory system design, would have possessed knowledge of memory architectures, bus interfaces, power management techniques, thermal management solutions, and electromagnetic interference (EMI) shielding principles.

Obviousness of Independent Claim 1

Claim 1 describes a reconfigurable high-speed memory chip module comprising:

• A type of memory cell array group with multiple memory cell array ICs.
• A first transmission bus (coupled to the memory group) having a first programmable transmitting or receiving data rate and signal swing.
• A second transmission bus (coupled to a logic unit) having a second programmable transmitting or receiving data rate and signal swing.
• A logic unit (coupled to the first bus) for accessing the memory group and converting a first set of parallel data from the first bus into a second set of parallel data for the second bus.

Combination of Prior Art Elements and Motivation:

A PHOSITA would have been motivated to combine known elements to achieve the claimed reconfigurable memory module, driven by the desire to overcome the inflexibility and integration challenges described in the prior art.

1. Programmable Data Rate and Signal Swing (First and Second Transmission Buses):

   • Prior Art Problem: The patent explicitly states that prior art JEDEC standards dictated fixed bus widths, signal levels, and data rates, leading to "less flexibility and higher system migration cost."
   • Motivation: To address the lack of flexibility and high migration costs, a PHOSITA would have been motivated to introduce programmability into the memory interface parameters. Techniques for dynamic voltage and frequency scaling were well-known in processor and system-on-chip (SoC) design by 2011 for optimizing power consumption and performance. Applying similar programmability to memory bus interfaces, including data rates and signal swings, would have been an obvious design choice to allow a memory module to adapt to various logic units and application requirements, thereby enhancing flexibility and reducing migration costs. The patent itself notes that programmability allows for "higher performance, lower operating power, lower standby power, longer battery life or another functional enhancement," indicating these were desired outcomes in the prior art.

2. Logic Unit as a Data Converter and Bus Bridge:

   • Prior Art Knowledge: The concept of a dedicated logic unit (e.g., a memory controller or an interface bridge) to manage memory access and adapt data formats between different bus architectures was standard practice. For instance, converting between wider internal memory buses and narrower external system buses (parallel-to-parallel or parallel-to-serial conversion) was a common function of memory controllers in various computing systems.
   • Motivation: Given the need for flexibility between the internal memory array group and an external processor, a PHOSITA would naturally employ a logic unit to serve as an intermediary. This logic unit would enable the adaptation of data (e.g., converting a wider internal parallel data set to a potentially narrower external parallel data set, as described in the patent) to optimize communication with different system processors (ASICs or SOCs) while maintaining high-speed access to the memory arrays.

3. Two Transmission Buses with Different Characteristics:

   • Prior Art Knowledge: System architects commonly employed different bus structures and protocols for internal chip-to-chip communication within a module and external module-to-system communication. It was well-understood that an internal bus could be optimized for high bandwidth and low latency memory access, while an external bus could be designed for compatibility with a system processor interface.
   • Motivation: The motivation would be to optimize performance and power efficiency. The patent explains that "system power efficiency can be higher if bit width of the first transmission bus is wider and with smaller signal swing comparing to the second transmission bus." Conversely, "the system data transmission bandwidth and noise level can be best optimized for another application environments or conditions if the second transmission bus is wider and with smaller signal swing comparing to the first transmission bus." These statements indicate that the trade-offs and benefits of such an architecture were known and desired in the prior art.

Therefore, a PHOSITA, motivated by the known desire for more flexible, efficient, and adaptable memory solutions to overcome the limitations of rigid standards and complex integration, would have found it obvious to combine the well-known principles of programmable interfaces, bus bridging logic, and differentiated bus architectures to arrive at the subject matter of Claim 1.

Obviousness of Independent Claim 5

Claim 5 depends on Claim 1 and further specifies:

• "...wherein at least one through silicon via (TSV) exists within a non-active circuit region surrounding or partially surrounding an active circuit region of each of the memory cell array ICs."

Combination of Prior Art Elements and Motivation:

A PHOSITA would have been motivated to incorporate TSVs in the described manner, driven by the need to address the "poorer heat dissipation, higher power consumption and bad noise interference" problems in integrated memory and logic systems, as highlighted in the patent's own description of prior art.

1. Use of TSVs for EMI Shielding and Heat Dissipation:

   • Prior Art Problem: The prior art suffered from "bad noise interference" and "poorer heat dissipation" in integrated memory/logic systems.
   • Prior Art Knowledge: Through-Silicon Vias (TSVs) were a known technology for vertical interconnections in 3D integrated circuits by 2011. The concept of using conductive structures (like metal fences formed by TSVs or other means) for EMI shielding and as paths for heat dissipation was well-established in semiconductor packaging and electromagnetic theory. The patent itself notes that the benefits of using TSVs to form a metal fence for "better EMI shielding effect, better heat dissipation capability, and an better external noise isolation function" are "based on the magnetic-electronic theory available today." This acknowledges the underlying principles were already understood.
   • Motivation: A PHOSITA, actively seeking to mitigate noise and improve thermal performance in stacked or integrated ICs, would naturally consider deploying TSVs for these purposes.

2. Placement of TSVs within Non-Active Circuit Regions:

   • Prior Art Knowledge: It was a common design practice in integrated circuit layout to place power/ground routing, decoupling capacitors, and other non-active structures in peripheral or "non-active" areas of a chip to minimize interference with sensitive active circuitry and to optimize the utilization of the more valuable active circuit area.
   • Motivation: Combining the known benefits of TSVs for shielding/thermal management with the established practice of utilizing non-active regions for such structures would be an obvious design choice. The patent itself explains that using TSVs in non-active regions "can save power or ground supply line area within an active circuit region... to improving the manufacturing yield and cost," and improve dicing yield. These benefits reflect known design goals in the prior art.

3. Arrangement of TSVs to Surround or Partially Surround Active Regions:

   • Prior Art Knowledge: The principle of creating a "Faraday cage" or similar shielding structures by surrounding a sensitive area with conductive material was a fundamental concept in electrical engineering.
   • Motivation: To effectively shield an active circuit region from external noise or to channel heat away, a PHOSITA would predictably arrange conductive elements, such as TSVs connected to power or ground, to surround or partially surround the active region. This forms a "metal fence" as described in the patent, which is a direct application of known shielding principles to the problem of "bad noise interference."

Therefore, a PHOSITA, motivated to solve the acknowledged problems of heat, power, and noise in integrated memory and logic components, and conversant with TSV technology and fundamental IC design principles regarding shielding and thermal management, would have found it obvious to integrate TSVs into the non-active regions of memory ICs within a module as described in Claim 5, to form a metal fence for EMI shielding and improved heat dissipation.