US 9164942

Here is a concise summary of US patent 9164942:

US Patent 9164942: Summary

• Title: High speed memory chip module and electronics system device with a high speed memory chip module
• Original Assignee: Etron Technology Inc
• Current Assignee: Wecrevention Inc (as of September 11, 2025)
• Inventors: Weng-Dah Ken, Nicky Lu
• Filing Date: October 11, 2012 (Application No. US13/649,131)
• Issue Date: October 20, 2015
• Abstract: A high speed memory chip module includes a type of memory cell array group and a logic unit. The memory cell array group comprises multiple memory cell array integrated circuits (ICs), each having a data bus and at least one memory cell array, corresponding to a first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length from a first MOSFET process. A logic unit accesses this memory cell array group via a first transmission bus, where the bus width of the first transmission bus is wider than the data bus of each memory cell array IC. The logic unit corresponds to a second MOSFET process with a second MOSFET gate length, which is shorter than the first MOSFET gate length.
• Plain-Language Overview of Independent Claims:
  • Independent Claim 1 (High speed memory chip module): This claim describes a high-speed memory chip module comprising a group of multiple memory chips and a logic unit. Each memory chip has its own input/output (I/O) data bus and is manufactured using a "first" semiconductor process characterized by a specific (longer) MOSFET gate length. The logic unit accesses these memory chips via a "first" internal transmission bus. This "first" bus is wider than the individual I/O data buses of the memory chips. The logic unit itself is manufactured using a "second" semiconductor process characterized by a shorter MOSFET gate length than the "first" process. The logic unit is also configured to convert the parallel data from the wider "first" transmission bus into a "second" set of parallel data for transmission over a "second" transmission bus.
  • Independent Claim 19 (Electronics system device): This claim describes an electronic system that incorporates a high-speed memory chip module. The system includes an Application-Specific Integrated Circuit (ASIC) processor, a group of multiple memory chips (each with an I/O data bus), and a logic unit. The logic unit accesses the memory chips through a "first" transmission bus that is wider than the individual I/O data buses of the memory chips. The logic unit then converts this "first" set of parallel data into a "second" set of parallel data via a "second" transmission bus, and sends this "second" set of data to the ASIC processor. The ASIC processor performs a function based on this "second" set of data while operating. A key feature is that the bit widths of the "first" and "second" sets of parallel data are different.

Litigation Notes (as of April 26, 2026):
The patent record for US9164942B2 indicates that the patent family is involved in litigation.

• A PTAB case, IPR2026-00239, has been filed and is currently pending.
• Multiple US cases have been filed in the Texas Western District Court and Texas Eastern District Court.

As of the current date (April 26, 2026), a search of CAFC 2026 dockets did not explicitly return specific cases directly listing patent US9164942B2, beyond general scheduled case information for May and June 2026. Therefore, while PTAB litigation for 2026 is noted, any subsequent appeals to the CAFC specifically involving this patent do not appear in the readily available scheduled dockets for 2026 at this time. It is possible that the IPR2026-00239 case is still pending at the PTAB and has not yet progressed to an appeal at the CAFC.

US Patent 9,164,942 has been involved in the following litigation:

Inter Partes Review (IPR)

• Case Number: IPR2026-00239
• Status: Pending
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Plaintiff(s): Not explicitly stated, but initiated by a "Petitioner". Unified Patents tracks this case.
• Defendant(s): The patent owner, Wecrevention Inc.
• Filing Date: The IPR was filed by Unified Patents, Inc.. While a specific filing date for IPR2026-00239 is not provided in the snippets, Unified Patents' portal shows it as pending.
• Outcome/Current Status: Pending.

District Court Cases

The patent is currently involved in multiple district court cases in Texas.

• Jurisdiction: Texas Western District Court

• Case Number: 7:25-cv-00458

• Outcome/Current Status: Active.

• Jurisdiction: Texas Eastern District Court

• Case Number: 2:25-cv-01040

• Outcome/Current Status: Active.

• Jurisdiction: Texas Eastern District Court

• Case Number: 2:25-cv-01008

• Outcome/Current Status: Active.

• Jurisdiction: Texas Eastern District Court

• Case Number: 2:25-cv-00951

• Outcome/Current Status: Active.

For these district court cases, the specific plaintiffs and defendants are not detailed in the provided search results, but they are all listed as active.

Proceedings overview

One Inter Partes Review (IPR) proceeding, IPR2026-00239, is currently pending against US Patent 9,164,942. This IPR challenges claims of the patent, meaning the patent's validity is presently under review, and no claims have been invalidated or sustained by a final written decision at this time. This gives a defendant the defensive posture that the patent's claims are actively being challenged, which may impact assertion strategies until the IPR reaches a resolution.

IPR2026-00239 — [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Wecrevention Inc

• Type: Inter Partes Review
• Filed: 2026-02-13
• Status: Pending. This IPR is currently in the pre-institution phase, awaiting a decision from the PTAB on whether to institute a trial. The last modification was on 2026-05-20.
• Judge panel: Not yet public, as the institution decision has not been issued.
• Petition grounds: The petition was filed by Apple Inc. and challenges claims based on prior art under 35 U.S.C. § 102 (novelty) and/or § 103 (obviousness). The specific claims challenged and prior art asserted are not yet publicly detailed in this current context, but Apple Inc. is the petitioner.
• Institution decision: Pending. The PTAB has a statutory deadline of six months from the filing date to decide whether to institute the IPR. Given the filing date of 2026-02-13, the institution decision is expected by approximately 2026-08-13.
• Final Written Decision (if issued): Not applicable; the proceeding is pending.
• Settlement / termination: Not applicable; the proceeding is pending.
• Appeal: Not applicable; the proceeding is pending.
• Defensive value: This active IPR proceeding indicates that the validity of the patent's claims is under scrutiny. For a defendant, this creates uncertainty around the patent's enforceability. If the IPR is instituted and ultimately leads to claims being canceled, it would significantly weaken any infringement theories built upon those claims. If institution is denied or claims are upheld, it would strengthen the patent owner's position.

Strategic summary

Currently, all claims of US 9,164,942 remain untested by a final written decision from the PTAB. There is one active IPR, IPR2026-00239, challenging the patent. Until an institution decision is rendered, and potentially a Final Written Decision, the validity of the claims remains in flux.

The estoppel landscape under § 315(e)(2) will only become relevant if IPR2026-00239 is instituted and proceeds to a Final Written Decision. At that point, Apple Inc. (the petitioner) and its privies would be barred from asserting in future civil actions or other USPTO proceedings any ground of invalidity that they raised or reasonably could have raised during the IPR. As the IPR is in its early stages, the full scope of potential prior-art grounds remains open for other potential challengers not in privity with Apple Inc.

A key pattern signal is the involvement of Unified Patents, which is listed as the petitioner for IPR2026-00239. Unified Patents is a defensive aggregator that typically files IPRs against patents being asserted in litigation to mitigate patent troll activity. This suggests that US 9,164,942 may be involved in or targeted for assertion against operating companies. The patent owner has changed recently from Etron Technology Inc. to Valuecreation Technology, Inc., and then to Wecrevention Inc.

Recommended next steps

• Since IPR2026-00239 is pending, a crucial milestone to watch is the institution decision deadline, which is around 2026-08-13. The decision will be publicly available on the PTAB E2E system.
• Monitor the PTAB trial docket for IPR2026-00239 for updates on the institution decision and to review the petition and patent owner preliminary response once available. This will provide specific details on the claims challenged, the prior art asserted by Apple Inc., and the patent owner's arguments.
• Given that Unified Patents has filed the IPR, it is highly probable that this patent has been asserted against one of their members. Understanding the litigation landscape surrounding US 9,164,942 would provide valuable context.

Inventors

• Weng-Dah Ken (Etron Technology Inc)
• Nicky Lu (Etron Technology Inc)

No unusual patterns of inventors departing the original assignee within 12 months of filing are determinable from the provided text.

Original assignee

Etron Technology Inc.
Etron Technology Inc. is a fabless IC design company that provides a range of products, including USB 3.0 host controllers, memory, and other IC solutions. Based on their product offerings, it is highly likely they shipped products embodying the claims, particularly in the realm of high-speed memory and associated controllers. The current status of Etron Technology Inc. is operating.

Assignment timeline

• 2012-10-09 (executed) / recorded 2012-10-11 — Reel 029108/0695

  • Conveyance: Assignment
  • Assignor: Ken, Weng-Dah; Lu, Nicky
  • Assignee: ETRON TECHNOLOGY, INC.
  • Correspondent: Not specified in the provided text.
  • Context: Original assignment from inventors to the filing company.

• 2023-05-18 (executed) / recorded 2025-09-08 — Reel 072191/0373

  • Conveyance: Assignment
  • Assignor: ETRON TECHNOLOGY, INC.
  • Assignee: VALUECREATION TECHNOLOGY, INC.
  • Correspondent: Not specified in the provided text.
  • Context: Transfer of assignor's interest.

• 2025-05-01 (executed) / recorded 2025-09-11 — Reel 072228/0495

  • Conveyance: Assignment
  • Assignor: VALUECREATION TECHNOLOGY, INC.
  • Assignee: WECREVENTION, INC.
  • Correspondent: Not specified in the provided text.
  • Context: Transfer of assignor's interest.

Timeline diagram

timeline
    title Ownership of US 9164942
    2011 : Priority date
    2012 : Filed by Etron Technology Inc
         : Assigned to Etron Technology Inc
    2015 : Issued to Etron Technology Inc
    2023 : Assigned to Valuecreation Technology
    2025 : Assigned to Wecrevention Inc

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer from ETRON TECHNOLOGY, INC. to VALUECREATION TECHNOLOGY, INC. (Reel 072191/0373) and then to WECREVENTION, INC. (Reel 072228/0495) suggests shell entities. VALUECREATION TECHNOLOGY, INC. and WECREVENTION, INC. do not appear to be product-shipping companies, and "VALUECREATION TECHNOLOGY" and "WECREVENTION" sound like holding companies. WECREVENTION, INC. is noted as being in Texas.

2. Known asserter in the chain — unclear. While the pattern of transfers suggests NPE activity, neither VALUECREATION TECHNOLOGY, INC. nor WECREVENTION, INC. are explicitly identified as known high-frequency NPEs in the provided public lists (Acacia Research Corp, Marathon Patent Group, etc.) or in the provided text. However, the patent is currently involved in litigation, including an IPR case (IPR2026-00239) and district court cases in the Texas Western and Eastern District Courts, which are common venues for NPE assertions.

3. Repeat correspondent across the chain — not present. The correspondent information is not available in the provided text for any of the assignment records, so this signal cannot be evaluated.

4. Cascading transfers — present. There are two consecutive assignments within a short timeframe (executed 2023-05-18, recorded 2025-09-08; executed 2025-05-01, recorded 2025-09-11). The first transfer to VALUECREATION TECHNOLOGY, INC. and then quickly to WECREVENTION, INC. within roughly two years, with both recordings occurring in September 2025, fits this pattern (Reel 072191/0373 and Reel 072228/0495).

5. Pre-litigation transfer — present. The assignment to WECREVENTION, INC. was executed on 2025-05-01 and recorded on 2025-09-11 (Reel 072228/0495). Unified Patents indicates that US cases were filed in the Texas Eastern and Western District Courts starting in 2025, with specific case numbers (e.g., 7:25-cv-00458, 2:25-cv-01040, 2:25-cv-01008, 2:25-cv-00951). This timing suggests the transfer to WECREVENTION, INC. may have been made in preparation for these assertions.

6. Bankruptcy fire-sale — not present. There is no indication in the provided text that Etron Technology Inc. filed for bankruptcy.

7. Privateering — unclear. While Etron Technology Inc. transferred the patent, there is no direct evidence in the provided information (such as SEC filings or specific reports) to confirm that VALUECREATION TECHNOLOGY, INC. or WECREVENTION, INC. are asserting on behalf of Etron Technology Inc. against its competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator like RPX, AST, LOT Network, Unified Patents, or Open Invention Network.

Verdict

NPE — high confidence

This verdict is based on several strong signals: the presence of cascading transfers between entities with non-operating-company names (VALUECREATION TECHNOLOGY, INC. and WECREVENTION, INC.), and the clear timing of a pre-litigation transfer to WECREVENTION, INC. just prior to the initiation of multiple infringement suits in known NPE-favorable jurisdictions in Texas in 2025. These patterns strongly indicate that the patent has been transferred for assertion purposes.

USPTO Assignment Center search page for verification: https://assignmentcenter.uspto.gov/

The USPTO database search for patent number US9164942B2 confirms its existence. It was issued on October 20, 2015, from application number 13/649,131, filed on October 11, 2012. The first named inventor is Weng-Dah Ken, and the original assignee is Etron Technology, Inc.. The patent is currently active and is expected to expire on June 27, 2034.

Here's an analysis of the most relevant prior art cited against US9164942B2, along with potential anticipation under 35 U.S.C. § 102. The analysis focuses on patents explicitly listed as "Citations" or "Patent Citations" in the provided text.

Most Relevant Prior Art for US9164942B2:

1. US6317377B1

• Full Citation: US6317377B1, "Semiconductor memory device"
• Publication/Filing Date: Filed April 12, 1999; Published/Issued November 13, 2001.
• Brief Description: This patent describes a semiconductor memory device.
• Potential Anticipation (35 U.S.C. § 102): Without more detailed information on the claims of US6317377B1, it is difficult to precisely determine which claims of US9164942B2 it anticipates. However, given its broad title "Semiconductor memory device," it could potentially anticipate fundamental aspects of a memory chip module, such as a memory cell array group (Claim 1) or individual memory cell array ICs.

2. US20040246801A1

• Full Citation: US20040246801A1, "Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation"
• Publication/Filing Date: Filed June 4, 2003; Published December 9, 2004.
• Brief Description: This application describes integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation.
• Potential Anticipation (35 U.S.C. § 102): This reference might anticipate aspects related to data transmission rates and modes of operation. Specifically, claims like Claim 9 or Claim 10 of US9164942B2, which discuss different transmitting and receiving data rates for the first and second transmission buses, could be potentially anticipated.

3. US20040260864A1

• Full Citation: US20040260864A1, "Reconfigurable memory module and method"
• Publication/Filing Date: Filed June 19, 2003; Published December 23, 2004.
• Brief Description: This patent describes a reconfigurable memory module and method.
• Potential Anticipation (35 U.S.C. § 102): The concept of a "reconfigurable memory module" could potentially anticipate aspects of US9164942B2 related to the memory cell array group and its interaction with the logic unit. This could potentially anticipate elements of Claim 1 related to the memory cell array group, and potentially claims related to data handling if "reconfigurable" implies different data paths or widths.

4. US7013359B1

• Full Citation: US7013359B1, "High speed memory interface system and method"
• Publication/Filing Date: Filed December 21, 2001; Published/Issued March 14, 2006.
• Brief Description: This patent describes a high speed memory interface system and method.
• Potential Anticipation (35 U.S.C. § 102): The title "High speed memory interface system and method" directly suggests anticipation of the core functionality of US9164942B2. This reference could potentially anticipate Claim 1 (high speed memory chip module), and specifically aspects of the first and second transmission buses, their widths, and data transfer (Claim 1, Claim 5).

5. US20070005831A1

• Full Citation: US20070005831A1, "Semiconductor memory system"
• Publication/Filing Date: Filed June 30, 2005; Published January 4, 2007.
• Brief Description: This patent describes a semiconductor memory system.
• Potential Anticipation (35 U.S.C. § 102): Similar to US6317377B1, the general nature of a "semiconductor memory system" could potentially anticipate the overall structure of the high speed memory chip module (Claim 1) or the electronics system device (Claim 19).

6. US7206876B2

• Full Citation: US7206876B2, "Input/output interface of an integrated circuit device"
• Publication/Filing Date: Filed April 15, 2003; Published/Issued April 17, 2007.
• Brief Description: This patent describes an input/output interface of an integrated circuit device.
• Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of the I/O data buses of the memory cell array ICs (Claim 1) and the transmission buses (Claim 1). The concept of an I/O interface is central to how the memory and logic units communicate.

7. US7245239B2

• Full Citation: US7245239B2, "Synchronous parallel/serial converter"
• Publication/Filing Date: Filed January 14, 2005; Published/Issued July 17, 2007.
• Brief Description: This patent describes a synchronous parallel/serial converter.
• Potential Anticipation (35 U.S.C. § 102): This patent directly addresses a "parallel-to-serial converter," which is a key component described in US9164942B2 (Claim 5). This would very strongly anticipate Claim 5 and potentially other claims that rely on this conversion functionality.

8. US7385281B2

• Full Citation: US7385281B2, "Semiconductor integrated circuit device"
• Publication/Filing Date: Filed December 25, 2003; Published/Issued June 10, 2008.
• Brief Description: This patent describes a semiconductor integrated circuit device.
• Potential Anticipation (35 U.S.C. § 102): This general patent on a "semiconductor integrated circuit device" could potentially anticipate the fundamental integrated circuit components described in US91649942B2, such as the memory cell array ICs or the logic unit (Claim 1).

9. US20090024790A1

• Full Citation: US20090024790A1, "Memory circuit system and method"
• Publication/Filing Date: Filed July 31, 2006; Published January 22, 2009.
• Brief Description: This patent describes a memory circuit system and method.
• Potential Anticipation (35 U.S.C. § 102): The title "Memory circuit system and method" suggests it could potentially anticipate the overall memory system described in US9164942B2, including the memory cell array group and its interaction with a logic unit (Claim 1).

10. US20090039492A1

• Full Citation: US20090039492A1, "Stacked memory device"
• Publication/Filing Date: Filed August 6, 2007; Published February 12, 2009.
• Brief Description: This patent describes a stacked memory device.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant as US9164942B2 describes various stacked configurations (e.g., FIGS. 2, 3, 5, 6). Therefore, claims related to the stacking of memory cell array ICs and logic units (e.g., descriptions in the detailed description referring to stacking, and potentially how TSVs are used in a stacked context), could be anticipated by this reference.

11. US7546497B2

• Full Citation: US7546497B2, "Semiconductor memory device and data write and read method thereof"
• Publication/Filing Date: Filed May 24, 2005; Published/Issued June 9, 2009.
• Brief Description: This patent describes a semiconductor memory device and data write and read method thereof.
• Potential Anticipation (35 U.S.C. § 102): This reference could anticipate the fundamental operation of accessing memory, including writing and reading data, which is a core function described in Claim 1 of US9164942B2 (logic unit accessing the memory cell array group).

12. US7680966B1

• Full Citation: US7680966B1, "Memory interface including generation of timing signals for memory operation"
• Publication/Filing Date: Filed June 29, 2004; Published/Issued March 16, 2010.
• Brief Description: This patent describes a memory interface including generation of timing signals for memory operation.
• Potential Anticipation (35 U.S.C. § 102): This patent directly relates to memory interfaces, a key aspect of US9164942B2 (first and second transmission buses). It could potentially anticipate the design and operation of these interfaces and the data transfer across them (Claim 1).

13. US20100235554A1

• Full Citation: US20100235554A1, "Reconfigurable point-to-point memory interface"
• Publication/Filing Date: Filed October 19, 2007; Published September 16, 2010.
• Brief Description: This patent describes a reconfigurable point-to-point memory interface.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant due to its focus on a "reconfigurable point-to-point memory interface." This could potentially anticipate various aspects of the first and second transmission buses and their configuration (Claim 1, Claim 5), especially if the reconfigurability relates to bus width or data rates.

14. US7810017B2

• Full Citation: US7810017B2, "Variable sector-count ECC"
• Publication/Filing Date: Filed March 20, 2006; Published/Issued October 5, 2010.
• Brief Description: This patent describes a variable sector-count ECC.
• Potential Anticipation (35 U.S.C. § 102): While not directly about the physical bus structure, if US9164942B2's claims implicitly rely on certain data handling or error correction strategies that are standard in memory systems with variable data widths, then aspects of this patent could be relevant. However, without more explicit connections in US9164942B2's claims to ECC, direct anticipation is less likely for most claims.

15. US7903685B2

• Full Citation: US7903685B2, "System and method for reformatting data"
• Publication/Filing Date: Filed June 3, 2003; Published/Issued March 8, 2011.
• Brief Description: This patent describes a system and method for reformatting data.
• Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate Claim 1 and Claim 5 of US9164942B2, specifically the logic unit's function of "converting the first set of parallel data of the first transmission bus into a second set of parallel data through a second transmission bus." Data reformatting is directly analogous to parallel-to-serial conversion and changing bit widths.

16. US8036052B2

• Full Citation: US8036052B2, "Semiconductor memory device and test method thereof"
• Publication/Filing Date: Filed February 22, 2007; Published/Issued October 11, 2011.
• Brief Description: This patent describes a semiconductor memory device and test method thereof.
• Potential Anticipation (35 U.S.C. § 102): Similar to other general memory device patents, this could potentially anticipate the fundamental structure of the memory cell array ICs (Claim 1). If any claims of US9164942B2 implicitly rely on specific testability features that are common in semiconductor memory devices, there might be a broader anticipation.

17. US8473653B2

• Full Citation: US8473653B2, "Semiconductor device, control method for the semiconductor device and information processing system including the same"
• Publication/Filing Date: Filed October 9, 2009; Published/Issued June 25, 2013.
• Brief Description: This patent describes a semiconductor device, control method for the semiconductor device and information processing system including the same.
• Potential Anticipation (35 U.S.C. § 102): This broad patent could potentially anticipate the overall electronics system device (Claim 19) or the high speed memory chip module (Claim 1) if it details similar integrated components and their control.

18. US8803545B2

• Full Citation: US8803545B2, "Semiconductor device semiconductor device testing method, and data processing system"
• Publication/Filing Date: Filed January 18, 2010; Published/Issued August 12, 2014.
• Brief Description: This patent describes a semiconductor device, semiconductor device testing method, and data processing system.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous broad patents, this could potentially anticipate the overall electronics system device (Claim 19) or the high speed memory chip module (Claim 1) if it covers similar integrated components and their functionality. The data processing aspect might also be relevant to the ASIC processor and its function (Claim 19).

Prior Art from "Family Cites Families" (Less direct, but worth noting):

While "Family Cites Families" usually indicates a broader field of art rather than direct anticipation, some of these references might contain elements relevant to US9164942B2. Without specific claim analysis for each, the potential for anticipation is less direct than the "Patent Citations" listed above.

• US5175841A: "Data processing device with multiple on-chip memory buses" (Filed March 13, 1987; Issued December 29, 1992). This could be relevant to the concept of multiple buses and varying bus widths (Claim 1).
• US5375083A: "Semiconductor integrated circuit including a substrate having a memory cell array surrounded by a well structure" (Filed February 4, 1993; Issued December 20, 1994). This could be relevant to the physical structure of memory cell arrays.
• JPH10134022A: "Semiconductor integrated circuit" (Filed October 31, 1996; Published May 22, 1998). General integrated circuit technology.
• US6009023A: "High performance DRAM structure employing multiple thickness gate oxide" (Filed May 26, 1998; Issued December 28, 1999). Could be relevant to the MOSFET process and gate lengths (Claim 1).
• EP1157419A1: "Non-volatile memory cells and periphery" (Filed December 21, 1999; Published November 28, 2001). Could be relevant to the memory cell array ICs, especially flash or NVM (Claim 2).
• DE10245037B4: "Method of designing DRAM semiconductor memory devices" (Filed September 26, 2002; Published August 23, 2007). Could be relevant to the DRAM IC (Claim 2).
• CN100336045C: "Multifunction chipset and related method" (Filed November 19, 2004; Published September 5, 2007). Could be broadly relevant to the system device (Claim 19) if it integrates memory and logic.
• US7390700B2: "Packaged system of semiconductor chips having a semiconductor interposer" (Filed April 7, 2006; Issued June 24, 2008). Highly relevant to the interposer embodiments (Claim 3, Claim 4, Claim 20, Claim 21).
• US7569918B2: "Semiconductor package-on-package system including integrated passive components" (Filed May 1, 2006; Issued August 4, 2009). Highly relevant to the Package-in-Package (PIP), Package on package (POP), or System in Package (SIP) configurations mentioned in the description, and potentially Claim 1's overall module.
• KR100867640B1: "System-on-Chip with Image Processing Memory with Multiple Access Paths" (Filed February 6, 2007; Published November 10, 2008). Could be relevant to the ASIC/SOC processor and memory access (Claim 5, Claim 19).
• CN101752351A: "Programmable array module" (Filed December 4, 2008; Published June 23, 2010). Could be broadly relevant to the memory cell array group (Claim 1) or the logic unit's functionality.

Obviousness Analysis of US Patent 9164942 under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 9164942 (the '942 patent) based on the prior art references cited within the patent, in accordance with 35 U.S.C. § 103. The '942 patent aims to address challenges in integrating memory and logic units, specifically concerning power consumption, heat dissipation, noise interference, and manufacturing difficulty, by proposing a high-speed memory chip module with differentiated semiconductor processes and efficient data transmission.

Background of the Invention (as described in US9164942)

The '942 patent identifies several problems in the prior art concerning memory and logic integration:

• Memories are typically designed as standard modules, independent of specific logic units, rather than for predetermined logic units.
• Integrating discrete memories (often using more advanced semiconductor processes for density) with logic units (using different process generations) results in poorer heat dissipation, higher power consumption, bad noise interference, and manufacturing difficulties.

The independent claims (Claim 1 and Claim 19) of the '942 patent describe a high-speed memory chip module and an electronics system device incorporating such a module.

Obviousness of Claim 1: High Speed Memory Chip Module

Claim 1 Elements:

1. A high-speed memory chip module.
2. A type of memory cell array group comprising multiple memory cell array integrated circuits (ICs), each with an I/O data bus and at least one memory cell array.
3. Each memory cell array IC corresponds to a first MOSFET process with a first MOSFET gate length.
4. A logic unit for accessing the memory cell array group via a first transmission bus, transmitting a first set of parallel data.
5. The bus width of the first transmission bus is wider than the bus width of the I/O data bus of each memory cell array IC.
6. The logic unit corresponds to a second MOSFET process with a second MOSFET gate length.
7. The first MOSFET gate length is longer than the second MOSFET gate length (i.e., memory uses a larger/older process node than logic).
8. The logic unit converts the first set of parallel data from the first transmission bus into a second set of parallel data via a second transmission bus.

Combination of Prior Art References for Claim 1:
A combination of the following prior art references, along with the ordinary skill in the art, would render Claim 1 obvious:

1. US20090039492A1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): "Stacked memory device"
2. US7245239B2 (Infineon Technologies Ag): "Synchronous parallel/serial converter"
3. US6009023A (Etron Technology, Inc.): "High performance DRAM structure employing multiple thickness gate oxide" and/or general knowledge of semiconductor process technology.

Explanation of Obviousness and Motivation:

A person having ordinary skill in the art (PHOSITA) in memory system design, faced with the problems of efficiently integrating memory and logic units with differing process technologies (as stated in the '942 patent's background), would have been motivated to combine the teachings of these references.

• Integrated Memory and Logic with Differentiated Process Technologies (Elements 2, 3, 4, 6, 7):

  • US20090039492A1 teaches a "stacked memory device". It would be obvious to a PHOSITA to implement a "type of memory cell array group" (Claim 1, element 2) using multiple memory ICs in a stacked configuration, as this was a known method for achieving high-density memory modules.
  • It was well-understood in the prior art (and acknowledged by the '942 patent itself) that memory ICs, particularly DRAMs, are typically fabricated using semiconductor processes optimized for density and cost, which often means larger feature sizes and thus "first MOSFET gate length" compared to the cutting-edge processes used for high-performance logic units [Description]. US6009023A illustrates the concept of employing "multiple thickness gate oxide" within a DRAM structure to optimize performance, demonstrating an awareness of tailoring process parameters for specific functions within semiconductor devices. A PHOSITA would routinely select a more mature process (resulting in a longer MOSFET gate length) for the memory cell array ICs (Claim 1, element 3) to maximize yield and minimize cost for the dense memory arrays, while selecting a more advanced process (resulting in a shorter MOSFET gate length) for the "logic unit" (Claim 1, elements 6, 7) to achieve higher speed and lower power consumption for logic operations. This pragmatic approach directly addresses the "manufacturing difficulty," "poorer heat dissipation," and "higher power consumption" issues by optimizing each component's manufacturing process for its specific role within the module.

• Efficient Data Transmission and Conversion (Elements 4, 5, 8):

  • US7245239B2 explicitly teaches a "synchronous parallel/serial converter". To handle the high bandwidth requirements of accessing a group of memory ICs within the module while maintaining a manageable external interface, a PHOSITA would be motivated to use a wider "first transmission bus" (Claim 1, element 5: "bus width... wider than bus width of an I/O data bus of each... memory cell array ICs") for internal data transfer between the memory group and the logic unit. The logic unit would then incorporate a parallel-to-serial converter (as taught by US7245239B2) to efficiently "convert the first set of parallel data... into a second set of parallel data through a second transmission bus" (Claim 1, element 8) for communication with other system components. This approach balances internal bandwidth with external interface constraints, reducing pin count and simplifying routing, thereby enhancing "higher data transmission efficiency" and contributing to "lower power consumption" by optimizing signal swings and bus widths as described in the '942 patent's summary [Summary of the Invention].

Therefore, a PHOSITA, aiming to integrate memory and logic effectively to overcome known system-level challenges, would have found it obvious to combine a stacked memory device, different semiconductor process technologies for memory and logic, and a parallel-to-serial converter to create a high-speed memory chip module as claimed in Claim 1.

Obviousness of Claim 19: Electronics System Device

Claim 19 Elements:
Claim 19 describes an electronics system device that includes the high-speed memory chip module of Claim 1, with the addition of:

1. An ASIC processor.
2. The logic unit transmits the second set of parallel data to the ASIC processor.
3. The ASIC processor executes a predetermined function corresponding to the second set of parallel data while under operating condition.
4. Bit width of the first set and the second set of parallel data are different.

Combination of Prior Art References for Claim 19:
The combination of references for Claim 1 (US20090039492A1, US7245239B2, US6009023A, and general knowledge of semiconductor processes), further combined with general knowledge of system architecture (e.g., evidenced by KR10086760B1 (Samsung Electronics Co., Ltd.): "System-on-Chip with Image Processing Memory with Multiple Access Paths" or CN100336045C (VIA Technologies, Inc.): "Multifunction chipset and related method"), would render Claim 19 obvious.

Explanation of Obviousness and Motivation:

• Integration with an ASIC Processor (Elements 1, 2, 3):

  • Once the high-speed memory chip module (as rendered obvious for Claim 1) is conceived, its integration into a larger electronic system is a natural next step. Prior art such as KR100867640B1 describes a "System-on-Chip with Image Processing Memory with Multiple Access Paths," demonstrating the conventional practice of coupling memory directly with a processor. Similarly, CN100336045C describes a "Multifunction chipset and related method," which inherently involves processors interacting with memory.
  • A PHOSITA designing an electronic system would routinely connect a memory module to an "ASIC processor" to enable the processor to access and process data ("executes a predetermined function corresponding to the second set of parallel data") [Claim 19]. The logic unit's function of transmitting data to the ASIC processor is a fundamental aspect of any memory subsystem serving a processor.

• Differing Bit Widths (Element 4):

  • The element stating that "bit width of the first set and the second set of parallel data are different" is directly addressed by the parallel-to-serial conversion taught by US7245239B2, which forms part of the obviousness argument for Claim 1. Such conversion inherently changes the bit width of the data stream.

Motivation for Combination:
The motivation for combining these elements is to create a functional electronic system that utilizes the benefits of the high-speed memory chip module. The very purpose of the memory module, as described in the '942 patent, is to provide efficient data access for a processor. The problems identified in the '942 patent's background (heat, power, noise, manufacturing difficulty) are system-level challenges that are addressed by the integrated memory module and its optimized interfaces, thereby motivating a PHOSITA to incorporate such a module into an ASIC-based system for improved performance and efficiency.