US 9164942

Here is a concise summary of US patent 9164942:

US Patent 9164942: Summary

• Title: High speed memory chip module and electronics system device with a high speed memory chip module
• Original Assignee: Etron Technology Inc
• Current Assignee: Wecrevention Inc (as of September 11, 2025)
• Inventors: Weng-Dah Ken, Nicky Lu
• Filing Date: October 11, 2012 (Application No. US13/649,131)
• Issue Date: October 20, 2015
• Abstract: A high speed memory chip module includes a type of memory cell array group and a logic unit. The memory cell array group comprises multiple memory cell array integrated circuits (ICs), each having a data bus and at least one memory cell array, corresponding to a first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length from a first MOSFET process. A logic unit accesses this memory cell array group via a first transmission bus, where the bus width of the first transmission bus is wider than the data bus of each memory cell array IC. The logic unit corresponds to a second MOSFET process with a second MOSFET gate length, which is shorter than the first MOSFET gate length.
• Plain-Language Overview of Independent Claims:
  • Independent Claim 1 (High speed memory chip module): This claim describes a high-speed memory chip module comprising a group of multiple memory chips and a logic unit. Each memory chip has its own input/output (I/O) data bus and is manufactured using a "first" semiconductor process characterized by a specific (longer) MOSFET gate length. The logic unit accesses these memory chips via a "first" internal transmission bus. This "first" bus is wider than the individual I/O data buses of the memory chips. The logic unit itself is manufactured using a "second" semiconductor process characterized by a shorter MOSFET gate length than the "first" process. The logic unit is also configured to convert the parallel data from the wider "first" transmission bus into a "second" set of parallel data for transmission over a "second" transmission bus.
  • Independent Claim 19 (Electronics system device): This claim describes an electronic system that incorporates a high-speed memory chip module. The system includes an Application-Specific Integrated Circuit (ASIC) processor, a group of multiple memory chips (each with an I/O data bus), and a logic unit. The logic unit accesses the memory chips through a "first" transmission bus that is wider than the individual I/O data buses of the memory chips. The logic unit then converts this "first" set of parallel data into a "second" set of parallel data via a "second" transmission bus, and sends this "second" set of data to the ASIC processor. The ASIC processor performs a function based on this "second" set of data while operating. A key feature is that the bit widths of the "first" and "second" sets of parallel data are different.

Litigation Notes (as of April 26, 2026):
The patent record for US9164942B2 indicates that the patent family is involved in litigation.

• A PTAB case, IPR2026-00239, has been filed and is currently pending.
• Multiple US cases have been filed in the Texas Western District Court and Texas Eastern District Court.

As of the current date (April 26, 2026), a search of CAFC 2026 dockets did not explicitly return specific cases directly listing patent US9164942B2, beyond general scheduled case information for May and June 2026. Therefore, while PTAB litigation for 2026 is noted, any subsequent appeals to the CAFC specifically involving this patent do not appear in the readily available scheduled dockets for 2026 at this time. It is possible that the IPR2026-00239 case is still pending at the PTAB and has not yet progressed to an appeal at the CAFC.