US 8370543

US Patent 8,370,543: Busy Detection Logic for Asynchronous Communication Port

Title: Busy detection logic for asynchronous communication port

Assignee: Induction Devices LLC

Inventors: Syed Babar Raza, Pradeep Bajpai

Filing Date: June 6, 2011

Issue Date: February 5, 2013

Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

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Plain-Language Overview of Independent Claims:

• Claim 1 (Circuit): This claim describes a circuit designed to synchronize communication between different time domains. It includes a "first logic" that receives incoming request signals from a first time domain and stores specific ones of these signals based on a "strobe signal." A "synchronizing logic" then takes these stored request signals and synchronizes them to a second, different time domain, producing synchronized request signals. Finally, "load logic" outputs these synchronized request signals according to a predefined priority.

• Claim 9 (Method): This claim outlines a method for communicating device resource access information between independent time domains. The method involves receiving various input signals, then capturing the state of certain selected input signals in response to a timing signal among those inputs. These captured states are then synchronously clocked along separate logic paths. Lastly, the captured states are outputted based on a predetermined priority.

• Claim 16 (System): This claim details a system comprising a "first device" (e.g., a processor) and a "second device" (e.g., a memory device) that has multiple resources accessible by the first device and operates in a first clock domain. The core of the invention lies in a "logic unit" situated between the two devices. This logic unit is configured to latch resource request signals from the first device when a timing signal within those requests is detected. It then synchronizes these latched resource request signals to the first clock domain of the second device.

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CAFC 2026 Dockets:

As of April 26, 2026, the provided patent information from Google Patents indicates no specific cases filed in the Court of Appeals for the Federal Circuit (CAFC) in 2026 for US patent 8,370,543. However, the patent family has ongoing litigation with numerous US cases filed in the Texas Eastern District Court, including cases filed in 2025 and 2026. These district court cases are: 2:25-cv-00787, 2:25-cv-00788, 2:26-cv-00258, 2:26-cv-00249, 2:26-cv-00248, 2:26-cv-00247, 2:26-cv-00246, 2:26-cv-00197, 2:26-cv-00196, 2:26-cv-00195, 2:25-cv-00765, 2:25-cv-00766, 2:25-cv-00767, 2:25-cv-00768, 2:25-cv-00769, 2:25-cv-00775, 2:25-cv-00776, 2:25-cv-00777, 2:26-cv-00194, 2:25-cv-00778, 2:26-cv-00192, 2:25-cv-00789, 2:25-cv-00790, 2:25-cv-00791, 2:25-cv-00975, 2:25-cv-01006, 2:26-cv-00191, and 2:26-cv-00193.