US 7864816

Litigation Summary

As of April 26, 2026, there is no known litigation specifically involving US patent 7864816 in the CAFC dockets. Searches of the CAFC website for "7864816" or "US7864816" did not yield any direct case results. The CAFC site provides information on scheduled cases and case records, but a patent number alone is not typically sufficient for a direct search of active litigation without specific case information like party names or a case number. My previous search of Unified Patents and PACER also did not reveal any litigation, and these platforms often require more specific details for effective searching.

Therefore, based on the available information and search capabilities, no specific litigation involving US patent 7864816 is known at this time.

US Patent 7864816: Concise Summary

Title: Integrated circuit for network delay and jitter testing

Assignee: Marvell Asia Pte Ltd. (Current Assignee)

Inventors: Yuval Cohen

Filing Date: 2005-02-11

Issue Date: 2011-01-04

Abstract: An integrated circuit (IC) and its corresponding method for network delay and jitter testing are disclosed. The IC includes one or more ports to transmit and receive data packets and a forwarding engine to transfer these packets between the ports. At least one port features a packet generator to create a first packet with a timestamp indicating its transmission time, a network transmit interface to send it, and a network receive interface to get a reply packet. A controller then calculates network delay using the original timestamp and the reply packet.

Plain-language overview of independent claims:

• Claim 1 (Integrated Circuit for Network Switch): This claim describes an integrated circuit designed for a network switch. It has multiple ports for sending and receiving data on a network, and a forwarding engine to move data between these ports. Crucially, at least one of these ports contains a specialized setup:

  • A packet generator that creates a "first packet" (a test packet) and includes a timestamp representing when this packet was generated. This first packet is considered "received by the at least one of the ports from the network," which is a somewhat unusual phrasing for a generated packet but is specified in the claim.
  • A network transmit interface to send out this first packet.
  • A network receive interface to get a "second packet" (a reply) back in response to the first packet.
  • A controller that calculates the network delay. This delay specifically includes a queue delay that occurs when the first packet is waiting to be sent. The calculation is based on the generation timestamp from the first packet and the received second packet.

• Claim 16 (Method for Network Switch IC): This claim describes a method performed by an integrated circuit acting as a network switch. The steps include:

  • Transmitting and receiving data packets on a network using the IC's ports.
  • Transferring packets between these ports via a forwarding engine.
  • Using a packet generator (within one of the ports) to create a "first packet" that contains a timestamp of its generation. Again, the first packet is characterized as "received by the one of the ports from the network."
  • Transmitting this first packet.
  • Receiving a "second packet" in reply.
  • Using a controller (within the same port) to calculate a network delay, which includes a queue delay. This calculation relies on the generation timestamp of the first packet and the received second packet.

• Claim 25 (Integrated Circuit for Network Interface Controller): This claim describes an integrated circuit for a network interface controller (NIC). It features one or more ports for network communication and a host interface for exchanging data with a host device. Similar to Claim 1, at least one port includes:

  • A packet generator to originate a "first packet" with a generation timestamp. This packet is also described as "received by the at least one of the ports from the network."
  • A network transmit interface to send the first packet.
  • A network receive interface to get a reply "second packet."
  • A controller to calculate a network delay that includes a queue delay, using the generation timestamp of the first packet and the second packet.

• Claim 40 (Method for Network Interface Controller IC): This claim describes a method performed by an integrated circuit functioning as a network interface controller. The steps involve:

  • Transmitting and receiving packets on a network through the IC's ports.
  • Using a packet generator (within one of the ports) to create a "first packet" with a generation timestamp. This packet is again described as "received by the one of the ports from the network."
  • Transmitting the first packet.
  • Receiving a "second packet" in reply.
  • Using a controller (within the same port) to calculate a network delay, which includes a queue delay. This calculation is based on the generation timestamp of the first packet and the received second packet.

• Claim 49 (Integrated Circuit - Refinement of Claim 1): This claim adds a specific detail to the integrated circuit described in Claim 1. The controller further includes in the first packet third data representing a time of transmission when the first packet is actually sent. The network delay is then calculated based on this transmission timestamp and the time the second packet is received. This refines the delay calculation by using the actual transmission time rather than the generation time if there is a queue delay between generation and transmission.

• Claim 50 (Integrated Circuit - Refinement of Claim 25): This claim refines the integrated circuit described in Claim 25 (for a NIC) in the same way Claim 49 refines Claim 1. The controller includes third data representing a time of transmission in the first packet and calculates the network delay based on this transmission timestamp and the time the second packet is received.

• Claim 51 (Method - Refinement of Claim 16): This claim refines the method described in Claim 16 (for a network switch IC). It explicitly includes the step of inserting third data representing a time of transmission into the first packet when it is sent. The network delay calculation is then based on this transmission timestamp and the time the second packet is received.

• Claim 52 (Method - Refinement of Claim 40): This claim refines the method described in Claim 40 (for a NIC IC). It includes the step of inserting third data representing a time of transmission into the first packet when it is sent. The network delay calculation is then based on this transmission timestamp and the time the second packet is received.

A consistent point of potential uncertainty across the independent claims is the phrase "a first packet of the first data received by the at least one of the ports from the network, wherein the first packet comprises second data representing a time of generation of the first packet of the first data". This wording could be interpreted as the packet being both generated by the port and received by the port from the network, which seems contradictory. However, given the context of a packet generator originating the packet and then transmitting it, this phrasing likely refers to the conceptual point in the process where the packet, having been generated, is now ready for transmission into the network, and the 'time of generation' is the relevant timestamp for the measurement. Claims 49-52 clarify this by introducing a "time of transmission" directly into the packet, suggesting a distinction between generation time and actual transmission time after queuing.