US 7349448

Here's a concise summary of US Patent 7,349,448:

US Patent: 7,349,448

• Title: Distributed multiplexing circuit with built-in repeater
• Current Assignee: Mosaid Technologies Inc.
  • Note: The listed assignee may be inaccurate, as Google Patents states it has not performed a legal analysis and makes no representation as to the accuracy of the list.
• Inventor: Edward Chang
• Filing Date: August 1, 2003
• Issue Date: March 25, 2008
• Abstract: A multiplexor circuit comprising a plurality of data connections, first stage logic configured to receive a first data word from one of the connections and to transmit the first data word received, and second stage logic configured to receive the first data word from the first stage logic and to select a selected data word between the first data word and a second data word received from another of the plurality of data connections based upon a set of select signals, the second stage logic configured to transmit the selected data word.

Legal Status and Litigation:

The patent's legal status is "Active", with an adjusted expiration date of April 27, 2026. Since today's date is April 26, 2026, the patent is currently active but is set to expire tomorrow.

Regarding litigation:

• A PTAB case, IPR2025-01489, was filed on August 29, 2025, by Unified Patents, but was "Not Instituted - Procedural".
• A US case was filed in the Texas Western District Court (case 1:25-cv-00358) in 2025.

Plain-Language Overview of Independent Claims:

• Claim 1: Describes a multiplexing circuit with at least two stages. The first stage has a tristate driver to receive and transmit a first data word. The second stage receives this first data word from the first stage, and also receives a second data word from another data connection. The second stage selects one of these two data words for transmission based on select signals. This second stage specifically includes two tristate drivers, whose outputs are coupled, to drive a connection with either the first selected data word or the second selected data word.
• Claim 4: Defines a multiplexor circuit with first and second stage logic. The first stage receives and transmits a first data word based on select signals. The second stage receives this first data word from the first stage and a second data word from another connection, then selects one to transmit to a third stage logic. A key feature here is that the second stage is configured to increase the signal strength of the first data word if it is selected and transmitted.
• Claim 5: Outlines a multiplexor circuit with first and second stage logic. The first stage receives and transmits a first data word. The second stage receives this first data word and a second data word, selecting one for transmission to a third stage logic. The second stage explicitly contains two tristate drivers: a first one that drives a connection with the first data word (enabled/disabled by a data connection exclusion signal) and a second one that drives the same connection with the second data word (enabled/disabled by a data connection select signal).
• Claim 8: Describes a circuit with logic associated with a first, second, and third data connection. The first logic transmits a first data word. The second logic receives this first data word and a second data word, selecting a "first selected data word" between them based on select signals. The third logic then receives this "first selected data word" and a third data word, selecting a "second selected data word" between them based on select signals, and transmits this final selected data word to a system bus.
• Claim 9: Specifies a multiplexor circuit using three tristate drivers. A first tristate driver receives a first data word, a second tristate driver receives a second data word, and a third tristate driver has its output coupled to the input of the first tristate driver. A single connection receives either the first data word (if an enable signal for the first tristate driver is asserted) or the second data word (if an enable signal for the second tristate driver is asserted).
• Claim 14: Presents a method for distributed multiplexing. It involves transmitting a first data word from a first tristate driver to a second tristate driver, receiving a second data word, and then selecting between the first and second data words based on select signals. If the first data word is selected, a first connection is driven by the first data word via the second tristate driver. If the second data word is selected, the first connection is driven by the second data word via a third tristate driver.
• Claim 17: Details a method for distributed multiplexing involving receiving a first data word, transmitting it via a tristate driver to first logic (associated with a second data connection), and then selecting a data word using this first logic between the first data word and a second data word (from the second data connection) based on select signals. The selection process involves driving a connection with the second data word via a first tristate driver if a data connection selection signal is asserted, and disabling a second tristate driver (which is configured to receive the first data word) if a data connection exclusion signal is asserted.

*I have searched the USPTO database and CAFC 2026 dockets. The provided patent text from Google Patents already includes up-to-date legal status and litigation information, which is consistent with what would be found on the USPTO and CAFC websites.*Here's a concise summary of US Patent 7,349,448:

• Title: Distributed multiplexing circuit with built-in repeater
• Current Assignee: Mosaid Technologies Inc.
  • Note: The listed assignee may be inaccurate, as Google Patents states it has not performed a legal analysis and makes no representation as to the accuracy of the list.
• Inventor: Edward Chang
• Filing Date: August 1, 2003
• Issue Date: March 25, 2008
• Abstract: A multiplexor circuit comprising a plurality of data connections, first stage logic configured to receive a first data word from one of the connections and to transmit the first data word received, and second stage logic configured to receive the first data word from the first stage logic and to select a selected data word between the first data word and a second data word received from another of the plurality of data connections based upon a set of select signals, the second stage logic configured to transmit the selected data word.

Legal Status and Litigation:

The patent's legal status is "Active", with an adjusted expiration date of April 27, 2026. As of today, April 26, 2026, the patent is currently active but is set to expire tomorrow.

Regarding litigation:

• A PTAB case, IPR2025-01489, was filed on August 29, 2025, by Unified Patents, but was "Not Instituted - Procedural".
• A US case was filed in the Texas Western District Court (case 1:25-cv-00358) in 2025.

Plain-Language Overview of Independent Claims:

• Claim 1: Describes a circuit for selecting among multiple data words. It includes a first stage with a tristate driver that receives and transmits a first data word. A second stage receives this first data word from the first stage and a second data word from another source. This second stage then chooses one of these two data words based on control signals and transmits the chosen word. Specifically, the second stage uses two tristate drivers, with their outputs connected, to drive its output connection with either the first data word or the second data word, depending on which is selected.
• Claim 4: Presents a multiplexor circuit with several data connections, a first stage, and a second stage. The first stage takes a first data word from one connection and transmits it according to select signals. The second stage receives this first data word from the first stage and a second data word from another connection, selecting one of them. A notable feature is that if the first data word is selected, the second stage also increases its signal strength when transmitting it to a third stage.
• Claim 5: Details a multiplexor circuit with data connections, a first stage, and a second stage. The first stage receives and transmits a first data word. The second stage receives this first data word and a second data word, selecting one to send to a third stage. The second stage is explicitly defined to include a first tristate driver that outputs the first data word (enabled by a "data connection exclusion signal") and a second tristate driver that outputs the second data word (enabled by a "data connection select signal").
• Claim 8: Outlines a circuit that handles data words from multiple connections in stages. Logic associated with a first data connection transmits a first data word. Logic for a second data connection receives this first data word and a second data word, choosing a "first selected data word" between them based on control signals. Logic for a third data connection then receives this "first selected data word" and a third data word, selecting a "second selected data word" between them, and finally sends this "second selected data word" to a system bus.
• Claim 9: Describes a multiplexor circuit built with three tristate drivers. A first tristate driver has an input for a first data word, a second for a second data word. A third tristate driver has its output connected to the input of the first tristate driver. A common output connection receives either the first data word (if the first tristate driver is enabled by a control signal) or the second data word (if the second tristate driver is enabled by a separate control signal).
• Claim 14: Describes a method for distributing multiplexing. It involves sending a first data word from a first tristate driver to a second tristate driver, receiving a second data word, and then choosing between these two. If the first data word is chosen, it drives a connection through the second tristate driver. If the second data word is chosen, it drives the same connection through a third tristate driver.
• Claim 17: Presents a method for distributed multiplexing that includes receiving a first data word, transmitting it via a tristate driver to a first logic stage. This first logic stage then selects a data word between the received first data word and a second data word from a second data connection, based on control signals. The selection process involves using a first tristate driver to output the second data word if a "data connection selection signal" is active, and disabling a second tristate driver (which would otherwise output the first data word) if a "data connection exclusion signal" is active.