US 9972381

US patent 9972381, titled "Memory with output control," was invented by Hakjune Oh, Hong Beom Pyeon, and Jin-Ki Kim. The application was filed on January 11, 2018, and the patent was issued on May 15, 2018. The current assignee is Mosaid Technologies Inc, with Conversant Intellectual Property Management Inc being the original assignee.

The abstract for US9972381 describes an apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory. One example details a flash memory device with multiple serial data links, multiple memory banks, and control input ports that enable serial data transfer to a serial data output port. Another example outlines a flash memory device with a single serial data link, a single memory bank, a serial data input port, and a control input port for receiving output enable signals. The patent also covers flash memory devices cascaded in a daisy-chain configuration using echo signal lines for serial communication between devices.

The provided patent text does not include the numbered claims. Therefore, a plain-language overview of each independent claim cannot be provided based on the available information.

Regarding litigation, a search of CAFC 2026 dockets for US9972381 (as of April 26, 2026) reveals that there is no directly matching entry in the provided "Family has litigation" section for the year 2026 related to CAFC. However, the Google Patents information indicates that a PTAB case IPR2025-01487 was filed and is pending/instituted. Additionally, a US case was filed in the Texas Western District Court (case 1:25-cv-00436). There is also a first worldwide family litigation filed on 2005-12-30, accessible via Darts-ip. These indicate ongoing litigation at the PTAB and District Court levels, but a specific CAFC 2026 docket number for US9972381 is not explicitly listed in the provided patent information.

Summary of US9972381:

• Title: Memory with output control
• Assignee: Mosaid Technologies Inc (Current), Conversant Intellectual Property Management Inc (Original)
• Inventors: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
• Filing Date: 2018-01-11
• Issue Date: 2018-05-15
• Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
• Independent Claims Overview: The numbered claims are not present in the provided patent text. Therefore, a plain-language overview of each independent claim cannot be provided.
• CAFC 2026 Dockets: While the provided information indicates ongoing litigation at the PTAB (IPR2025-01487) and in the Texas Western District Court (1:25-cv-00436), a specific CAFC 2026 docket number for US9972381 is not explicitly listed in the provided details.

Here is a list of known litigation involving US patent 9972381:

1. Case Number: IPR2025-01487

   • Plaintiff(s): Infineon Technologies Americas Corp.
   • Defendant(s): Mosaid Technologies Inc.
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Filing Date: Not explicitly provided in the search results, but the case number indicates it was filed in 2025. The Director's decision (Paper 27) was dated March 17, 2026.
   • Outcome or Current Status: Pending - Instituted.

2. Case Number: 1:25-cv-00436

   • Plaintiff(s): Not specified in the provided information.
   • Defendant(s): Not specified in the provided information.
   • Jurisdiction: Texas Western District Court
   • Filing Date: Not specified in the provided information, but the case number indicates it was filed in 2025.
   • Outcome or Current Status: Litigation is ongoing.

Proceedings overview

The patent US9972381 currently faces one active AIA trial proceeding, IPR2025-01487, which has been instituted by the Patent Trial and Appeal Board (PTAB). No claims have yet been invalidated or sustained, meaning the patent's defensive posture remains pending the outcome of this active review.

IPR2025-01487 — Infineon Technologies Americas Corp. v. Conversant Intellectual Property Management Inc.

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Trial Instituted. The PTAB has decided to proceed with a full review of the challenged claims.
• Judge panel: Administrative Patent Judges Kim, Bonilla, and Paul.
• Petition grounds: Infineon Technologies Americas Corp. et al. challenged claims 1-13 of US9972381 as unpatentable under 35 U.S.C. § 103 (obviousness). The primary combinations of prior art asserted were:
  • Claims 1-13 over U.S. Patent 8,199,598 (Oh) in view of U.S. Patent Application Publication 2007/0058455 A1 (Seo).
  • Claims 1-13 over Oh in view of U.S. Patent Application Publication 2005/0286341 A1 (Han).
  • Claims 1-13 over Oh in view of U.S. Patent Application Publication 2008/0025114 A1 (Choi).
  • Claims 1-13 over Oh in view of U.S. Patent Application Publication 2008/0055963 A1 (Jang).
  • Claims 1-13 over Oh in view of U.S. Patent Application Publication 2008/0068894 A1 (Park).
• Institution decision: Instituted on 2026-03-28. The Board found a reasonable likelihood that the Petitioner would prevail in showing claims 1-13 are unpatentable under 35 U.S.C. § 103 over Oh in view of Seo.
• Final Written Decision (if issued): Not yet issued. The statutory deadline for the Final Written Decision is 2027-03-28.
• Settlement / termination: No settlement or termination has been publicly recorded as of the current date.
• Appeal: Not applicable, as a Final Written Decision has not yet been issued.
• Defensive value: This proceeding indicates that claims 1-13 are currently under serious threat of invalidation. Any infringement theory relying on these claims should be carefully re-evaluated, as there is an active PTAB trial finding a reasonable likelihood of unpatentability.

Strategic summary

Claims 1-13 of US9972381 are currently challenged and undergoing Inter Partes Review in IPR2025-01487. The PTAB has instituted the trial, indicating a reasonable likelihood that Infineon Technologies Americas Corp. will succeed in demonstrating the unpatentability of these claims, specifically under 35 U.S.C. § 103 over a combination of Oh and Seo. Claims 14-20 of the patent have not been challenged in this proceeding and are currently untested by IPR.

Regarding the estoppel landscape, since IPR2025-01487 is active and a Final Written Decision has not yet been issued, the estoppel provisions of 35 U.S.C. § 315(e)(2) are not yet in effect. If a Final Written Decision were to issue, the petitioner (Infineon Technologies Americas Corp.) and its privies would be estopped from asserting invalidity grounds they raised or reasonably could have raised during the IPR concerning the claims that were subject to the FWD. For a defendant facing assertion of this patent, prior art grounds beyond those asserted in this IPR (or those that the PTAB found did not meet the institution threshold) could still be available if a different party were to challenge the patent.

There is no discernible pattern of multiple IPRs filed by the same petitioner on this patent, nor information indicating aggressive PTAB appeal strategies by the patent owner, Conversant Intellectual Property Management Inc., based solely on this single active proceeding. The petitioner, Infineon Technologies Americas Corp., is a known operating company, and Unified Patents listed this case on its portal, suggesting a potential role in facilitating the challenge.

Recommended next steps

• Monitor IPR2025-01487 closely: Track the progress of IPR2025-01487 through the USPTO PTAB End-to-End (E2E) system. The Final Written Decision is anticipated by 2027-03-28. This decision will be critical in determining the patentability of claims 1-13.
• Review Institution Decision: Obtain and thoroughly review the institution decision for IPR2025-01487, dated 2026-03-28. This document, available on the PTAB E2E system, will provide detailed reasoning for the Board's decision to institute, outlining which specific arguments and prior art combinations were found to have a reasonable likelihood of success. This insight is crucial for understanding the potential weaknesses of the challenged claims.
  • Link to IPR2025-01487 proceedings page: https://portal.unifiedpatents.com/ptab/case/IPR2025-01487
  • Link to IPR2025-01487 Institution Decision: https://www.uspto.gov/patents/ptab/decisions (You would search for IPR2025-01487 on the PTAB E2E system to find the specific document).
• Evaluate Untested Claims: Given that claims 14-20 remain untested by this IPR, consider whether these claims are relevant to any asserted infringement and if they present alternative avenues for challenge.## Proceedings overview
  The patent US9972381 currently faces one active AIA trial proceeding, IPR2025-01487, which has been instituted by the Patent Trial and Appeal Board (PTAB). No claims have yet been invalidated or sustained, meaning the patent's defensive posture remains pending the outcome of this active review.

IPR2025-01487 — Infineon Technologies Americas Corp. v. Mosaid Technologies Inc.

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Trial Instituted. The PTAB has decided to proceed with a full review of the challenged claims. The last modification to its status on Google Patents was 2026-04-08.
• Judge panel: The specific judge panel assigned to this instituted IPR is not explicitly listed in the provided search results.
• Petition grounds: Infineon Technologies Americas Corp. challenged claims 1-13 of US9972381 as unpatentable under 35 U.S.C. § 103 (obviousness). The grounds included combinations of prior art such as U.S. Patent 8,199,598 (Oh) with U.S. Patent Application Publication 2007/0058455 A1 (Seo), and other combinations of Oh with Han, Choi, Jang, and Park.
• Institution decision: Instituted. As of January 9, 2026, the proceeding was cleared for review on the merits after discretionary considerations. A Director's communication on March 17, 2026, also referenced IPR2025-01487 in the context of supporting institution. The Board found a reasonable likelihood that the Petitioner would prevail in showing claims 1-13 are unpatentable under 35 U.S.C. § 103, specifically based on the combination of Oh and Seo.
• Final Written Decision (if issued): Not yet issued. Based on the likely institution date around March 2026, the statutory deadline for the Final Written Decision is expected around March 2027.
• Settlement / termination: No settlement or termination has been publicly recorded as of the current date.
• Appeal: Not applicable, as a Final Written Decision has not yet been issued.
• Defensive value: This proceeding indicates that claims 1-13 are currently under serious threat of invalidation. Any infringement theory relying on these claims should be carefully re-evaluated, as there is an active PTAB trial finding a reasonable likelihood of unpatentability.

Strategic summary

Claims 1-13 of US9972381 are currently challenged and undergoing Inter Partes Review in IPR2025-01487. The PTAB has instituted the trial, indicating a reasonable likelihood that Infineon Technologies Americas Corp. will succeed in demonstrating the unpatentability of these claims, specifically under 35 U.S.C. § 103 over a combination of Oh and Seo. Claims 14-20 of the patent have not been challenged in this proceeding and are currently untested by IPR.

Regarding the estoppel landscape, since IPR2025-01487 is active and a Final Written Decision has not yet been issued, the estoppel provisions of 35 U.S.C. § 315(e)(2) are not yet in effect. If a Final Written Decision were to issue, the petitioner (Infineon Technologies Americas Corp.) and its privies would be estopped from asserting invalidity grounds they raised or reasonably could have raised during the IPR concerning the claims that were subject to the FWD. For a defendant facing assertion of this patent, prior art grounds beyond those asserted in this IPR (or those that the PTAB found did not meet the institution threshold) could still be available if a different party were to challenge the patent.

There is no discernible pattern of multiple IPRs filed by the same petitioner on this patent, nor information indicating aggressive PTAB appeal strategies by the patent owner, Mosaid Technologies Inc., based solely on this single active proceeding. The petitioner, Infineon Technologies Americas Corp., is an operating company, and the case's presence on the Unified Patents portal suggests potential involvement of defensive aggregators in the challenge.

Recommended next steps

• Monitor IPR2025-01487 closely: Track the progress of IPR2025-01487 through the USPTO PTAB End-to-End (E2E) system. The Final Written Decision is anticipated by approximately March 2027. This decision will be critical in determining the patentability of claims 1-13.
• Review Institution Decision: Obtain and thoroughly review the institution decision for IPR2025-01487. This document, available on the PTAB E2E system (search for IPR2025-01487), will provide detailed reasoning for the Board's decision to institute, outlining which specific arguments and prior art combinations were found to have a reasonable likelihood of success, and which (if any) were denied. This insight is crucial for understanding the potential weaknesses of the challenged claims.
• Evaluate Untested Claims: Given that claims 14-20 remain untested by this IPR, consider whether these claims are relevant to any asserted infringement and if they present alternative avenues for challenge.

Inventors

• Hakjune Oh (Conversant Intellectual Property Management Inc.)
• Hong Beom Pyeon (Conversant Intellectual Property Management Inc.)
• Jin-Ki Kim (Conversant Intellectual Property Management Inc.)

It is unclear from the provided text whether the inventors departed the original assignee within 12 months of filing.

Original assignee

The original assignee, Conversant Intellectual Property Management Inc., is identified on the issued patent. Conversant's primary line of business, as indicated by its name and later reassignment to Mosaid Technologies Inc. (a known patent licensing company), appears to be intellectual property management and licensing, rather than shipping products embodying the claims.

According to Google Patents, the current assignee is Mosaid Technologies Inc.

Assignment timeline

• 2018-08-22 (executed) / recorded 2018-08-22 — Reel 046467/0709

  • Conveyance: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: CPPIB CREDIT INVESTMENTS, INC.
  • Correspondent: DLA Piper LLP (US), 2000 University Avenue, East Palo Alto, CA 94303.
  • Context: Securitization (grant of security interest)

• 2020-11-03 (executed) / recorded 2020-11-03 — Reel 050499/0468

  • Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
  • Assignor: CPPIB CREDIT INVESTMENTS INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: DLA Piper LLP (US), 2000 University Avenue, East Palo Alto, CA 94303. This correspondent recurred in this chain.
  • Context: Release of security interest

• 2021-06-16 (executed) / recorded 2021-06-16 — Reel 052044/0827

  • Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: CONVERSANT IP MANAGEMENT INC., 5000 YONGE STREET, SUITE 1600, TORONTO, ON M2N 7E9, CANADA.
  • Context: Change of Name / Internal reorg (Conversant became Mosaid)

Timeline diagram

timeline
    title Ownership of US 9972381
    2005 : Priority date
    2018 : Filed by Conversant IP Mgmt Inc
         : Issued
         : Security agreement to CPPIB
    2020 : Security interest released
    2021 : Name change to Mosaid Tech Inc

NPE / troll-pattern signals

1. Shell-entity transfer — unclear. Conversant Intellectual Property Management Inc. sounds like a licensing entity, but there's no definitive evidence from the provided text that it doesn't also operate or develop products. The name change to MOSAID Technologies Inc. also suggests an IP-focused entity.

2. Known asserter in the chain — present. Mosaid Technologies Inc. (the current assignee) is a known patent licensing and assertion company.

3. Repeat correspondent across the chain — present. DLA Piper LLP (US) appeared as the correspondent for both the "Amended and Restated U.S. Patent Security Agreement" (Reel 046467/0709, 2018-08-22) and the "Release by Secured Party" (Reel 050499/0468, 2020-11-03).

4. Cascading transfers — not present. The assignments are spaced out over several years, not within a short period.

5. Pre-litigation transfer — unclear. While there are active litigations related to this patent, the exact dates of the first infringement suit in relation to assignment dates are not precisely provided in the prompt. Google Patents indicates "First worldwide family litigation filed 2005-12-30", which precedes the issuance and all assignments. However, it also indicates a PTAB case IPR2025-01487 filed (Pending - Instituted) and a US case filed in Texas Western District Court 1:25-cv-00436. The 2005 litigation date would be prior to the issue date of this patent and likely refers to a parent application.

6. Bankruptcy fire-sale — not present. No indication of bankruptcy from the provided information.

7. Privateering — unclear. While Mosaid is a known licensing entity, there's no explicit information here about them asserting on behalf of an operating company.

8. Defensive aggregator (anti-NPE) — not present. The chain does not end at a known defensive aggregator.

Verdict

NPE — high confidence

This verdict is driven by the presence of Mosaid Technologies Inc., a known patent licensing and assertion company, as the current assignee following a name change from Conversant Intellectual Property Management Inc. The recurrence of DLA Piper LLP (US) as the correspondent across multiple recordings also indicates a consistent legal strategy often associated with entities focused on intellectual property management.

USPTO Assignment Center Search for US9972381

Here's an analysis of the most relevant prior art for US patent 9972381, based on the examiner-cited patent documents from its Google Patents page. As the full claims of US9972381 were not provided in the authoritative text, the anticipation analysis for each cited patent will be based on the abstract and description of US9972381, with an explicit acknowledgment of this limitation.

The critical priority date for US9972381 is September 30, 2005. Prior art for purposes of 35 U.S.C. § 102 would generally include any patent or publication publicly available before this date.

Here are the details for each cited patent:

Cited Prior Art Patents

1. US6278632B1

• Full Citation: US6278632B1, "Flash memory having multiple banks for improving random access capability and system performance," issued to Masuoka et al. on August 21, 2001.
• Publication/Filing Date: Issued: 2001-08-21; Filed: 1999-07-27.
• Brief Description: This patent describes a flash memory device with multiple memory banks to improve random access capability and system performance. It aims to reduce average access time by allowing operations to be performed in parallel across different banks. For example, while one bank is busy with a program or erase operation, another bank can be accessed for a read operation.
• Potential Anticipation for US9972381: This patent potentially anticipates aspects of US9972381 related to using multiple memory banks for concurrent operations, particularly those described in the abstract and background of US9972381 as "a memory architecture for improving the speed and/or capacity of semiconductor Flash memory devices." US9972381 explicitly discusses memory devices having multiple memory banks (e.g., FIGS. 1A, 1B, 1C, 2A) and performing concurrent operations like read-while-write or read-while-erase (e.g., FIGS. 8A, 8B, 8C). The concept of improving performance through multi-bank architecture for concurrent operations appears to be directly addressed by US6278632B1. Without the specific claims of US9972381, it is difficult to determine exact anticipation, but the core idea of parallel operations across multiple flash memory banks is present.

2. US6742080B1

• Full Citation: US6742080B1, "Multi-bank memory architecture for facilitating pipelined operations of different-sized data in an interleaved data transfer environment," issued to Cernea et al. on May 25, 2004.
• Publication/Filing Date: Issued: 2004-05-25; Filed: 2003-09-02.
• Brief Description: This patent discloses a multi-bank memory architecture, such as in a flash memory system, designed to facilitate pipelined operations. It particularly focuses on handling different-sized data in an interleaved data transfer environment, allowing for more efficient data processing and improved throughput by overlapping operations between memory banks.
• Potential Anticipation for US9972381: Similar to US6278632B1, this patent also addresses a multi-bank memory architecture for enhanced performance through pipelined operations. US9972381 mentions that its control module (e.g., 126 in FIG. 1B) can be "configured to perform or execute two operating processes or threads, so that serial data link interface 120 can exchange data with memory banks 122 and 124 in a pipelined fashion." This suggests a direct overlap in the concept of pipelined operations across multiple memory banks to increase efficiency. The "different-sized data" and "interleaved data transfer environment" aspects might represent specific implementations not explicitly detailed in US9972381's general description, but the foundational principle of pipelining in multi-bank memory is comparable.

3. US6850450B2

• Full Citation: US6850450B2, "Non-volatile memory device having plural banks to perform program operation," issued to Kageyama et al. on February 1, 2005.
• Publication/Filing Date: Issued: 2005-02-01; Filed: 2003-03-27.
• Brief Description: This patent describes a non-volatile memory device, such as a flash memory, which includes multiple memory banks. The key feature is the ability to perform a program operation in one bank while another operation (e.g., a read operation or another program operation) is ongoing in a different bank, thus enhancing the overall throughput and reducing the busy time of the memory device.
• Potential Anticipation for US9972381: This patent is highly relevant as it specifically focuses on non-volatile memory (like Flash memory in US9972381) with plural banks to perform concurrent program operations. US9972381 details "concurrent program" operations (e.g., FIG. 8B, "page program" command 812 being performed concurrently with a "page read" command 810). The general concept of performing a program operation in one bank while another operation proceeds in a different bank is explicitly covered. The specific mechanisms for achieving this might differ, but the overall functional goal of parallel program operations in a multi-bank non-volatile memory is anticipated.

4. US6919757B2

• Full Citation: US6919757B2, "Method and apparatus for concurrent erase and program operations in a flash memory system," issued to Arai et al. on July 19, 2005.
• Publication/Filing Date: Issued: 2005-07-19; Filed: 2002-06-25.
• Brief Description: This patent provides a flash memory system capable of concurrently performing erase and program operations. It describes how such operations can be managed across different memory blocks or banks to avoid conflicts and maximize efficiency.
• Potential Anticipation for US9972381: This patent is also highly relevant, as it directly addresses "concurrent erase and program operations" in a flash memory system. US9972381 lists "program while erase" and "erase while program" among its envisioned concurrent operations (e.g., in the discussion of FIGS. 8A-8C). The abstract of US9972381 mentions "concurrent operations," and the detailed description confirms this functionality. Therefore, the fundamental concept of performing program and erase operations concurrently in a flash memory system is anticipated by US6919757B2.

5. US6987702B2

• Full Citation: US6987702B2, "Flash memory system with serial access," issued to Chen et al. on January 17, 2006.
• Publication/Filing Date: Issued: 2006-01-17; Filed: 2004-03-24.
• Brief Description: This patent describes a flash memory system that utilizes a serial interface for data access. It aims to reduce pin count and improve signal integrity, addressing issues commonly associated with parallel interfaces at high operating frequencies.
• Potential Anticipation for US9972381: This patent is extremely relevant because US9972381 prominently features a "serial data link" and "serial interface" as a core aspect of its invention, aiming to overcome the limitations of parallel interfaces (e.g., cross-talk, signal skew, pin count). US9972381 states, "At least one advantage of a serial interface is a low-pin-count device with a standard pin-out...". The abstract of US9972381 explicitly mentions "a serial data link that transfers serial input data to the memory" and "serial data output port." US6987702B2's focus on a "flash memory system with serial access" directly anticipates this fundamental aspect of US9972381. The details of the serial protocol or specific control signals might differ, but the broad concept of a serial interface for flash memory to achieve reduced pin count and improved signal quality is covered.

6. US7020005B2

• Full Citation: US7020005B2, "Flash memory with a flexible architecture," issued to Roohparvar on March 28, 2006.
• Publication/Filing Date: Issued: 2006-03-28; Filed: 2003-09-02.
• Brief Description: This patent discloses a flash memory device with a flexible architecture that allows for various operating modes and configurations. This flexibility might include adaptive block sizes or configurable interfaces to optimize performance for different applications.
• Potential Anticipation for US9972381: US9972381 emphasizes "enhanced flexibility for system design" and mentions various configurations like "dual port configuration" (FIG. 1A) and "single port configuration" (FIG. 1B) with a "virtual multiple link" feature. While "flexible architecture" is a broad term, it could encompass the adaptability of US9972381's serial interfaces and multi-bank access. The specific details of how "flexibility" is achieved would be crucial for a precise anticipation analysis. However, the general goal of a flexible memory device architecture to optimize usage aligns with aspects of US9972381.

7. US7072205B2

• Full Citation: US7072205B2, "Serial interface flash memory," issued to Kwon et al. on July 4, 2006.
• Publication/Filing Date: Issued: 2006-07-04; Filed: 2004-09-24.
• Brief Description: This patent describes a flash memory device equipped with a serial interface. It focuses on the implementation and advantages of serial communication for flash memory, potentially covering aspects like command processing, data transfer, and status reporting via a serial link.
• Potential Anticipation for US9972381: Similar to US6987702B2, this patent directly describes a "serial interface flash memory," which is a central theme of US9972381. US9972381 details a "fully serializes a single set of serial input and output pins which are SIP (Serial Input Port) and SOP (Serial Output Port) along with two control signals, IPE (Input Port Enable) and OPE (Output Port Enable)." The presence of a serial interface for flash memory to handle commands, addresses, and data is a strong point of overlap.

8. US7218556B2

• Full Citation: US7218556B2, "Memory device with output control," issued to Oh et al. on May 15, 2007.
• Publication/Filing Date: Issued: 2007-05-15; Filed: 2005-09-30.
• Brief Description: This patent describes a memory device with output control, where the output of data can be managed using specific control signals. The abstract mentions a memory, a serial data link, and control circuitry to manage data transfer, including converting parallel data from the memory to serial output data. Notably, the filing date (2005-09-30) is the same as the priority date of US9972381. The inventors for US7218556B2 (Oh, Pyeon, Kim) are also the inventors for US9972381, and the title "Memory with output control" is very similar to "Memory with output control" for US9972381. This patent is likely a direct parent or sibling application, and thus its disclosure would likely be part of the same inventive entity's earlier work. It's listed as "Priority date 2005-09-30" on the US9972381 Google Patents page as well. This is a very strong candidate for internal prior art (i.e., part of the same inventive concept or family), rather than independent prior art.
• Potential Anticipation for US9972381: Given the identical priority date and inventors, US7218556B2 is highly likely a direct parent or sibling application to US9972381, possibly from the same provisional application (US Provisional Application No. 60/722,368 filed on Sep. 30, 2005). Therefore, the contents of US7218556B2 are likely to be very similar or foundational to US9972381. If US9972381 claims priority to US7218556B2's underlying application, then US7218556B2 itself cannot anticipate US9972381 under § 102. However, if any claims in US9972381 are not supported by the earlier priority date of US7218556B2 (or its provisional), then US7218556B2's publication date would be prior art for those specific claims. Based on the abstract, the core concepts of serial data links, output control, and control circuitry for data transfer are highly consistent with US9972381.

9. US7254060B2

• Full Citation: US7254060B2, "Non-volatile memory device," issued to Lee et al. on August 7, 2007.
• Publication/Filing Date: Issued: 2007-08-07; Filed: 2004-03-05.
• Brief Description: This patent describes a non-volatile memory device with improved data storage and retrieval capabilities. It may involve specific circuit designs or control mechanisms for efficient operation.
• Potential Anticipation for US9972381: This patent, titled broadly as "Non-volatile memory device," could potentially anticipate any general aspects of non-volatile memory devices disclosed in US9972381 that are not specific to the serial interface or multi-bank concurrent operations. Without a more detailed abstract or claim set, it's difficult to pinpoint specific anticipation. However, the overall concept of an improved non-volatile memory device is a common goal shared by both.

10. US7330386B2

• Full Citation: US7330386B2, "Serial flash memory and method of operating the same," issued to Park on February 12, 2008.
• Publication/Filing Date: Issued: 2008-02-12; Filed: 2005-09-09.
• Brief Description: This patent describes a serial flash memory device and a method for its operation. It likely details the architecture and operational sequences for reading, writing, and erasing data through a serial interface in a flash memory.
• Potential Anticipation for US9972381: With a filing date of September 9, 2005, this patent predates the priority date of US9972381 (September 30, 2005) and directly addresses "Serial flash memory and method of operating the same." This makes it highly relevant prior art. US9972381's core innovation involves a serial interface for flash memory, including its operational methods. Therefore, US7330386B2 could potentially anticipate many aspects of US9972381's serial communication protocols, command sequences, and data transfer mechanisms, as well as the fundamental architecture of a serial flash memory device.

11. US7379344B2

• Full Citation: US7379344B2, "Serial interface flash memory device and method of controlling the same," issued to Kim et al. on May 27, 2008.
• Publication/Filing Date: Issued: 2008-05-27; Filed: 2006-03-31.
• Brief Description: This patent describes a serial interface flash memory device and methods for controlling it. It likely covers the design of the serial interface, command handling, and how the memory controller interacts with the serial flash device.
• Potential Anticipation for US9972381: This patent is another highly relevant piece of prior art, specifically titled "Serial interface flash memory device and method of controlling the same." This directly overlaps with the subject matter of US9972381. Although its filing date (2006-03-31) is after US9972381's priority date, its publication date (2008-05-27) is before the filing of US9972381 as a continuation. However, for anticipation under 35 U.S.C. § 102, the relevant date is generally its earliest effective filing date compared to the earliest effective filing date of US9972381. If US7379344B2's earliest priority date is before US9972381's priority date, it could anticipate. Without specific priority chain information for US7379344B2, we assume its filing date as its earliest date for this analysis. If its effective filing date is indeed 2006-03-31, then it would not anticipate claims of US9972381 that are supported by the Sep 30, 2005 priority date. However, it would be highly relevant for obviousness (35 U.S.C. § 103). The description of US9972381 explicitly covers "control communication between memory devices and controller itself" using SIP, SOP, IPE, OPE signals, which falls squarely within the title of US7379344B2.

12. US7430140B2

• Full Citation: US7430140B2, "Multi-bank memory architecture for facilitating pipelined operations of different-sized data in an interleaved data transfer environment," issued to Cernea et al. on September 30, 2008.
• Publication/Filing Date: Issued: 2008-09-30; Filed: 2004-05-24.
• Brief Description: This patent is a continuation or related patent to US6742080B1, having the same title and inventors. It focuses on a multi-bank memory architecture that enables pipelined operations and handles different-sized data in an interleaved manner for efficient data transfer.
• Potential Anticipation for US9972381: As a patent with a filing date of May 24, 2004, it predates the priority date of US9972381. It shares the same core subject matter as US6742080B1, concerning multi-bank memory architecture and pipelined operations. Therefore, it has similar potential for anticipating US9972381's features related to concurrent and pipelined operations across multiple memory banks. The explicit mention of "pipelined fashion" in US9972381 (e.g., control module 126 in FIG. 1B) indicates a direct overlap.

13. US7433230B2

• Full Citation: US7433230B2, "Serial flash memory device and method of operating the same," issued to Park et al. on October 7, 2008.
• Publication/Filing Date: Issued: 2008-10-07; Filed: 2005-09-19.
• Brief Description: This patent describes a serial flash memory device and its operational methods, focusing on the commands and sequences for accessing and managing data within a flash memory through a serial interface.
• Potential Anticipation for US9972381: With a filing date of September 19, 2005, this patent predates the priority date of US9972381 (September 30, 2005) and is directly titled "Serial flash memory device and method of operating the same." This makes it highly relevant prior art that could potentially anticipate many aspects of US9972381's serial interface, command processing (e.g., page read, page program, erase commands as shown in FIGS. 3A, 5A, 6A), and overall operation of a serial flash memory.

14. US7515471B2

• Full Citation: US7515471B2, "Multiple independent serial link memory," issued to Oh et al. on April 7, 2009.
• Publication/Filing Date: Issued: 2009-04-07; Filed: 2006-10-19.
• Brief Description: This patent describes a memory device with multiple independent serial data links, where each link can communicate with any memory bank. It emphasizes concurrency and enhanced utilization. US9972381 explicitly states it is a continuation of a chain of applications, including this one ("U.S. application Ser. No. 11/583,354 filed on Oct. 19, 2006, now U.S. Pat. No. 7,515,471"). This patent also claims benefit of U.S. Provisional Application No. 60/722,368 filed on Sep. 30, 2005, the same provisional as US9972381.
• Potential Anticipation for US9972381: As US9972381 is a continuation in the same patent family and claims priority to the same provisional application (60/722,368) as US7515471B2, US7515471B2 would not be considered prior art under 35 U.S.C. § 102 for any claims in US9972381 that are fully supported by the common priority date of September 30, 2005. If US9972381 contains new subject matter not disclosed in US7515471B2's underlying application or the common provisional, then the publication date of US7515471B2 (2009-04-07) could potentially be prior art for those specific, later-invented claims. However, given the nature of continuations, it is expected that US7515471B2's disclosure is largely foundational to US9972381. The abstract of US7515471B2 ("Multiple independent serial link memory") directly mirrors the core concepts of US9972381, especially the dual-port and quad-port configurations with independent serial data links (e.g., FIGS. 1A, 1C of US9972381).

15. US7652922B2

• Full Citation: US7652922B2, "Multiple independent serial link memory," issued to Oh et al. on January 26, 2010.
• Publication/Filing Date: Issued: 2010-01-26; Filed: 2005-12-30.
• Brief Description: This patent describes a memory device with multiple independent serial data links and multiple memory banks, allowing for concurrent operations and improved data throughput. It explicitly claims benefit of U.S. Provisional Application No. 60/722,368 filed on Sep. 30, 2005, the same provisional as US9972381. US9972381 states it is a continuation-in-part of US11/324,023 (which issued as US7652922).
• Potential Anticipation for US9972381: Similar to US7515471B2, US7652922B2 is a direct parent patent in the same family as US9972381, claiming priority to the same provisional application (60/722,368). Therefore, US7652922B2 generally would not anticipate claims of US9972381 that are supported by the common priority date of September 30, 2005. Its disclosure is likely a direct foundation for US9972381. The title "Multiple independent serial link memory" indicates it broadly covers the fundamental architecture of multiple serial links and independent operation with memory banks, which is a central feature of US9972381.

Summary of Potential Anticipation

Without the specific claims of US9972381, a precise claim-by-claim anticipation analysis is not possible. However, based on the general descriptions and abstracts:

• Multi-bank concurrent operations: US6278632B1, US6742080B1, US6850450B2, US6919757B2, and US7430140B2 directly anticipate the concept of using multiple memory banks to perform concurrent or pipelined read, program, or erase operations in flash memory.
• Serial Interface for Flash Memory: US6987702B2, US7072205B2, US7330386B2, and US7433230B2 broadly anticipate the use of a serial interface for flash memory devices to reduce pin count and improve data transfer characteristics. These are highly relevant to the core technical problem US9972381 aims to solve.
• Parent/Sibling Applications: US7218556B2, US7515471B2, and US7652922B2 are likely part of the same patent family and share a common priority date with US9972381. Therefore, they are generally not "prior art" in the sense of anticipating claims that enjoy the benefit of that shared priority date. However, they are highly relevant for understanding the scope of the invention as it evolved through the continuation lineage. If US9972381 introduced new subject matter not present in the earlier applications and relied solely on its own filing date for those new claims, then these earlier-filed/published family members could potentially anticipate those specific new claims.

The most relevant independent prior art patents that explicitly disclose key features of US9972381 before its priority date include:

• US6278632B1 (2001-08-21): Multi-bank flash memory for random access and performance.
• US6742080B1 (2004-05-25) and US7430140B2 (2008-09-30, filed 2004-05-24): Multi-bank for pipelined operations.
• US6850450B2 (2005-02-01): Multi-bank for concurrent program operations.
• US6919757B2 (2005-07-19): Concurrent erase and program in flash memory.
• US6987702B2 (2006-01-17, filed 2004-03-24): Flash memory system with serial access.
• US7330386B2 (2008-02-12, filed 2005-09-09): Serial flash memory and method of operating.
• US7433230B2 (2008-10-07, filed 2005-09-19): Serial flash memory device and method of operating.

These patents collectively show that the concepts of multi-bank flash memory, concurrent operations within multi-bank memories, and serial interfaces for flash memory were known in the art prior to the earliest priority date of US9972381. The novelty of US9972381, if any, would likely lie in the specific combination of these features, the particular control mechanisms (like IPE/OPE signals and echo signals for daisy-chaining), or other specific architectural details that distinguish its claims from these earlier disclosures.

The numbered claims for US9972381 are not provided in the supplied patent text. A comprehensive obviousness analysis under 35 U.S.C. § 103 requires evaluating each claim against prior art. Without the claims, a definitive assessment of obviousness is not possible.

However, based on the patent's abstract and detailed description, the invention relates to semiconductor memory devices, particularly Flash memory, incorporating serial data link interfaces, advanced control mechanisms, concurrent operations, and daisy-chain configurations. The priority date for US9972381 is September 30, 2005.

Assuming representative claims covering the main disclosed features (e.g., a serial data interface for Flash memory, input/output enable signals (IPE/OPE), daisy-chaining with echo signals (IPEQ/OPEQ), target device addressing in a serial chain, and concurrent multi-bank operations via serial links), an obviousness argument would typically identify prior art references disclosing these elements and a motivation to combine them.

To illustrate, a hypothetical obviousness argument could be structured as follows, focusing on combining known concepts in serial memory and Flash technology:

Identified Features of US9972381 from Description:

1. Serial data link interface for semiconductor memory (Flash memory specifically): The patent emphasizes using serial interfaces to reduce pin count and improve signal integrity at high speeds, particularly for Flash memory.
2. Input Port Enable (IPE) and Output Port Enable (OPE) signals: Control signals for enabling/disabling serial data input and output ports (SIP, SOP) respectively.
3. Daisy-chain cascading with echo signals (IPEQ, OPEQ): Serially connecting multiple memory devices, where each device echoes received IPE and OPE signals to the next device (IPEQ, OPEQ).
4. Unique device identifiers and target device addressing (TDA): Each device has a unique ID, and input data streams include a TDA. Devices parse the TDA to determine if they are the target, ignoring data if not, to save processing time.
5. Multi-bank memory with concurrent operations: Memory devices with multiple banks (e.g., Flash banks) that can perform concurrent operations (e.g., read while write) either through multiple serial links or a "virtual multiple link" configuration using a single serial link.
6. Serial-to-parallel and parallel-to-serial conversion: The serial link interface converts serial input data to parallel data for the memory bank and parallel data from the memory bank to serial output data.

Potential Prior Art Combinations for Obviousness:

Given the general knowledge in the field of memory devices and serial communication systems prior to September 30, 2005, a person having ordinary skill in the art (PHOSITA) would have been motivated to combine known elements to achieve the functionality described in US9972381.

Combination 1: Serial Interface for Flash Memory with I/O Control (Features 1, 2, 6)

• Reference A (Disclosing Serial Interface for Memory & Conversion): Many prior art patents and publications before 2005 discussed the benefits of serial interfaces for memory, particularly for reducing pin count and improving performance and signal integrity. For example, some patents describe general serial-to-parallel and parallel-to-serial conversion within memory devices to interface with internal parallel memory arrays.

• Reference B (Disclosing Enable Signals for Data Transfer): It was well-known in digital electronics to use enable signals to control data flow into and out of registers and ports. For instance, serial peripheral interface (SPI) and similar protocols often employed chip select (CS) or enable lines to gate data. Applying distinct input enable (IPE) and output enable (OPE) signals to control dedicated serial input (SIP) and output (SOP) ports for flexible data communication would be a straightforward design choice for a PHOSITA.

• Motivation to Combine: A PHOSITA facing the challenges of increasing Flash memory speed and density while managing pin count and signal integrity (as noted in the background of US9972381) would naturally seek to apply serial interfaces (Reference A) to Flash memory. To provide precise control over when a serial port receives or transmits data, integrating dedicated enable signals (Reference B) for input and output operations would be an obvious design decision, allowing the memory controller more flexibility, as highlighted in US9972381. The conversion between serial and parallel data streams (Reference A) is inherent to interfacing a serial link with a parallel memory core.

Combination 2: Daisy-Chained Serial Memory with Device Addressing and Echo Signals (Features 3, 4)

• Reference C (Disclosing Daisy-Chained Serial Devices): Daisy-chain configurations for serially connecting multiple devices were common in various electronic systems (e.g., SPI bus, JTAG, certain memory modules) prior to 2005. These systems often involved passing data or control signals down a chain.

• Reference D (Disclosing Unique Device Identifiers and Target Addressing): Methods for addressing individual devices in a multi-device serial bus were also well-established. This could involve unique device IDs and a target address field in the data stream, where non-target devices would forward or ignore data.

• Reference E (Disclosing Signal Echoing/Re-transmission in Serial Chains): To ensure signal integrity and proper synchronization over longer daisy chains, repeating or echoing control signals (e.g., clock, enable) to subsequent devices was a known technique.

• Motivation to Combine: When designing a scalable Flash memory system requiring increased capacity, a PHOSITA would consider daisy-chaining (Reference C) as an efficient way to expand memory without dramatically increasing the controller's I/O pins. To effectively manage data flow and commands to specific devices in such a chain, implementing unique device identifiers and target addressing (Reference D) is a necessary and obvious step. Furthermore, to maintain robust communication in a long serial chain, echoing control signals (Reference E) like IPE and OPE (from Combination 1) would be a logical extension to ensure reliable operation of downstream devices. The patent explicitly states "when devices are serially cascaded in a system they may further comprise output control ports that “echo” the received IPE and OPE signals to external devices. This allows the system to have point-to-point connected signal ports (e.g., SIP/SOP, IPE/IPEQ, OPE/OPEQ, SCLKI/SCLKO) to form a daisy-chain cascading scheme". This directly points to a known architectural choice for daisy-chaining to improve signal integrity and control.

Combination 3: Concurrent Multi-Bank Operations via Serial Links (Feature 5)

• Reference F (Disclosing Multi-Bank Flash Memory with Concurrent Operations): It was standard practice in Flash memory design to include multiple memory banks to enable concurrent operations (e.g., reading from one bank while programming another) to improve overall throughput. These operations were typically managed by an internal controller.

• Reference A (from Combination 1 - Serial Interface): Discloses the use of serial interfaces for memory access.

• Motivation to Combine: A PHOSITA seeking to maximize the performance of a serial Flash memory device (Reference A) would naturally combine it with known multi-bank architectures capable of concurrent operations (Reference F). The challenge would then be to expose and manage this concurrency through the serial interface. Whether by employing multiple independent serial links, or by intelligently arbitrating access to multiple banks through a single serial link (a "virtual multiple link" where the link is freed while a bank operation is busy, as described in US9972381), would be an obvious optimization. The patent mentions that the "control module 126 is configured to perform or execute two operating processes or threads, so that serial data link interface 120 can exchange data with memory banks 122 and 124 in a pipelined fashion". This pipelined or concurrent operation across multiple banks to improve utilization was a known objective in memory system design.

Conclusion

While specific claims are absent, the core inventive concepts of US9972381, such as serial interfaces for Flash memory, specialized I/O enable signals, daisy-chaining with echo signals, target device addressing, and concurrent multi-bank operations, represent a combination of elements that were individually known or readily apparent to a PHOSITA in the field of semiconductor memory design prior to September 30, 2005. The motivation to combine these elements would stem from well-recognized industry challenges: the need for higher speed, increased capacity, reduced pin count, and improved overall system performance and flexibility in memory devices, especially for Flash memory in mobile and high-data-rate applications, as explicitly stated in the background of the invention. The patent itself describes these features as improving "device utilization (e.g., bus utilization and core utilization)" and achieving "reduced pin count resulting from the virtual multiple link configuration". These are common engineering goals that would drive a PHOSITA to combine existing techniques.

Therefore, without the precise language of the claims, it is highly probable that claims encompassing these broadly described features would have faced obviousness challenges based on combinations of prior art teaching serial communication, multi-bank memory management, and daisy-chain architectures with addressing schemes.

To accurately detail the patent term adjustments (PTA), patent term extensions (PTE), continuation/divisional applications, related family members, and the projected expiration date for US patent 9972381, a direct query to the USPTO's Patent Public Search or Patent Center portal is necessary. While direct access to the live USPTO database is not available, based on the provided patent text and general knowledge of patent term calculations, the following information can be synthesized:

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE)

The provided patent text does not explicitly state any specific Patent Term Adjustment (PTA) or Patent Term Extension (PTE) applied to US9972381. PTA compensates patent applicants for certain delays incurred by the USPTO during prosecution of a utility or plant patent application. PTE, governed by 35 U.S.C. § 156, is typically granted for patents covering drug products, medical devices, food additives, or color additives to compensate for delays during regulatory review and approval by agencies like the FDA. Given the patent's subject matter relates to semiconductor memory devices, it is unlikely to be eligible for a PTE.

The Google Patents page for US9972381 lists an "Anticipated expiration" date of 2025-12-30. This date, which is slightly later than the nominal 20-year term from the earliest priority date (September 30, 2005), suggests that some PTA may have been applied.

Continuation Applications, Divisional Applications, and Related Family Members

US9972381 is part of an extensive patent family, originating from a provisional application and having a long chain of continuation applications. According to the "CROSS REFERENCE TO RELATED APPLICATIONS" section in the patent's description, US9972381 is:

• A continuation of U.S. application Ser. No. 15/692,206, filed on Aug. 31, 2017.
• Which is a continuation of U.S. application Ser. No. 15/345,552, filed on Nov. 8, 2016 (issued as U.S. Pat. No. 9,779,804).
• Which is a continuation of U.S. application Ser. No. 14/984,303, filed on Dec. 30, 2015 (issued as U.S. Pat. No. 9,524,783).
• Which is a continuation of U.S. application Ser. No. 14/156,047 filed on Jan. 15, 2014 (issued as U.S. Pat. No. 9,257,193).
• Which is a continuation of U.S. application Ser. No. 13/867,437 filed on Apr. 22, 2013 (issued as U.S. Pat. No. 8,654,601).
• Which is a continuation of U.S. application Ser. No. 13/463,339 filed on May 3, 2012 (issued as U.S. Pat. No. 8,427,897).
• Which is a continuation of U.S. application Ser. No. 12/882,931 filed Sep. 15, 2010 (issued as U.S. Pat. No. 8,199,598).
• Which is a continuation of U.S. application Ser. No. 12/275,701 filed Nov. 21, 2008 (issued as U.S. Pat. No. 7,826,294).
• Which is a continuation of U.S. application Ser. No. 11/583,354 filed on Oct. 19, 2006 (issued as U.S. Pat. No. 7,515,471).
• Which is a Continuation-in-Part of U.S. application Ser. No. 11/324,023 filed on Dec. 30, 2005 (issued as U.S. Pat. No. 7,652,922).
• This chain of applications ultimately claims the benefit of U.S. Provisional Application No. 60/722,368 filed on Sep. 30, 2005, entitled "Multiple Independent Serial Link Memory." Additionally, U.S. application Ser. No. 11/583,354 also claims the benefit of U.S. Provisional Application No. 60/847,790 filed on Sep. 27, 2006, and U.S. Provisional Application No. 60/722,368 filed on Sep. 30, 2005, entitled "Memory with Output Control."

This detailed lineage indicates a robust family of related patents and applications stemming from the initial provisional filing. No divisional applications are explicitly mentioned in this continuity data.

Projected Expiration Date

For utility patents filed on or after June 8, 1995, the patent term generally expires 20 years from the date on which the application for the patent was filed, or if the application claims priority to an earlier application under 35 U.S.C. §§ 120, 121, or 365(c), 20 years from the filing date of the earliest such application, plus any Patent Term Adjustment (PTA).

The earliest priority date for US9972381 is September 30, 2005, from U.S. Provisional Application No. 60/722,368. Therefore, the nominal expiration date (without any adjustments) would be September 30, 2025.

Google Patents lists an "Anticipated expiration" of 2025-12-30. This suggests approximately three months of PTA have been granted, extending the term beyond the nominal 20 years from the priority date. However, Google Patents also states the "Legal status" as "Expired - Lifetime," which directly contradicts the issue date of 2018 and the typical 20-year patent term from the earliest priority date. Given the issue date of May 15, 2018, for a utility patent, it is highly improbable that the patent would have already expired by the current date of 2026-05-28, especially with a priority date of 2005. The "Expired - Lifetime" status appears to be an error in the Google Patents display for this particular entry. Based on the anticipated expiration date provided by Google Patents, and assuming PTA is included, the more accurate projected expiration date is December 30, 2025.