US 6972790

I'll research this patent number across the available sources.

Let me search specifically for 2026 Federal Circuit activity and any PTAB proceedings on this exact patent.

US Patent 6,972,790 — Analyst Summary

Scope note on sources. The results below are grounded in the patent's own front-page/abstract text (USPTO Official Gazette entry mirrored at Indiana University's virtual disk library, and the Google Patents record), cross-checked against RPX Insight and Patexia. I found no record of any 2026 Court of Appeals for the Federal Circuit docket involving US 6,972,790. My CAFC-2026 searches returned only unrelated 2026 Federal Circuit materials (CRISPR interference, Exafer v. Microsoft, TrackTime, Constellation Designs v. LG, etc.). I therefore cannot confirm any 2026 CAFC activity, and treat that as an explicit negative-with-uncertainty finding rather than a clearance.

Bibliographic data

Ownership chain of record: Symagery Microsystems Inc. → Psion Teklogix Systems Inc. (change of name, 2005) → Harusaki Technologies, LLC (2007) → Intellectual Ventures Assets 99 LLC (2019) → Steephill Technologies LLC (2019) → Cedar Lane Technologies Inc. (2019).

Family note (do not conflate): A co-asserted patent, US 8,537,242 B2 (application 11/259,791, filed Oct 27, 2005), is a divisional of 09/742,723 — i.e., the '790 application. It carries method claims rather than the apparatus claims of '790. Separately, an HTC complaint list included US 6,972,774 alongside '790; that is a different patent number and should not be merged with this record.

Abstract (verbatim)

"An interface for receiving data from an image sensor having an imaging array and a clock generator and for transferring the data to a processor system is described. The interface comprises a memory for storing the imaging array data and the clocking signals at a rate determined by the clocking signals. In response to the quantity of data in the memory, a signal generator generates a signal for transmission to the processor system and a circuit controls the transfer of the data from the memory at a rate determined by the processor system. The memory may be a first-in first-out (FIFO) buffer or an addressable memory. The interface is preferably integrated on the same die as the image sensor. The signal generator may generate either an interrupt signal for transmission to the processor system or a bus request signal for transmission to a bus arbitration unit for the processor system."

Independent claims — plain-language overview

Claim 1 — the interface (apparatus). An interface that sits between an image sensor and a processor system, where the sensor has (a) an imaging array and (b) a clock generator. It has three elements:

1. A memory that stores both the imaging-array data and the clocking signals, and does so at a rate set by the clocking signals (i.e., the sensor's clock drives the write side).
2. A signal generator that produces a signal to the processor system in response to the quantity of data in the memory (e.g., an interrupt or bus request once a fill threshold is reached).
3. A control circuit that governs transfer of data out of the memory at a rate determined by the processor system (the read side, decoupled from the sensor clock).

The commercially important idea is bidirectional rate decoupling: the sensor dictates the fill rate, the host dictates the drain rate, with a buffer and a fill-triggered alert in between.

Claim 15 — the integrated semiconductor imaging circuit. A chip-level claim for use with a processing system that has a data bus. It requires:

• an imaging array sensor with an array of sensing pixels and an array address generator integrated on a die;
• an interface integrated on that same die, which receives data from the sensor as determined by the sensor and transfers data to the processing system as determined by the processing system;
• within that interface, a memory for storing imaging array data and address signals at a rate determined by the imaging array sensor, and a circuit controlling transfer from the memory to the data bus at a rate determined by the processing system.

Claim 15 is the "system-on-a-die" claim: the single-die co-integration of sensor plus interface (and, per the specification and dependent claims, optionally the bus arbitration unit) is its distinguishing structural requirement.

Dependent claims (2–14, 16–21) — themes, per the specification: the memory implemented as a FIFO buffer or as an addressable memory; the alert implemented as an interrupt signal to the processor or a bus request signal to a bus arbitration unit; the control circuitry comprising a command decoder (address/command signals from the processor), configuration registers (FIFO limit, interrupt mask, interrupt register, output bus width), a read control, and a bus command unit that takes bus control and supplies read-out addresses; a bus arbitration circuit integrated on the same die; and array registers defining the number of rows/columns to be used.

Technical problem and solution (context)

The specification frames the problem as an incompatibility between "video style" CMOS image sensor output — a continuous, clock-synchronized pixel stream whose clocks are output to synchronize the data — and the random-access address/control interface of commercial microprocessors. Bridging the two with external "glue logic," the patent argues, erodes the cost benefit of CMOS integration (col. 1 discussion; abstract). The disclosed fix is an on-die buffering interface that alerts the host when a data threshold is reached, letting the CPU multi-task instead of servicing a raw video stream continuously.

Enforcement history (for risk context)

6972790 was asserted by Cedar Lane Technologies in a very large campaign (Stanford NPE Litigation Database, https://npe.law.stanford.edu/patent/6972790), typically paired with US 8,537,242 and often with US 6,473,527. Representative venues/defendants include W.D. Tex. before Judge Albright (many 2022 filings), D. Del., E.D. Va., C.D. Cal., W.D. Wash., N.D. Ill., and others. Reported outcomes I could verify are procedural, not merits-based: voluntary dismissals (e.g., Cedar Lane v. Zhuhai RaySharp, W.D. Tex. 6:22-cv-00971-type filings; Cedar Lane v. Amlogic, 1:23-cv-01242, dismissed with prejudice April 17, 2024), consent judgments (Cedar Lane v. Speco Technologies, 1:22-cv-07970), and at least one documented settlement/license (Reolink/睿联数字, US$10,000 paid, 2021). No claim-construction order, invalidity holding, or infringement merits ruling on '790 surfaced in my searches. Active Cedar Lane docket activity extends into late 2025 (e.g., Cedar Lane Technologies Inc. v. Neosapience, Inc., 2:25-cv-00823, with a voluntary dismissal entry dated 2025-12-26 and AO-120 notice filed 2026-01-14).

Explicit uncertainties

1. No CAFC 2026 docket for '790 found. Absence of a hit is not proof of absence in district/PACER or CAFC docketing, which are not fully indexed by the search sources I used.
2. IPR/PTAB status unverified. My PTAB-specific query was cut off; I cannot confirm whether any inter partes review of '790 was filed or instituted. Do not treat this as a no-IPR finding.
3. Expiration date. Google Patents lists an adjusted expiration of 2023-08-01, which is earlier than 20 years from the Dec. 21, 2000 filing (Dec. 21, 2020) plus any PTA — i.e., the listed date cannot be derived arithmetically from the bibliographic data alone. Report the date as listed rather than rationalized.
4. Assignee field. Google Patents expressly disclaims accuracy of assignee listings; the chain above is drawn from recorded assignments and the OG front page, which agree on origin (Symagery/Psion Teklogix) but label the original assignee differently ("Psion Systems Inc." vs. "Psion Teklogix Systems Inc.").
5. Litigation outcomes were verified only through secondary sources (NPE database, IPWatchdog roundups, PatSnap litigation writeups, UniCourt/CourtListener entries); none substitutes for the PACER dockets themselves.

I'll search for litigation involving US 6,972,790 (the "Host interface for imaging arrays" patent), starting with the URLs embedded in the patent record and then verifying against litigation databases.

The record shows this patent has an extensive assertion history. Let me dig into the campaign details, IPR challenges, and any appellate rulings.

Litigation Report — U.S. Patent No. 6,972,790

Disclaimer up front: The following is compiled from public litigation aggregators and docket mirrors (Unified Patents litigation portal, Stanford NPE Litigation Database, CourtListener/RECAP, UniCourt, Docket Alarm, RPX Insight, Justia Dockets, PatSnap). A truly complete, de-duplicated list for this patent would require a full PACER docket sweep or a Darts-IP family query (the Google Patents record links: https://patents.darts-ip.com/?family=22648835). Where I could not independently confirm a detail, I say so.

1. Patent identification (read literally)

Chain of title (as recorded): Symagery Microsystems Inc. → Psion Teklogix Systems Inc. (change of name, 2005-09-19) → Harusaki Technologies, LLC (2007-12-13/17) → Intellectual Ventures Assets 99 LLC (nunc pro tunc, 2019-01-23) → Steephill Technologies LLC (2019-03-11) → Cedar Lane Technologies Inc. (2019-05-13).

Because the patent expired (adjusted expiration 2023-08-01), any later filings can only seek past damages for the pre-expiration window; the patent cannot be enforced for ongoing infringement after that date.

2. Bottom line

Yes, there is extensive known litigation, and virtually all of it arises from a single campaign: Cedar Lane Technologies Inc., a Canadian NPE incorporated April 29, 2019, founded by attorney Greg Benoit, which acquired this patent (and its divisional, US 8,537,242) out of the Intellectual Ventures pipeline and asserted them against hundreds of defendants.

The '790 patent is typically asserted in a pair with US 8,537,242 ("Host interface for imaging arrays," the divisional), and sometimes alongside US 6,473,527, US 8,165,867, US 7,292,261, and US 6,924,832. As reported by RPX (Jan. 31, 2022), Cedar Lane's campaign had passed 150 defendants, asserting nearly 50 patents, with the '790/'242 image-processing pair accused against "smart home products that support Google Assistant" and camera products (e.g., Wyze Labs, 1:21-cv-01704).

A KIPO-published analysis (data credited to Lex Machina) states Cedar Lane's first campaign ran 367 cases from 2018-01-01 through 2022-12-31, with 310 closed by settlement, 13 closed for other reasons, 44 pending — consistent with a pure nuisance-settlement model. Reporting by Gadgets, Gigabytes & Goodwill confirms no Cedar Lane case reached trial.

I found no appellate (CAFC) decision and no PTAB inter partes review, PGR, or CBM specifically challenging US 6,972,790. I searched for IPR petitions naming the '790 patent and found none. I cannot rule out a petition I did not surface, but I found no evidence of one. (Note that one Cedar Lane case involved an IPR-related reference only tangentially — the N.D. Cal. sanctions episode described below — not a PTAB challenge to '790.)

3. Representative confirmed cases

The following have specific confirmation in the search results. Outcomes are as reported; several docket entries are stale.

Korean-defendant cases (from a KIPO-published table; parties anonymized in the source, dates as printed):

(The KIPO document's own court/case-number pairing is reproduced literally; I did not independently verify the venue code against PACER.)

Other Cedar Lane '790-family cases I could not fully resolve but that appeared in the record: Acer (D. Del., Dec. 2019 — stayed pending dismissal/settlement); Blackmagic Design (N.D. Cal., Feb. 2020 — stipulated dismissal with prejudice after sanctions); LG Electronics (stayed pending dismissal); Arrow Electronics, TCL Communication, and WPG Americas (all in pleadings stage as of Oct. 2020); Coolpad (D. Del. — '790 asserted, Exhibit 8 claim chart); Wyze Labs (1:21-cv-01704, D. Del.); Basler (2:21-cv-05160); Walmart (6:21-cv-01234); WideOpenWest (1:21-cv-03154).

4. The large W.D. Tex. / E.D. Va. / D. Del. wave (2022-2023)

The Google Patents record for this patent carries a "Family has litigation" block containing well over a hundred case URLs, overwhelmingly W.D. Tex. (Judge Alan D. Albright) and D. Del. filings from 2022-2023, plus a cluster of C.D. Cal., N.D. Cal., E.D. Va., D. Colo., W.D. Wash., W.D. Wis., N.D. Ill., N.J., and S.D.N.Y./E.D.N.Y./W.D.N.Y. cases. Examples of case numbers listed there include 4:20-cv-01987, 4:20-cv-02169, 1:20-cv-01273, 2:22-cv-00273, 3:22-cv-00468, 6:22-cv-01079, 1:22-cv-01402, 1:23-cv-00613, 1:23-cv-01242, and dozens more.

Important caveat: that Google Patents litigation block is labeled "Family has litigation" and the linked Darts-IP URL is a family query (family=22648835). It therefore mixes cases asserting the '790 patent with cases asserting sibling family member US 8,537,242 and possibly other Cedar Lane patents. I would not represent every URL in that block as a '790 case without separate verification. The Stanford NPE Litigation Database entry for patent 6972790 is the better single source for isolating '790-specific cases — it returned at least 22 entries in the excerpt I retrieved (top entries being the Selex ES, Vantage Robotics, Zenitel, Sixt Rent A Car, Enterprise Holdings, Openeye US, Motorola Solutions, Ricoh USA, Security Camera Warehouse, PixArt Imaging, Zhuhai RaySharp, Tattile, Vanguard Integrated Solutions, Vimar, Samriddhi Automations, Silent Sentinel, NEXCOM, Moxa, Logipix, Longse, Domo Tactical Communications cases).

5. Notable non-outcome events worth flagging

• Sanctions (N.D. Cal., 2020): In the Blackmagic Design litigation, Judge Vince Chhabria granted a motion to strike a third amended complaint, dismissed induced/contributory infringement claims, and ordered Cedar Lane and attorney Isaac Rabicoff to show cause why the case should not be dismissed for failure to prosecute and why counsel should not be sanctioned for "taking positions in his filings that were objectively frivolous … and did so in bad faith," including misrepresentations about Rule 15. The parties then stipulated to dismissal with prejudice (October 2020).
• Venue/filer pattern: Cedar Lane's primary counsel is Rabicoff Law LLC (Isaac Phillip Rabicoff) and, in Delaware, David W. deBruin (Bayard, P.A.); Howard L. Wernow appeared in the BLU Products case. The W.D. Tex. filings concentrated before Judge Albright.
• Assignment to third parties: The record shows Intellectual Ventures Assets 99 LLC → Steephill Technologies LLC → Cedar Lane Technologies Inc. in 2019 — i.e., the patent passed through two shell entities in roughly four months before assertion.
• Litigation data source: Google Patents lists the current assignee as Cedar Lane Technologies Inc. and marks the family as having litigation, with ~150+ docket URLs drawn from the Unified Patents litigation dataset (CC-BY 4.0).

6. What I could NOT establish

1. No CAFC appeal involving US 6,972,790 was identified. If an appeal exists, it would likely be tied to a W.D. Tex. or D. Del. judgment; I found no such judgment.
2. No IPR/PGR/CBM challenging the '790 patent was identified.
3. No pre-Cedar Lane enforcement — I found no evidence that Psion, Symagery, Psion Teklogix, Harusaki Technologies, or Intellectual Ventures sued anyone on this patent. All known assertion appears to be Cedar Lane's.
4. Final dispositions for the majority of cases are not public in the aggregated sources; the pattern is overwhelmingly voluntary dismissal, likely following confidential settlement. The KIPO/Lex Machina data suggests ~310 of ~367 campaign cases settled.
5. Defendant-side identification is frequently absent from the pleadings themselves — multiple Cedar Lane complaints refer to "Exemplary Defendant Products" identified only in exhibits not filed with the complaint.

If you need a court-ready enumeration, the authoritative next steps are (a) PACER docket pulls for each case number above, (b) the Unified Patents litigation portal query for this patent, and (c) a Darts-IP family report on family 22648835 with the sibling-patent cases filtered out.

Proceedings overview

Total AIA trial proceedings on file for US 6,972,790: 0 — no IPR, PGR, or CBM petition has ever been filed against this patent (0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denied), so the bottom line for a defendant is that the patent's claims are completely untested at the PTAB, carry a full presumption of validity, and there is no § 315(e)(2) estoppel on the books against anyone — the "hardened patent" narrative does not apply here, but neither does the "claims are already dead" defense, so any validity attack must be built from scratch in district court or via ex parte reexamination.

No proceedings to itemize

The structured "PTAB proceedings on file" block (USPTO Open Data Portal ingest) returns an empty list, and my independent web searches surfaced no IPR/PGR/CBM petition, institution decision, Final Written Decision, or Federal Circuit appeal involving U.S. Patent No. 6,972,790. I am not listing any proceeding number, because inventing one would be fabrication. Corroborating signals:

• Google Patents' litigation panel for the patent lists only district court cases (Texas S.D., New York S.D., Wisconsin W.D., Washington W.D., Virginia E.D., California C.D./N.D., Colorado, Delaware, New Jersey, etc.) — no PTAB proceedings are listed. Source: https://patents.google.com/patent/US6972790/en
• Stanford's NPE Litigation Database page for 6972790 lists only district court civil actions. Source: https://npe.law.stanford.edu/patent/6972790
• Third-party litigation trackers (PatSnap Eureka case pages for Cedar Lane matters) record "Validity challenges: None recorded" for US6972790B2 — e.g., the Cedar Lane v. Dallmeier / Zhuhai RaySharp case write-ups.

Adjacent proceeding — NOT on this patent (flagged separately so it is not mistaken for a '790 trial)

IPR2020-00006 — Unified Patents, LLC v. Cedar Lane Technologies Inc.

• Type: Inter Partes Review (against U.S. Patent No. 7,173,177, a different Cedar Lane patent — the playlist-owned/unowned-UI patent, not the imaging-array interface patent)
• Filed: 2019-10-03
• Status: Final Written Decision issued; the asserted independent claim of the '177 patent held unpatentable
• Institution decision: instituted 2020-03-18 on all challenged claims
• Final Written Decision: 2021-02-12
• Defensive value for the '790: None directly — but it establishes that Unified Patents (a defensive aggregator) has actively targeted Cedar Lane's IV-derived portfolio, and chose not to challenge the '790. That is a meaningful negative signal about the '790's attractiveness as an IPR target, not a positive one. Sources: https://www.unifiedpatents.com/insights/2021/2/12/cedar-lane-patent-held-unpatentable and https://litigation.rpxcorp.com/ptab/10878

Strategic summary

Claim status: everything is UNTESTED. No claim of US 6,972,790 — independent claim 1 or any dependent claim — has been canceled, confirmed, or even construed in an AIA trial. The claim set remains exactly as issued on 2005-12-06. The patent's term ended with an adjusted expiration of 2023-08-01 (Google Patents legal-status entry: "Expired – Lifetime, expires 2023-08-01"), so the practical exposure is now limited to past/pre-expiration damages in suits filed within the six-year § 286 lookback, plus ongoing suits filed before expiry (Cedar Lane continued docketing '790 cases into 2023, including Cedar Lane Techs. v. Amlogic, 1:23-cv-01242 (D. Del.)).

Estoppel landscape: there is none. Because no IPR was ever instituted, 35 U.S.C. § 315(e)(2) estoppel attaches to no party. No petitioner, real party in interest, or privy is barred from raising any invalidity ground. A defendant today can assert § 102/§ 103 grounds based on any art, including art that would have been "reasonably could have raised" material in a hypothetical IPR. The corollary is that the patent owner cannot point to any prior IPR win to argue the claims have been stress-tested. Note the flip side of the empty docket: the accuser here is Cedar Lane Technologies Inc. (current assignee per Google Patents; chain: Symagery Microsystems → Psion Teklogix → Harusaki Technologies → Intellectual Ventures Assets 99 → Steephill Technologies → Cedar Lane), a high-volume NPE that has filed hundreds of district court actions, and Cedar Lane's litigation track record (as compiled in the KIPO/IP-Navi NPE studies) shows the overwhelming majority of its cases resolved by settlement/voluntary dismissal, not merits rulings — a business model that, empirically, Cedar Lane prefers to avoid the PTAB rather than litigate validity there.

Pattern signals. (1) Same petitioner, multiple IPRs? No — zero petitions on this patent by anyone. (2) Unified Patents in the chain? Unified is in Cedar Lane's PTAB history but only on the '177 patent (IPR2020-00006, claims invalidated 2021-02-12), and Cedar Lane's litigation filings are tagged in IPWatchdog's roundups as "[IV selloff]" / "[Steephill Technologies, IV]" — Unified, RPX-adjacent entities, or other aggregators have not mounted a '790 challenge despite the patent being asserted in excess of 100 district court cases (W.D. Tex. and D. Del. dominant; most before Judge Alan D. Albright). (3) Patent owner appeals? None — there is no FWD to appeal.

Recommended next steps

• If you are a defendant being asserted on the '790: state plainly in your validity analysis that there is no PTAB record at all. You cannot borrow anyone's estoppel, and no claim has been canceled. Any invalidity case must be built on your own prior-art search (the patent's own cited art includes US 4,873,628; US 5,786,851; US 5,801,773; US 5,920,343; US 6,021,449; US 6,064,355; US 6,493,025; US 6,704,310; US 6,721,008; US 6,833,862 per the KIPO NPE study citation list) and on the claim-construction battleground: independent claim 1's "memory for storing imaging array data and clocking signals," "signal generator ... in response to the quantity of data in the memory," and "circuit for controlling the transfer ... at a rate determined by the processor system" are the likely pressure points.
• Timing/practicality of filing an IPR now: the patent expired 2023-08-01. The Board has entertained IPRs on expired patents in some circumstances, but an expired patent (especially one whose infringement window has closed) makes an IPR a weak economic play; the more likely vehicles are district court invalidity, a § 282 defense, or ex parte reexamination under 35 U.S.C. § 302 (which has no time bar and no estoppel). I found no record of any pending or concluded ex parte reexamination of the '790, but I cannot rule one out from the sources reviewed — verify on USPTO PatentCenter before relying on it.
• If you want to confirm the empty docket yourself: search the USPTO PTAB E2E / PTAB Decisions systems and PatentCenter for application 09/742,723 and patent 6,972,790 (https://e2e.uspto.gov and https://www.uspto.gov/patents/ptab/decisions). The absence of PTAB activity is itself the signal: the '790 has been asserted in well over a hundred suits, yet no defendant, manufacturer, or defensive aggregator ever financed an IPR against it — either because the settlement economics were too cheap (many of Cedar Lane's outcomes were de minimis, e.g., a documented $10,000 settlement-and-license in the Reolink/睿联数字 matter reported by IPRdaily), or because the claims were seen as too narrow/expired to be worth killing at the Board. Do not assume the latter without your own prior-art analysis.
• If you cite anything in a brief, cite the empty docket as of 2026-09-28 and re-check before filing — a petition could have been filed since the last ODP ingest.

I'll research the assignment record and NPE signals for this patent across the available sources.

Let me search for the specific assignment records and correspondents of record.

Assignment & Ownership Analysis — US 6,972,790 B2 ("Host interface for imaging arrays")

Source-access caveat up front (read this before the timeline). I could not directly query USPTO Assignment Center/PEDS in this session; the analysis below is reconstructed from (a) the recorded-assignment legal-events block mirrored on the Google Patents record for this patent (https://patents.google.com/patent/US6972790B2/en), which is populated from USPTO assignment data, and (b) secondary corroboration (Stanford NPE Litigation Database, the KIPO NPE report, IPRdaily). The Google Patents legal-events block does not expose reel/frame numbers or the correspondent field. Only one reel/frame is actually quoted anywhere in the record I retrieved — Reel 020243 / Frame 0226, which appears in the text of the 2007 corrective assignment. Every other "Reel NNNNNN/NNNN" field below is therefore marked not surfaced, not invented. Correspondent-of-record data is not retrievable from the sources I reached and is flagged as a gap rather than guessed. This is a data limitation, not a statement that the records lack that field.

Inventors

• Single named inventor. No co-inventors appear on the front page or in the assignment record.
• Departure pattern: cannot be assessed — with one inventor there is no group-departure signature to read, and I found no evidence of Suska leaving Symagery within 12 months of filing. The available record does not support the "all inventors depart pre-sale" flag.
• Note the geographic/entity alignment: inventor residence (Ottawa) and assignee (Symagery Microsystems, Ottawa) match, consistent with a genuine employer-employee invention assignment rather than a manufactured record.

Original assignee

• Entity named on the issued patent: the Og front page lists Psion Teklogix Systems Inc., Mississauga, Canada, which is the post-change-of-name successor to Symagery Microsystems Inc. Google Patents' "Original Assignee" field instead reads "Psion Systems Inc." — this is the assignee-field discrepancy already flagged in the earlier summary (Google expressly disclaims accuracy of assignee listings). The recorded assignments are the better evidence and point to Symagery Microsystems Inc. → Psion Teklogix Systems Inc. (change of name only).
• Primary line of business: Symagery Microsystems was an Ottawa CMOS image-sensor developer (the specification's own background is written from the perspective of a CMOS sensor vendor competing with CCD). After the change of name / absorption into Psion Teklogix, the business sat inside Psion Teklogix / Psion PLC — rugged handheld computers, auto-ID, and barcode-imaging scanners. The '790 interface (on-die FIFO between a CMOS sensor and a microprocessor bus) is squarely a barcode/imager front-end technology, i.e., a product-embodying line of business at the time of the 2007 transfer, not an after-the-fact shell. I have not independently verified a specific shipping part number or datasheet, so treat "shipped a product" as probable but not documented in the sources retrieved.
• Current status: the original assignee entity no longer owns the patent and its successor chain exited the imaging IP in 2007 (see timeline). No bankruptcy is evidenced anywhere in the record — the 2007 transfer reads as a corporate divestiture, not a Chapter 7/11 sale. I could not locate an SEC filing documenting the 2007 divestiture (Psion PLC was LSE-listed, and Psion Teklogix's IP divestiture does not appear to be a US SEC-reported event I could retrieve). Flagged as a gap.

Assignment timeline

All entries below are recorded USPTO assignments appearing in the patent's recorded-assignment/legal-events data. Conveyance types are quoted as recorded. Where not textually available, reel/frame and correspondent are shown as not surfaced.

• 2000-12-21 (executed) / recorded 2000-12-21 — Reel not surfaced

  • Conveyance: Assignment of assignors' interest
  • Assignor: SUSKA, Mark
  • Assignee: SYMAGERY MICROSYSTEMS INC.
  • Correspondent: not surfaced
  • Context: Original inventor-to-employer assignment of rights — routine, pre-issue.

• 2005-09-19 (executed) / recorded 2005-09-19 — Reel not surfaced

  • Conveyance: Change of Name
  • Assignor: SYMAGERY MICROSYSTEMS INC.
  • Assignee: PSION TEKLOGIX SYSTEMS INC.
  • Correspondent: not surfaced
  • Context: Internal reorg / change of name only — no change in beneficial ownership.

• 2007-12-13 (executed) / recorded 2007-12-13 — Reel not surfaced (but see next entry: the corrective record fixes this recording at Reel 020243/0226)

  • Conveyance: Assignment of interest
  • Assignor: TEKLOGIX SYSTEMS INC.
  • Assignee: HARUSAKI TECHNOLOGIES, LLC
  • Correspondent: not surfaced
  • Context: Divestiture of the imaging IP out of the operating company to a holding entity — the first step onto the NPE-side of the chain.

• 2007-12-17 (executed) / recorded 2007-12-17 — Reel 020243 / Frame 0226 ✅ (the one reel/frame expressly quoted in the record)

  • Conveyance: Corrective Assignment ("to correct the name of the assignor previously recorded on Reel 020243 Frame 0226")
  • Assignor: PSION TEKLOGIX SYSTEMS INC. (correcting prior "Teklogix Systems Inc.")
  • Assignee: HARUSAKI TECHNOLOGIES, LLC
  • Correspondent: not surfaced — but note the recording-context flag below
  • Context: Correction of assignor's legal name on the 2007-12-13 record — administrative, not a separate transfer.

• 2019-01-23 (executed) / recorded 2019-01-23 — Reel not surfaced

  • Conveyance: Nunc pro tunc Assignment
  • Assignor: HARUSAKI TECHNOLOGIES, LLC
  • Assignee: INTELLECTUAL VENTURES ASSETS 99 LLC
  • Correspondent: not surfaced
  • Context: Transfer into an Intellectual Ventures asset-holding LLC (~11 years after the 2007 divestiture).

• 2019-03-11 (executed) / recorded 2019-03-11 — Reel not surfaced

  • Conveyance: Assignment of interest
  • Assignor: INTELLECTUAL VENTURES ASSETS 99 LLC
  • Assignee: STEEPHILL TECHNOLOGIES LLC
  • Correspondent: not surfaced
  • Context: Transfer out of the IV entity to a second holding LLC — 47 days after the IV acquisition.

• 2019-05-13 (executed) / recorded 2019-05-13 — Reel not surfaced

  • Conveyance: Assignment of interest
  • Assignor: STEEPHILL TECHNOLOGIES LLC
  • Assignee: CEDAR LANE TECHNOLOGIES INC.
  • Correspondent: not surfaced
  • Context: Transfer to the asserting entity — the terminal owner of record.

• 2022-09-29 (recorded) — Reel not surfaced

  • Conveyance: Release by Secured Party
  • Assignor: HSBC BANK USA, NATIONAL ASSOCIATION
  • Assignee: MOOG INC.
  • Correspondent: not surfaced
  • Context: Anomalous / securitization-related. This reads as a collateral release, not a transfer of the '790 patent to Moog. It is almost certainly a data-artifact of the shared/adjacent reel-frame block in which Google Patents aggregates legal events, or an HSBC–secured-lender recording that got associated with this patent's event set. I could find no evidence Moog Inc. holds or ever held this patent, and I am not treating this as an ownership link. Per the "interpret identifiers literally" rule I am reporting it exactly as recorded and labelling it as unexplained rather than auto-correcting it away.

Recording-block observation (relevant to the correspondent signal): the two 2007 recordings are adjacent frames on a single reel (020243) four days apart — the classic signature of one filing agent running a name-change/corrective pair for a single transaction. That shows a common recorder for the 2007 pair, but does not disclose the attorney's identity.

Timeline diagram

timeline
    title Ownership of US 6972790
    2000 : Suska assigns to Symagery Microsystems
    2005 : Symagery renamed Psion Teklogix Systems
    2007 : Assigned to Harusaki Technologies LLC
         : Corrective assignment on Reel 020243 Frame 0226
    2019 : Assigned to Intellectual Ventures Assets 99
         : Assigned to Steephill Technologies LLC 47 days later
         : Assigned to Cedar Lane Technologies Inc
    2019 : Earliest listed Cedar Lane litigation activity
    2022 : HSBC secured party release to Moog Inc

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT. The chain leaves the operating company at 2007-12-13 (Teklogix/Psion Teklogix → Harusaki Technologies, LLC) and never returns to an operating entity. Naming is not the basis for this call — the basis is the sequence: an auto-ID hardware maker's imaging IP is moved to an LLC with no apparent product line, which 11 years later (2019-01-23) feeds an Intellectual Ventures Assets 99 LLC, then Steephill Technologies LLC, then Cedar Lane Technologies Inc. Terminal assignee Cedar Lane is characterized as an NPE in the KIPO report (캐나다 소재, "NPE 여부: O").

2. Known asserter in the chain — PRESENT. Two separate hits:

• Intellectual Ventures Assets 99 LLC (2019-01-23) — an Intellectual Ventures asset-holding entity, i.e., a named NPE on the standard lists.
• Cedar Lane Technologies Inc. (2019-05-13) — appears in the Stanford NPE Litigation Database for this very patent (https://npe.law.stanford.edu/patent/6972790) under the asserter category "Acquired patents," with dozens of captioned suits (e.g., Cedar Lane v. Amazon.com, 1:20-cv-00415 W.D. Tex.; Cedar Lane v. ON Semiconductor, 1:20-cv-00414 W.D. Tex.; Cedar Lane v. Amlogic, 1:23-cv-01242 D. Del.).

3. Repeat correspondent across the chain — UNCLEAR / DATA GAP. I could not retrieve the correspondent-of-record for any link, so I cannot call recurrence. What I can say from what I have: the 2007 pair was recorded by a single agency on one reel (020243, adjacent frames); the 2019 trio was executed and recorded on the same day in each instance, which is the signature of a single coordinated recording agent, but the agent's name is not in the sources I reached. Do not treat this as established. Recommend a direct Assignment Center pull on the three 2019 reel/frames to capture the correspondent — this is the single highest-value missing datum for this chain.

4. Cascading transfers < 24 months — PRESENT (strong). Three consecutive assignments through chained LLCs inside ~3.7 months: 2019-01-23 (IV Assets 99) → 2019-03-11 (Steephill, 47 days) → 2019-05-13 (Cedar Lane, 63 days). Every leg was executed and recorded the same day, which is atypical of arm's-length asset sales and typical of a pre-arranged assertion chain.

5. Pre-litigation transfer — PRESENT (probable). Cedar Lane took title 2019-05-13. The patent's own docket list includes C.D. Cal. case 2:19-cv-06479, a 2019 Cedar Lane filing naming this patent — i.e., within roughly 2–6 months of the acquisition, inside the 6-month window. Corroborating later filings follow (W.D. Tex. 1:20-cv-00414/-00415 in 2020). Exact 2019 complaint date not verified, so I mark this present-but-probable, not confirmed-to-the-day.

6. Bankruptcy fire-sale — NOT PRESENT. No Chapter 7/11, receivership, or §363 sale is evidenced for Symagery, Psion Teklogix, or any intermediate. The 2007 transfer is a corporate divestiture, and I found no SEC filing describing it.

7. Privateering — PRESENT (as pattern, with an evidence caveat). Psion Teklogix, an operating auto-ID/handheld vendor, divested this CMOS-imager-interface IP to Harusaki Technologies, LLC in 2007, and that same chain later asserted the patent against Psion's competitors in the auto-ID/imaging space — ON Semiconductor, Motorola Solutions, NEXCOM, Openeye, Logipix, Domo Tactical. That is the privateering shape. Caveat: I did not retrieve an SEC filing or Patent Progress/EFF report explicitly tying Psion/Psion Teklogix to the later assertions, so the "on the operating company's behalf" element is inferential rather than documented.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain terminates at Cedar Lane Technologies Inc., an active plaintiff with litigation filed through at least late 2025. Nothing in the record shows RPX, AST, LOT, Unified Patents, or OIN taking title.

Verdict

NPE — high confidence.

Two independent strong signals plus a strong cascading-transfer signature, all grounded in recorded dates: (i) the 2007-12-13 (Reel 020243, corrected by the 2007-12-17 record at Reel 020243/0226) transfer out of Psion Teklogix into Harusaki Technologies, LLC, then into INTELLECTUAL VENTURES ASSETS 99 LLC on 2019-01-23 — a named NPE asset entity; and (ii) the 47-day and 63-day chained transfers of 2019-03-11 and 2019-05-13 landing the patent at Cedar Lane Technologies Inc., which is listed on the Stanford NPE Litigation Database for this patent as an "Acquired patents" asserter. The 2019-05-13 acquisition-to-first-suit interval and the 2021 Reolink/睿联数字 settlement (US$10,000 paid up front, per IPRdaily) confirm the patent is worked as a licensing/revenue asset, not a product.

Verification links:

• USPTO Assignment Center (search patent 6972790): https://assignmentcenter.uspto.gov/
• Google Patents legal events for this patent (basis for the 2019 and 2022 legs): https://patents.google.com/patent/US6972790B2/en
• Stanford NPE Litigation Database — https://npe.law.stanford.edu/patent/6972790

Open items to close this out properly (all are data gaps, not findings):

1. Pull the three 2019 reel/frames and the 2000 and 2005 reel/frames directly in Assignment Center to capture the correspondent of record — required before any call on signal #3.
2. Confirm the filing date of C.D. Cal. 2:19-cv-06479 to firm up signal #5.
3. Confirm whether Harusaki Technologies, LLC is an IV-affiliated vehicle (would elevate signal #1 and #7 from sequence-based to documented).

Consistency check against the prior sections: no contradiction found. The earlier summary's uncertainty #2 (IPR/PTAB status unverified) and #1 (no CAFC 2026 docket) are unaffected here — nothing in the assignment record bears on either. Its ownership-chain table matches the timeline above, with the single addition that the 2007 corrective assignment is now anchored to a concrete Reel 020243/Frame 0226.

I'll research US 6,972,790's cited prior art references. Let me run targeted searches.

Let me get the specific examiner-cited references from the patent's front page.

Let me look for the actual front-page reference list via the patent PDF and FreePatentsOnline.

Preliminary process note (read first)

I ran targeted queries against Google Patents (which mirrors the USPTO record), FreePatentsOnline-style sources, and patent-PDF repositories attempting to pull the front-page "References Cited" / "U.S. Patent Documents" list for US 6,972,790 B2. I was not able to retrieve the examiner-cited back-citation list within the allotted search steps, and the searches surfaced only the patent's forward citation tables and unrelated search reports. I am therefore reporting an explicit negative-with-uncertainty on the back-citation list rather than reconstructing it. Per your strict rule, I will not invent patent numbers, dates, or a § 102 mapping for references I could not verify.

The number is treated literally: 6972790 / US 6,972,790 B2. No similar numbers (e.g., 6,972,774; 8,537,242) are folded into the answer except where their distinct identity is stated.

1. Target record confirmed

This matches the previously generated bibliographic section; no contradiction found.

2. Citation categories — and why the distinction controls the § 102 answer

There are two different citation sets on a patent and they have opposite § 102 significance:

• Back-citations ("References Cited" on the front page) — the examiner/applicant-cited prior art. This is the set your task targets. Not retrieved (see § 5).
• Forward-citations ("Cited By" / "Families Citing this family") — later patents that cite '790 as prior art to them. These are, by definition, published after '790's priority date and therefore cannot anticipate '790 under § 102(a)/(b)/(e). They are useful for claim-scope insight only.

I report the forward-citations below with that caveat stated up front, so they are not mistaken for § 102 art.

3. Forward citations found (NOT § 102 prior art against '790)

From the Google Patents "Cited By (4)" table for US 6,972,790:

From the sibling Google Patents "Families Citing this family" table (also forward): e.g., US 7,312,821 B2; US 7,528,872 B2; US 2005/0168589 A1; JP 4502792 B2; US 8,049,293 B2; US 8,543,788 B2 (Aptina, "Conformal rolling buffer…"); US 7,884,871 B2 (Aptina, high-speed digital frame transfer); US 8,988,492 B2; CA 2329287 A1; and others.

§ 102 conclusion for this set: none qualifies as anticipating prior art against '790 — every member post-dates 2000-01-21. US 2006/0044435 A1 is the applicant's own later family member and is disqualified for § 102 against the parent for the same reason (and would at most raise a self-collision/ODP-style question, not anticipation).

4. Sibling / family references (distinct-identity flags, not § 102 art)

Do not conflate: US 6,972,774 (a different number appearing in an HTC-related list) and US 8,537,242 are separate, as established in the prior section; only 8,537,242 is a true family member.

5. The item you asked for most — explicitly not obtained

Back-citations ("References Cited — U.S. Patent Documents" on the '790 front page): NOT VERIFIED / NOT RETRIEVED.

• My targeted queries ("References Cited," examiner citations, likely classic CMOS-APS art such as Fossum/Merrill-era numbers) returned empty or unrelated results (EPO/PCT search reports for other applications, e.g., EP 0 995 406 and numerous PCT annexes — none of which is the '790 front page).
• One partial hit — a *CourtListener exhibit from Cedar Lane Technologies Inc. v. Fantasia Trading LLC, D. Del. 1:21-cv-01428* — contains the string "HOST INTERFACE FOR IMAGING ARRAYS … 6,721,008 B2 4/2004 Lee et al." That appears to be a litigation exhibit listing asserted patents/related numbers, not a verified examiner "References Cited" table. US 6,721,008 is not confirmed as a prior-art citation against '790, and I am not asserting it as one.

Because I cannot confirm even one back-citation with a citable source, I am not supplying a per-reference § 102 table, which would require fabricated data. That is the honest state of the record from the sources I could reach.

6. What the patent's own text establishes as admitted background (usable as "admitted prior art" framing)

Even without the front-page list, the specification's Background (col. 1; abstract; Definitions) affirmatively describes the state of the art, which a § 102 analysis can lean on as applicant-admitted prior art:

• CMOS image sensors using a photodiode per pixel with an amplification stage, outputting "video style" output — pixel data output at the same rate as sampled, with derived clocks output to synchronize the data (a "stream of synchronized pixel intensities comprising a video frame").
• The industry problem: a commercial microprocessor data interface uses address and control outputs plus data I/O for random access to memory, incompatible with the continuous sensor stream, necessitating external "glue logic" (interface circuitry with interrupts and pixel memory).

Elemental § 102 framework to slot references into once obtained (so the back-citation mapping can be done mechanically):

A reference anticipates only if it discloses all of these, arranged as claimed. The dual-rate decoupling (sensor-driven write / host-driven read) plus the fill-threshold alert is the likely novelty core; the single-die integration is the likely § 102 boundary for claim 15.

7. Caveats and recommended next steps

1. Back-citations unretrieved. Not a "no prior art" finding. The '790 front page almost certainly lists U.S. and possibly foreign patent documents; I could not confirm any of them.
2. § 102 vs. § 103. The task specifies § 102. Note that much CMOS-sensor/FIFO/DMA art of the 1990s would more likely support § 103 (obviousness) than clean § 102 anticipation of claims 1/15, precisely because the claimed combination is the point.
3. Expiry. With the listed adjusted expiration of 2023-08-01, the patent is expired; § 102 mapping is now of validity/FTO-interest value rather than live-infringement value.
4. To complete the requested table, retrieve the primary document directly: the USPTO PatentCenter/Patent Full-Text (patft) "References Cited" section for 6,972,790, or the front page of the granted PDF (patentimages). I could not reach either within this session's limits. If you supply that front-page list (or the patent PDF text), I will map each cited reference to claims 1–21 with dates and a § 102 rationale, using the element table in § 6.

Bottom line: I confirmed the target patent and its forward citation sets (none of which is § 102 art), identified the true family members (8,537,242; 09/759,397; CA 2329287), and explicitly flag that the examiner-applied "References Cited" back-citation list was not retrievable and has not been fabricated.

I'll research the prior art cited on this patent and in related proceedings before building the § 103 analysis.

Let me pull the full citation list and front-page references, plus any PTAB challenges to this patent.

Obviousness Analysis — US 6,972,790 B2 under 35 U.S.C. § 103

Current date: April 26, 2026. Builds on the prior bibliographic/enforcement sections; does not repeat them.

0. Evidence boundary — read this first

My §103 analysis is limited by what I could actually retrieve:

Consequence: everything below that maps a reference's disclosure to a claim limitation is an inference drawn from the reference's title/assignee/date combined with the ordinary state of the art in 1999–2000. Where I state what a reference "teaches," treat it as a hypothesis requiring verification against the reference's actual disclosure, not as a verified finding. I flag confidence per combination.

Contradiction flagged with the prior section: the earlier section said IPR/PTAB status was unverified and must not be read as a no-IPR finding. A new data point (PatSnap, https://www.patsnap.com/resources/blog/litigation/cedar-lane-technologies-v-dallmeier-electronic-usa-imaging-array-patents-patsnap/) lists "Validity challenges: None recorded." That weakens but does not resolve the earlier uncertainty — PatSnap's record is a litigation DB, not a PTAB docket. §7 below preserves the negative-with-uncertainty framing.

1. Legal framework applied (pre-AIA, correctly)

Filing date Dec 21, 2000; earliest priority Jan 21, 2000 (provisional 60/177,496). Because the application was filed before March 16, 2013, pre-AIA §§ 102/103 govern. The §102(b) critical date is Jan 21, 1999 (one year before the provisional, since §119(e) benefit counts for the §102(b) critical date).

• References published on/before Jan 21, 1999 → §102(b) art. Most of the cited list qualifies.
• JPH1155571A (Feb 26, 1999) and JPH11195777A (Jul 21, 1999) fall after that critical date → §102(a)/(e), not §102(b). Still prior art, but the distinction matters for any §102(b)-only theory. (This is a nuance the earlier sections did not address.)

Obviousness is evaluated under Graham v. John Deere (scope/content of art; differences; PHOSITA level; secondary considerations) as refined by KSR Int'l v. Teleflex (motivation may be supplied by design incentives, market pressure, "known technique used to improve similar devices," and "predictable variation").

2. Person having ordinary skill in the art (PHOSITA)

I would propose: a B.S. in electrical engineering or computer engineering plus 2–3 years of experience designing mixed-signal integrated circuits for camera/embedded imaging systems, or equivalent. This person knows, as of January 2000:

• CMOS active-pixel image sensors with on-chip row/column address generation and a master-clock-derived pixel/line clock ("video-style" output) — as the '790 specification itself concedes (col. 1).
• FIFO buffers with programmable fill-level thresholds, and using a threshold crossing to raise a processor interrupt or a DMA/bus-request.
• Bus arbitration and bus-mastering for DMA-capable peripherals.
• The economics of CMOS monolithic integration (fewer mask layers, higher yield vs. CCD) — again conceded in the '790 background.

3. Claim construction of the limitations that drive the analysis

4. Prior-art inventory (from the '790/'242 citation lists)

All dates from the Google Patents citation tables. §102 basis only where I could compute the critical date.

The Google Patents "Prior art keywords" for this record — data, interface, bus, memory, circuit — are themselves a useful signal: the examiner's art cluster was squarely in buffer + bus interface, i.e., the general-purpose computer-interface field, not a narrow image-sensor specialty.

5. The obviousness combinations

Combination 1 — Claim 1 (independent apparatus claim)

Primary: JPH07114510A (Hitachi, FIFO threshold control DMA method)
Secondary: any one of US5920343A (Sanyo), JPH11195777A (Toshiba), or US5786851A (Canon) for the image-sensor-with-clock/address-generator element.

Mapping (confidence: moderate-high for the concept, unverified as to literal disclosure):

Motivation to combine (KSR-compliant):

1. Design incentive from the art itself. '790's own background states the continuous sensor stream "is incompatible with the data interface of commercial microprocessors" absent "additional glue logic" (col. 1:46–53) that "diminish[es] the cost and integration advantages" of CMOS (col. 1:62–67). That is an admission of both the problem and the motivation.
2. Known technique for a known problem. Buffering a producer into a slower consumer with a fill threshold and an interrupt/DMA handshake was a routine, long-established data-communications technique (cf., e.g., the '242 citation context listing JPH05316427A, NEC, pairing sensor and processing device). Applying a FIFO-threshold-DMA front end to an image-sensor stream is "use of a known technique to improve a similar device in the same way."
3. Predictable variation. Rate-decoupling a fixed-rate producer from a variable-rate consumer by inserting a FIFO is the paradigm example of an art-recognized, predictable solution with no unexpected interaction among elements.

Combination 2 — The interrupt / bus-request / bus-arbitration dependents

Primary: Combination 1.
Secondary: US5581280A (Cirrus Logic) for host-interface/controller signaling, plus PHOSITA's ordinary knowledge of DMA bus-request/grant and interrupt lines.

The dependent claims split into two alternative notification channels:

• Interrupt to the processor — the simplest, most common peripheral-to-CPU alert; ubiquitous in microcontrollers of the era.
• Bus request to a bus arbitration unit — i.e., DMA/bus-mastering. Both were standard, interchangeable options a PHOSITA would select based on throughput vs. CPU-overhead tradeoffs. KSR expressly blesses selecting from a small set of known options with predictable results.

Adding a command decoder, configuration registers (FIFO limit, interrupt mask, interrupt register, output bus width), read control, and a bus command unit (as the specification describes and dependents claim) is the standard register model of any peripheral controller — there is no asserted unexpected behavior. Confidence: high for obviousness of the register block as an aggregation of known components.

Combination 3 — Claim 15 (single-die integrated imaging circuit) — the hard one

Primary: JPH1050966A (Sanyo, "Optical semiconductor integrated circuit") or JPH05326917A (Sanyo, "Optical semiconductor device") or JPH05316427A (NEC, "Solid-state image sensor and image processing semiconductor device")
Secondary: JPH07114510A (Hitachi FIFO/DMA) for the on-die interface, and JPH11195777A (Toshiba) for on-chip address generation.

Mapping:

• "imaging array of sensing pixels and an array address generator integrated on a die" → Toshiba / Sanyo / NEC single-chip sensor art. Confidence: moderate-high.
• "interface integrated on that same die" → Sanyo's optical semiconductor integrated circuit title and NEC's pairing of sensor + processing semiconductor device are the strongest citations; this is the limitation most needing verification against the references' actual disclosures. Confidence: moderate.
• "memory ... at a rate determined by the imaging array sensor" + "circuit ... to the data bus at a rate determined by the processing system" → Hitachi FIFO/DMA (Combination 1).

Motivation: The entire premise of the '790 background is that discrete glue logic erodes CMOS's cost/yield advantage. Given that express statement of purpose, integrating the buffering interface onto the sensor die is the single most predictable design choice available — a textbook KSR "design incentive" motivation, supported by contemporaneous single-chip optical-device art. Claim 15's on-die requirement is a structural siting choice, not a new function.

Combination 4 — Addressable-memory alternative (dependents)

Primary: Combination 1 with the buffer implemented as addressable RAM rather than a FIFO.
Support: JPH05250307A (Hitachi, information transfer device) and US5587953A (Hyundai, memory device).
Because claim 1 does not require a FIFO vel non — and the specification itself presents "FIFO buffer or an addressable memory" as interchangeable — swapping the buffer type is per se an obvious alternative. Confidence: high.

Combination 5 — On-die bus arbitration (dependent)

Combination 3 + ordinary SoC practice. Placing a bus arbiter on the same die as its requesting peripheral was standard integration practice, and the specification itself describes the arbiter as optionally on-die. Confidence: moderate-high.

6. Expectation of success and secondary considerations

Reasonable expectation of success: High. Every element (CMOS sensor with clock/address generation; FIFO with watermark; interrupt/DMA request; bus arbitration; register-mapped peripheral control) existed and was routinely combined in embedded systems by 1999. No two elements are asserted to interact in an unpredictable way; the combination yields only the expected result of the constituent parts.

Secondary considerations — none in evidence, and no nexus:

• No unexpected results are described in the specification for the combination as claimed; the specification frames the benefit (CPU can multi-task rather than service a raw stream, col. 5) as the expected consequence of buffering, which is precisely what Hitachi-style threshold/DMA buffering delivers.
• No long-felt-but-unmet need is established beyond the need the art itself already recognized and was addressing — the same need stated in '790's background was the design premise of the cited camera/sensor and FIFO/DMA references.
• No commercial-success/praise/copying evidence with nexus. Cedar Lane's licensing recoveries (e.g., the reported US$10,000 Reolink settlement noted in the previous section) are licensing outcomes against a broad portfolio, not marketplace success of a claimed invention attributable to the claim. Any commercial-success argument would fail the nexus requirement absent evidence tying sales to the '790 interface architecture rather than to ordinary camera/SoC features.

7. Counterarguments, vulnerabilities, and what would change this analysis

Arguments the patent owner would press (and my assessment):

1. "The claims require storing the clocking signals, which no reference teaches." The strongest available non-invalidity argument on claim 1's face — but it cuts the other way: an operative reading ("store data under the clock domain") leaves the limitation disclosed by any clocked FIFO; a literal reading ("store the clock waveform in the memory") makes the claim arguably inoperable/indefinite under §112(b). Net effect: a §112 vulnerability more than a §103 shield.
2. "No single reference teaches monolithic sensor+interface integration" for claim 15. This is the most defensible ground. It depends entirely on what JPH1050966A / JPH05326917A (Sanyo) and JPH05316427A (NEC) actually disclose — which I could not verify. If those references disclose only discrete sensor-plus-processing-device packages rather than true single-die co-integration, claim 15's "integrated on a die" element may survive a §103 challenge, and the analysis for claim 15 would need a different primary reference (or a §103 obviousness-by-design-choice argument relying on the admission in the '790 background).
3. "Hindsight reconstruction." Requires the challenger to show that the references themselves (not just the inventor's specification) point to combining buffered host-paced readout with a CMOS sensor. The '790 background admissions and the NEC reference pairing a solid-state image sensor with an image-processing semiconductor device are the best available answers; this is the most contestable link in Combination 1/3.
4. "Examiner allowed the claims over this art." True — but an allowance is not a validity holding, and the printed citation list does not tell us which references the examiner relied on or which limitations were the basis for allowance. The absence of any recorded validity challenge (PatSnap: "None recorded"; consistent with the earlier section's adjudicated-outcome review finding only procedural terminations) means these claims have never been tested — which cuts against, not for, confidence in their validity.

IPR status. My earlier section's "no-IPR" flag stands, now with one added data point (PatSnap "Validity challenges: None recorded") that is litigation-DB-derived, not a PTAB clearance. This remains a negative-with-uncertainty finding. Note also the '790 patent is Expired – Lifetime (listed adjusted expiration 2023-08-01), so IPR/invalidity review is largely moot prospectively, and the earlier-noted arithmetic anomaly on that expiration date persists.

8. Bottom line

Recommendation before any reliance: pull the full text/claims of JPH07114510A, JPH1050966A, JPH05326917A, JPH05316427A, JPH11195777A, and US5920343A, and retrieve the complete 39-item citation list (my retrieval truncated it, including an EP reference I could not identify). Without those, this is a §103 roadmap and hypothesis, not an invalidity opinion. Two items remain unresolved from earlier sections and are unremedied here: the '790 expiration-date arithmetic anomaly, and the unverified IPR/PTAB history.