Prior art — US Patent 6963505

Prior Art Analysis for U.S. Patent 6,963,505

Date of Analysis: April 26, 2026

Subject Patent: U.S. Patent 6,963,505, "Method, circuit and system for determining a reference voltage," filed October 29, 2003, and issued November 8, 2005.

Analyst: Senior U.S. Patent Analyst

This report details the most relevant prior art cited against U.S. Patent 6,963,505. The analysis focuses on the novelty of the patent's claims in light of pre-existing technologies, as mandated by 35 U.S.C. § 102. Each cited reference has been reviewed to determine its potential for anticipation of the claims of the '505 patent.

Key Findings:

The core invention of U.S. Patent 6,963,505 revolves around a method for selecting an optimal reference voltage for reading non-volatile memory (NVM) cells. This is achieved by reading a subset of memory cells with various possible reference levels, determining the read error rate for each level, and selecting the reference level that results in a relatively low error rate. This selected reference is then used for reading the broader memory array.

Several prior art references disclose concepts related to reference voltages and error checking in memory systems. The following analysis details the most pertinent of these.

Analysis of Cited Prior Art:

1. U.S. Patent 5,657,332: "Soft errors handling in EEPROM devices"

Full Citation: US Patent 5,657,332
Publication Date: August 12, 1997
Filing Date: May 20, 1992
Assignee: SanDisk Corporation
Brief Description: This patent describes a method for handling soft errors in EEPROM devices by using an error correction code (ECC). It discusses the concept of reading data with different reference voltages to recover data that is initially read with errors. The system can adjust read parameters to improve data recovery.
Potential Anticipation of Claims (35 U.S.C. § 102):
- Claim 1: This patent discloses using different reference levels to read memory cells and determining if errors occur, which is a foundational concept in claim 1 of the '505 patent. While it doesn't explicitly describe a systematic process of testing a set of possible reference levels to find the one with the lowest error rate for future use, it does teach the adjustment of read parameters in response to errors. This could be argued to anticipate the core concept of using error feedback to select a better reference level.
- Claims 29 & 30: The '332 patent's disclosure of using an adjusted reference voltage to subsequently read memory cells aligns with the broader method outlined in these claims.

2. U.S. Patent 5,805,500: "Circuit and method for generating a read reference signal for nonvolatile memory cells"

Full Citation: US Patent 5,805,500
Publication Date: September 8, 1998
Filing Date: June 18, 1997
Assignee: SGS-Thomson Microelectronics S.r.l.
Brief Description: This invention provides a circuit for generating a read reference signal for a non-volatile memory. It describes a system where the reference level can be adjusted to compensate for variations in the memory cells' threshold voltages due to factors like temperature and aging.
Potential Anticipation of Claims (35 U.S.C. § 102):
- Claim 1 & 13: The '500 patent discloses the concept of adjusting a reference level to improve read accuracy. While it doesn't explicitly mention determining a read error rate across multiple test levels, its teaching of adapting the reference level based on the memory's condition implies a feedback mechanism to optimize reading, which is central to the '505 patent's claims.
- Claim 22: This patent's description of a circuit that can be adapted to offset a reference voltage is relevant to the method of establishing a reference cell based on a selected reference voltage.

3. U.S. Patent 5,828,601: "Programmed reference"

Full Citation: US Patent 5,828,601
Publication Date: October 27, 1998
Filing Date: December 1, 1993
Assignee: Advanced Micro Devices, Inc.
Brief Description: This patent details a method for creating a reference cell in a non-volatile memory that has a threshold voltage distribution similar to the memory cells it is meant to reference. This is achieved by programming the reference cell in a similar manner to the data cells.
Potential Anticipation of Claims (35 U.S.C. § 102):
- Claim 13 & 26: The '601 patent's method of programming a reference cell to a specific threshold voltage is directly relevant to the concept of "establishing a reference cell based on said selected reference voltage" as claimed. While the '601 patent focuses on matching the reference cell's characteristics to the data cells rather than minimizing a read error rate, the fundamental step of programming a reference cell is disclosed.

4. U.S. Patent 6,044,019: "Non-volatile memory with improved sensing and method therefor"

Full Citation: US Patent 6,044,019
Publication Date: March 28, 2000
Filing Date: October 23, 1998
Assignee: SanDisk Corporation
Brief Description: This patent describes a method for improved sensing in a non-volatile memory by using a reference voltage that tracks changes in the memory cells' characteristics. It discloses using a reference cell that is subject to the same conditions as the data cells to generate a more accurate reference level. It also mentions adjusting the reference level to optimize read margins.
Potential Anticipation of Claims (35 U.S.C. § 102):
- Claim 1: The '019 patent teaches adjusting the reference level to improve read performance. The concept of optimizing read margins is closely related to minimizing read error rates. While it may not explicitly detail a process of iterating through a set of predefined reference levels and calculating error rates, the underlying principle of adjusting the reference for better accuracy is present.
- Claims 13 & 29: The method of using a tracking reference cell and adjusting its level provides a mechanism for establishing and operating with an optimized reference, as broadly claimed.

5. U.S. Patent 6,538,922: "Writable tracking cells"

Full Citation: US Patent 6,538,922 B1
Publication Date: March 25, 2003
Filing Date: September 27, 2000
Assignee: SanDisk Corporation
Brief Description: This patent discloses a system with writable tracking cells that are used to monitor the condition of the main memory cells. The information from these tracking cells can be used to adjust read parameters, including the reference voltage, to compensate for changes over time. It suggests that data from the tracking cells can be used to find an optimal read level.
Potential Anticipation of Claims (35 U.S.C. § 102):
- Claim 1 & 13: The '922 patent describes a very similar concept to the '505 patent. The use of tracking cells to gather information about the memory array's state and then adjusting the read reference voltage to an optimal level strongly aligns with the core claims of the '505 patent. The process of using this information to "find an optimum read level" can be seen as equivalent to selecting a reference level with a "relatively low read error rate."
- Claims 2, 3, 29, 31, 32: The detailed implementation of finding an optimal or improved read level, as suggested in the '922 patent, could be argued to anticipate the dependent claims that specify selecting the lowest error rate or a rate below a threshold.

6. U.S. Patent 6,678,192: "Error management for writable tracking storage units"

Full Citation: US Patent 6,678,192 B2
Publication Date: January 13, 2004
Filing Date: November 2, 2001
Assignee: SanDisk Corporation
Brief Description: This patent builds upon the concept of tracking cells and describes a system where the data read from these cells is analyzed for errors. The error information is then used to adjust the operating parameters of the memory, including the reference voltages, to improve data reliability.
Potential Anticipation of Claims (35 U.S.C. § 102):
- All Claims: This reference appears to be highly relevant. It explicitly links the concept of determining errors in a subset of cells (the tracking units) to the adjustment of reference voltages for the main memory array. This directly maps to the independent claims of the '505 patent. The disclosure of using error information to guide the selection of operating parameters is a direct anticipation of the claimed method.

Conclusion:

While several prior art patents disclose the general concepts of adjustable reference voltages and error detection in memory systems, U.S. Patents 6,538,922 and particularly 6,678,192, both assigned to SanDisk Corporation, present the most significant challenge to the novelty of the claims in U.S. Patent 6,963,505. These references describe a system where information from dedicated tracking cells, including error rates, is used to dynamically adjust the reference voltage for reading the main memory array. This process of feedback-based optimization of the read reference level appears to anticipate the core inventive concept of the '505 patent. A thorough claim-by-claim analysis would be required in a legal setting, but based on this initial review, a strong case for anticipation under 35 U.S.C. § 102 exists, especially from the '192 patent.