Obviousness

An analysis of U.S. Patent 6,963,505 under 35 U.S.C. § 103 for obviousness reveals potential vulnerabilities based on a combination of prior art references that were available at the time of the invention. A person having ordinary skill in the art of non-volatile memory (NVM) design and operation would have been motivated to combine existing technologies to arrive at the claimed invention, rendering its claims obvious.

The core of the invention in U.S. Patent 6,963,505 lies in a method for selecting an optimal reference voltage for reading NVM cells by testing a plurality of reference levels, determining a read error rate for each, and selecting the level with a relatively low error rate. This addresses the problem of threshold voltage drift in NVM cells, which can lead to read errors.

An obviousness rejection of the claims of the '505 patent can be constructed by combining the teachings of prior art that address an iterative approach to finding optimal read parameters with a well-established understanding of error detection methods in memory systems.

For instance, the combination of U.S. Patent 5,172,338 (to Mehrotra et al.), which discloses a multi-state EEPROM system that uses multiple read and verify levels, and the common practice of using error detection codes (like parity bits or more complex ECC) as documented in various industry standards and publications, would render the claims of the '505 patent obvious.

Analysis of Prior Art and Motivation to Combine:

• U.S. Patent 5,172,338 (Mehrotra et al.): This patent describes a method for storing multiple bits per memory cell by programming the cell to one of several distinct threshold voltage levels. To accurately read these levels, Mehrotra et al. teach the use of multiple reference voltages to distinguish between the states. This establishes the principle of using a set of possible reference levels to read memory cells. A person of ordinary skill in the art would understand from Mehrotra et al. that to accurately read data from a memory cell, especially one with multiple states, a precise reference voltage is crucial.

• Standard Error Detection Techniques: At the time of the '505 invention, the use of error detection codes (EDC) and error correction codes (ECC) in memory systems was a widespread and fundamental practice. These techniques, which involve storing redundant data (such as parity bits, checksums, or more complex codes) alongside the actual data, were used to detect and sometimes correct errors that occurred during data storage and retrieval. This knowledge was part of the common general knowledge of a person skilled in the art of memory systems design.

Motivation to Combine:

A person of ordinary skill in the art, faced with the problem of read errors in NVM due to threshold voltage drift as acknowledged in the background of the '505 patent, would be motivated to combine the teachings of Mehrotra et al. with standard error detection techniques.

The motivation would arise from the need to improve read reliability. Mehrotra et al. provide a framework of using multiple reference levels. The problem then becomes selecting the best reference level from this set, especially as cell characteristics change over time. The most direct and logical way to quantify the "best" level is to measure which one results in the fewest errors.

A skilled artisan would logically turn to the well-established field of error detection to make this measurement. By writing a known data pattern with its corresponding error detection code to a set of memory cells and then reading that data back using each of the possible reference levels from Mehrotra et al., one could easily count the number of errors produced by each reference level. The reference level that yields the lowest error count would naturally be selected as the optimal one for current operating conditions.

This combination of an iterative read process with multiple reference levels (as suggested by the spirit of Mehrotra et al.) and the use of a quantitative error rate as the selection metric (a straightforward application of known error detection principles) directly arrives at the core inventive concept of the '505 patent. The invention claimed in the '505 patent would therefore have been an obvious design choice and a natural progression of existing technologies to a person of ordinary skill in the art seeking to improve the reliability of NVM reads.

Conclusion:

The claims of U.S. Patent 6,963,505 are likely obvious under 35 U.S.C. § 103 in light of the combination of prior art teaching the use of multiple reference levels for reading multi-state memory cells and the common knowledge of employing error detection codes to identify read errors. The motivation to combine these teachings would have been the clear and pressing need to improve the accuracy of data reads in non-volatile memory systems, a fundamental goal for any memory system designer at the time. The solution presented in the '505 patent represents a predictable application of known techniques to solve a known problem.