Derivative works

Defensive Disclosure: Method, Circuit, and System for Determining a Reference Voltage

Publication Date: May 13, 2026
Assignee: Defensive Publications Inc.
Reference Patent: US 6,963,505 B2

Introduction: This document discloses a plurality of methods, systems, and applications that build upon the core teachings of US Patent 6,963,505. The purpose of this disclosure is to place these concepts in the public domain, thereby establishing prior art against subsequent patent applications for trivial or obvious improvements. The following disclosures are intended to be enabling for a person of ordinary skill in the art of semiconductor memory design, testing, and fabrication.

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Core Technology Synopsis (Based on US 6,963,505)

The foundational patent describes a method for optimizing the reference voltage used for reading data from non-volatile memory (NVM) cells, particularly multi-level cells (MLCs). The core process involves:

1. Reading a subset of memory cells using multiple, slightly different "test" reference voltage levels.
2. Calculating a read error rate for each test reference level.
3. Selecting the reference level that produces the lowest error rate.
4. Using this optimized reference level for subsequent read operations on the main memory array, or to program a new set of operating reference cells.

This technique compensates for threshold voltage drift in NVM cells over time and with use, a critical issue for data integrity in flash memory.

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Derivative Disclosures

I. Variations on Core Claim 1: A method of selecting a reference level... comprising: using each of said possible reference levels to read a set of cells... determining a read error rate... and selecting a reference level... whose read error rate is relatively low.

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Axis 1: Material & Component Substitution

1.1. Graphene-Based Sensing Transistors:

• Enabling Description: The sense amplifier circuit (as in Fig. 4, element 414) is fabricated using graphene field-effect transistors (GFETs) instead of traditional CMOS-based transistors. The high carrier mobility and atomic-scale thickness of graphene allow for ultra-sensitive detection of minute current variations from the memory cell, enabling the differentiation of much finer reference voltage steps. The GFETs are arranged in a differential amplifier configuration, where one input is connected to the memory cell's bit line and the other to the output of the selected test reference cell. The resulting output provides a more precise error signal, allowing for the selection of an optimal reference voltage with higher resolution than achievable with silicon-based sense amplifiers.
• Mermaid Diagram:

  graph TD
      subgraph GFET Sense Amplifier
          A[Memory Cell Bitline] --> GFET1(GFET T1);
          B[Test Reference Cell Output] --> GFET2(GFET T2);
          GFET1 --> C{Differential Stage};
          GFET2 --> C;
          C --> D[Output to Controller];
      end
      Controller(Controller 410) -- Selects --> B;
      D --> Controller;
      Controller -- Analyzes Error Rate --> E(Error Rate Table 416);
  

1.2. Phase-Change Memory (PCM) Reference Cells:

• Enabling Description: The test reference cells (Fig. 4, elements 432, 434, 436) are constructed from Phase-Change Materials like Ge2Sb2Te5 (GST) instead of standard floating-gate transistors. The resistance of a PCM cell can be finely tuned by controlling the degree of amorphization or crystallization induced by programming pulses. A digital-to-analog converter (DAC) provides precise, stepped voltage pulses to the PCM reference cells, programming them to a wide spectrum of resistance values. These resistance values directly correspond to the test reference levels. This substitution allows for a non-volatile and highly granular set of reference levels that are less susceptible to the charge leakage that affects traditional floating-gate reference cells.
• Mermaid Diagram:

  sequenceDiagram
      participant Controller
      participant DAC
      participant PCM_Ref_Cell as PCM Reference Cell
      Controller->>DAC: Set Voltage Level 'V_n'
      DAC->>PCM_Ref_Cell: Apply Programming Pulse
      PCM_Ref_Cell->>PCM_Ref_Cell: Resistance set to R(V_n)
      Controller->>Sense_Amplifier: Compare Memory Cell to PCM_Ref_Cell
  

1.3. Ferroelectric RAM (FeRAM) for Error Count Storage:

• Enabling Description: The error rate table (Fig. 4, element 416) is implemented using a small array of Ferroelectric RAM (FeRAM) cells. FeRAM offers fast, low-power write operations and high endurance. As the controller calculates the error rate for each test reference voltage, it directly writes the binary count to the FeRAM array. This is more efficient than writing to the main NVM block, which would incur higher latency and power consumption. The FeRAM's non-volatility ensures the error rate data persists across power cycles.
• Mermaid Diagram:

  classDiagram
  class Controller410 {
    +calculateErrorRate()
    +recordErrorRate()
  }
  class ErrorRateTable416_FeRAM {
    -feRAM_Array: byte[]
    +writeErrorCount(address, count)
    +readErrorCount(address): count
  }
  Controller410 --|> ErrorRateTable416_FeRAM : records to
  

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Axis 2: Operational Parameter Expansion

2.1. Cryogenic Temperature Operation for Quantum Computing Readout:

• Enabling Description: The entire reference voltage selection system is operated within a dilution refrigerator at temperatures below 100 millikelvin, designed for controlling and reading out superconducting qubits. At these temperatures, the threshold voltage distributions of the NVM cells (now silicon-germanium heterostructures) become extremely narrow. The reference voltage determination method is used to dynamically calibrate the readout reference for each qubit's associated control transistor. The test reference levels are generated with microvolt precision. The error rate calculation is based on the fidelity of qubit state measurement (distinguishing |0⟩ from |1⟩), with the optimal reference minimizing state misidentification.
• Mermaid Diagram:

  graph TD
      subgraph Dilution Refrigerator (<100mK)
          A(Qubit) --> B(Control Transistor);
          B --> C{Sense Amplifier};
          D(Cryo-DAC) -- generates test V_ref --> E(Reference Cell);
          E --> C;
          C --> F(Cryo-Controller);
          F -- calculates qubit state fidelity --> G(Fidelity Table);
          F -- selects optimal V_ref --> D;
      end
  

2.2. High-Frequency Operation for RF Signal Processing:

• Enabling Description: The method is adapted for an analog NVM array used to store filter coefficients for a high-frequency (GHz range) RF signal processor. The "read" operation is a continuous signal comparison, not a discrete data read. The "error rate" is quantified by the Signal-to-Noise Ratio (SNR) or Error Vector Magnitude (EVM) of the processed RF output signal. The controller sweeps the reference levels (which are now DC bias points for the analog memory cells) and uses a feedback loop from an RF power meter or vector signal analyzer to determine which reference bias point results in the highest output SNR. This optimal bias is then locked in for device operation.
• Mermaid Diagram:

  flowchart LR
      subgraph RF_Processor
          Input(RF Input Signal) --> Analog_NVM(Analog NVM Filter)
          Analog_NVM -- V_bias --> Controller
          Analog_NVM --> Output(Filtered RF Output)
      end
      subgraph Feedback_Loop
          Output --> VSA(Vector Signal Analyzer)
          VSA -- measures EVM/SNR --> Controller(Controller)
          Controller -- adjusts --> Test_Bias_Generator(Test Bias Generator)
          Test_Bias_Generator --> Controller
      end
      Controller -- Selects V_bias_optimal --> Analog_NVM
  

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Axis 3: Cross-Domain Application

3.1. Aerospace: Adaptive Sensor Calibration in Hypersonic Vehicles:

• Enabling Description: Strain gauges and temperature sensors embedded in the airframe of a hypersonic vehicle are subject to extreme material stress and thermal drift. Each sensor's output is digitized by an ADC whose reference voltage is provided by an NVM-based reference cell array. During pre-flight checks and in-flight cooldown periods, a known calibration signal (e.g., zero strain) is applied. The reference voltage selection method is then executed. The controller reads the sensor's digital output using a range of reference voltages. The "error rate" is defined as the deviation from the expected digital output for the known calibration signal. The reference voltage that minimizes this deviation is selected, effectively re-calibrating the sensor's ADC in real-time to compensate for drift caused by extreme operational conditions.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> PreFlight_Calibration
      PreFlight_Calibration: Apply zero-strain signal
      PreFlight_Calibration: Run V_ref optimization loop
      PreFlight_Calibration: Store V_ref_optimal
      PreFlight_Calibration --> InFlight_Operation: Lock V_ref
      InFlight_Operation: Monitor sensor data
      InFlight_Operation --> Cooldown_Recalibration: Detect cooldown phase
      Cooldown_Recalibration: Re-run V_ref optimization
      Cooldown_Recalibration --> InFlight_Operation: Update V_ref
  

3.2. AgTech: Soil Nutrient Sensor Self-Correction:

• Enabling Description: An in-situ soil sensor array measures levels of nitrates, phosphates, and potassium (NPK). The ion-selective electrodes used for sensing are prone to biofouling and calibration drift over time. The sensor node includes a microcontroller and a small NVM. Periodically (e.g., nightly), the sensor performs a self-test by switching its input to a set of internal, stable chemical reference solutions. It then executes the reference voltage selection algorithm. It reads the output for the known reference solution using various ADC reference voltages. The "error" is the difference between the measured value and the known concentration. The algorithm finds the reference voltage that minimizes this error, effectively compensating for sensor drift without requiring manual recalibration in the field.
• Mermaid Diagram:

  sequenceDiagram
      participant Scheduler
      participant Sensor_Mux as Sensor Multiplexer
      participant ADC
      participant Controller
      Scheduler->>Sensor_Mux: Switch to Reference Solution
      loop For each Test V_ref
          Controller->>ADC: Set Reference Voltage
          Sensor_Mux->>ADC: Provide Signal
          ADC->>Controller: Send Digital Reading
          Controller->>Controller: Calculate Deviation from Known Value
      end
      Controller->>Controller: Select V_ref with min deviation
      Controller->>ADC: Lock Optimal V_ref
      Scheduler->>Sensor_Mux: Switch back to Soil Probes
  

3.3. Consumer Electronics: Battery State-of-Charge (SoC) Estimation Refinement:

• Enabling Description: A battery management system (BMS) in a smartphone or laptop uses an NVM to store its aging model parameters. The "coulomb counting" method for SoC estimation suffers from cumulative error. The disclosed method is used to correct this drift. A "subset of cells" is a set of known SoC data points (e.g., a fully charged state, a 50% discharged state) recorded during manufacturing test. Periodically, when the battery reaches one of these known states (e.g., upon reaching 100% charge), the BMS controller reads a cell representing the coulomb count using different reference voltages. The "error rate" is the discrepancy between the coulomb counter's reading and the known ground-truth SoC. The controller selects the reference voltage that minimizes this error, effectively recalibrating the SoC "reader" to account for battery aging and temperature effects.
• Mermaid Diagram:

  graph TD
      A[Battery Cell] -- Voltage/Current --> B(Coulomb Counter);
      B --> C{SoC Estimator};
      D(NVM Aging Model) -- V_ref --> C;
      C -- Estimated SoC --> E(System);
      F(Ground Truth Event: e.g., Full Charge Detected) --> G(Controller);
      G -- Initiates Calibration --> H(V_ref Test Module);
      H -- Tries V_ref(n) --> D;
      C -- Test SoC --> G;
      G -- Compares Test SoC with Ground Truth --> G;
      G -- Selects V_ref_optimal --> D;
  

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Axis 4: Integration with Emerging Tech

4.1. AI-Driven Predictive Reference Voltage Selection:

• Enabling Description: The controller (Fig. 4, 410) is replaced with a small, edge-based neural network (NN) processor. This NN is trained on historical data of temperature, program/erase cycles, and the corresponding optimal reference voltages determined by the original method. Instead of exhaustively testing all reference levels, the NN takes current operating parameters (temperature, cycle count) as input and predicts a smaller, high-probability range of optimal reference voltages to test. This significantly reduces the time and power required for calibration. The system still performs the error rate check on the predicted subset to validate the NN's output and provide new data for continuous, on-device learning.
• Mermaid Diagram:

  flowchart TD
      A[Temperature Sensor] --> D{NN Processor};
      B[P/E Cycle Counter] --> D;
      C[Time-since-last-program] --> D;
      D -- Predicts --> E(Small Set of Test V_refs);
      E --> F(Test & Error Check Module);
      G(Subset of NVM Cells) --> F;
      F -- Validates & Finds V_ref_optimal --> H(Operational V_ref);
      F -- (V_in, V_out_optimal) --> I(NN Training Feedback Loop);
      I --> D;
  

4.2. IoT-Enabled Fleet-Wide Drift Monitoring:

• Enabling Description: Each NVM device in a large-scale IoT deployment (e.g., a fleet of autonomous vehicles) periodically runs the reference voltage optimization process. The determined optimal reference voltage, along with device ID, temperature, and cycle count, is transmitted to a central cloud server. This server aggregates the data from the entire fleet, creating a real-time map of memory drift characteristics under various real-world conditions. This aggregated data can be used to predict failures, schedule preventative maintenance, and push firmware updates that proactively adjust the range of test reference voltages for all devices in the fleet, improving overall system reliability.
• Mermaid Diagram:

  sequenceDiagram
      participant IoT_Device
      participant Cloud_Server
      participant Analytics_Engine
      loop Periodically
          IoT_Device->>IoT_Device: Run V_ref Optimization
          IoT_Device->>Cloud_Server: Send {DeviceID, V_ref_optimal, Temp, Cycles}
      end
      Cloud_Server->>Analytics_Engine: Aggregate Fleet Data
      Analytics_Engine->>Analytics_Engine: Analyze Drift Trends
      Analytics_Engine->>Cloud_Server: Generate New V_ref Test Ranges
      Cloud_Server->>IoT_Device: Push Firmware Update
  

4.3. Blockchain for Reference Cell Provenance:

• Enabling Description: For high-security applications (e.g., military or financial hardware), the manufacturing and initial calibration data of the reference cells is recorded on a private blockchain. During the initial factory test, the optimal reference voltage for a "golden" data pattern is determined and its value, along with the test conditions and a timestamp, is stored as a transaction in a block associated with the chip's unique ID. In the field, if the device needs to prove its data integrity, it can re-run the calibration and the resulting optimal reference can be cryptographically checked against the immutable record on the blockchain. This provides a verifiable audit trail for the memory's physical state, preventing tampering with reference levels.
• Mermaid Diagram:

  graph TD
      subgraph Factory
          A[Chip Manufacturing] --> B(Initial Calibration);
          B -- {ChipID, V_ref_initial, Test_Pattern, Timestamp} --> C(Create Transaction);
          C --> D{Add to Blockchain};
      end
      subgraph Field_Operation
          E[Device Power-On Self-Test] --> F(Run V_ref Optimization);
          F -- V_ref_current --> G(Verification Module);
          D -- query with ChipID --> G;
          G -- Compares V_ref_current with V_ref_initial --> H(Integrity Status);
      end
  

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Axis 5: The "Inverse" or Failure Mode

5.1. Graceful Degradation to Binary Mode:

• Enabling Description: In a multi-level cell (MLC) memory, if the reference voltage optimization process fails to find any reference level that produces an error rate below a critical threshold (e.g., the error correction code limit is exceeded), the controller triggers a "safe mode." In this mode, the memory logically reconfigures itself to operate as a single-level cell (SLC) device. It collapses the four MLC levels (e.g., '11', '10', '01', '00') into two SLC levels ('1' and '0'). This drastically widens the voltage margin between states, making the data readable even with significant threshold voltage drift, albeit at a reduced storage capacity. The reference voltage is set to a fixed level midway between the new, wider SLC distributions. This allows the device to remain functional for critical data retrieval even after severe degradation.
• Mermaid Diagram:

  stateDiagram-v2
      state "MLC Operation (4-Level)" as MLC
      state "SLC Operation (2-Level)" as SLC
  
      [*] --> MLC
      MLC --> MLC: V_ref optimization successful
      MLC --> SLC: Error rate > Critical Threshold
      note right of MLC
          Capacity = N
          Reference voltage is dynamic.
      end note
      SLC --> [*]: Device Failure
      note right of SLC
          Capacity = N / 2
          Reference voltage is fixed.
          Critical data can be retrieved.
      end note
  

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II. Combination Prior Art with Open-Source Standards

1. Combination with the RISC-V ISA:

• Enabling Description: A custom instruction is added to the open-source RISC-V instruction set architecture (ISA) specifically to execute the reference voltage optimization process. The instruction, VREF.OPT rd, rs1, rs2, takes the starting memory address of the test subset (rs1) and the address of a configuration block (rs2) as inputs. The configuration block specifies the range and step of test voltages. The instruction triggers a hardware state machine (a co-processor) that performs the read/error-check loop defined in US 6,963,505. Upon completion, the optimal reference voltage value is written to the destination register (rd). This offloads the entire process from the main CPU cores, allowing for a standardized, low-overhead method of memory calibration on any RISC-V compliant system.

2. Combination with the JTAG (IEEE 1149.1) Standard:

• Enabling Description: The reference voltage determination circuitry is integrated into the JTAG Boundary-Scan architecture of the chip. A new public instruction, CAL_VREF, is added to the device's Boundary Scan Description Language (BSDL) file. When this instruction is loaded into the JTAG instruction register, the Test Access Port (TAP) controller re-purposes the scan chain to control the reference voltage selection logic. The TDI pin is used to serially load the test voltage parameters, and the TDO pin is used to shift out the resulting error rates or the final optimal voltage. This allows manufacturing test equipment and in-field diagnostic tools to non-intrusively trigger and monitor the memory calibration process using a ubiquitous, standardized hardware interface.

3. Combination with the Universal Flash Storage (UFS) Protocol:

• Enabling Description: A new vendor-specific command is defined within the open UFS protocol standard to manage the reference voltage calibration. A VREF_CALIBRATE command, sent from the host system to the UFS device, initiates the process. The command's arguments specify the logical block addresses (LBAs) to use for the test subset and whether to run a quick or exhaustive search. The UFS device controller performs the optimization internally and returns a status code and the new optimal reference voltage in the command's response UPIU (Unit Protocol Information Unit). This integrates the physical layer optimization of the NAND flash directly into the high-level storage protocol, allowing the host operating system or file system to intelligently request memory recalibration based on performance metrics or predicted workload.