US 6946371

I'll search for authoritative information on this patent number.

Let me run more targeted searches for court dockets and the patent record.

Let me check for any 2025–2026 Federal Circuit activity and confirm litigation history.

US Patent 6,946,371 B2 — Analyst Summary

Scope note on sources: I was able to retrieve the patent's own front‑page/full text (Google Patents and the USPTO‑hosted PDF at patentimages.storage.googleapis.com/.../US6946371.pdf) and litigation data. My searches for a CAFC 2026 docket involving this patent returned no results — see the uncertainty statement at the end. I did not locate any 2026 Federal Circuit activity, and I am not going to assert one exists.

Bibliographic data (from the patent document itself)

Abstract (verbatim)

"Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication."

(Note: the printed abstract contains a typographical error, rendering "facetless" as "faceltess." I have not corrected the identifier/title data elsewhere.)

Plain-language overview of the independent claim

Claim 1 (the sole independent claim) covers a method of fabricating a semiconductor structure, comprising four steps:

1. Provide a chamber — i.e., an epitaxial deposition reactor.
2. Provide a semiconductor substrate in the chamber, the substrate having a surface with a first portion and a second portion proximal to (adjacent to) the first portion.
3. Provide a gate stack disposed over the first portion, where the gate stack comprises a dielectric region — in practice, the gate plus its spacer/liner dielectric (e.g., SiO₂, Si₃N₄, or a two-layer SiO₂/Si₃N₄ spacer).
4. Selectively deposit an epitaxial layer of at least one semiconductor material on the second portion, adjacent to the gate stack, while in situ doping that epitaxial layer at a first predetermined level to substantially suppress facet formation, thereby forming a substantially facetless semiconductor region — with the chamber pressure during selective deposition being greater than about 5 Torr.

Why the claim is framed that way. The specification explains that selective epitaxial growth of raised source/drain regions normally forms facets — slanted, low-energy crystallographic planes — at the epi/dielectric interface near the spacer. Facets cause thinner epi at the spacer edge, which produces deeper dopant penetration during implant, deeper silicide penetration (potentially reaching buried oxide or the relaxed SiGe layer), and localized high-resistivity regions. The prior art (the Langdo MIT thesis) had suppressed faceting only by in‑situ n‑type doping in a UHVCVD system with SiO₂ sidewalls — which the patent characterizes as commercially impractical, incompatible with Si₃N₄ dielectrics, and incompatible with multilayer commercial spacers. The invention's asserted contribution is to achieve facetless growth in commercially available CVD reactors (LPCVD, APCVD, PECVD) by in‑situ doping at roughly 10¹⁷–10¹⁹ cm⁻³, rather than by tightly engineering spacer composition/geometry. The "> 5 Torr" limitation is the feature that distinguishes the claim from the UHVCVD prior art.

Representative dependent-claim subject matter (all narrower than claim 1): CVD reactor types (claims 2–3); source gas = precursor gas + carrier gas such as hydrogen (4–6); silicon precursors — silane, disilane, trisilane, dichlorosilane (7–8); germanium precursors — germane, digermane, GeCl₄, GeCl₂ (9–10); etchant such as HCl or Cl₂ for selectivity (11–12); dopants P, As, Sb, B and dopant gases phosphine, arsine, stibine, diborane (13–14); doping range 10¹⁷–10¹⁹ cm⁻³ (15); epi is Si and/or Ge (16); dielectric is silicon oxide and/or nitride, optionally a two‑layer spacer (17–18); substrate types including bulk Si, SOI with strained layer, and relaxed Si₁₋ₓGeₓ on Si with a strained Si layer, optionally with a graded SiGe layer or buried insulator (19–24); chamber temperature 300–900 °C, further 500–700 °C (25–26); growth rate > 1 nm/min (27); CMOS integration with NMOS and PMOS plus counter‑doping, with the facet‑suppressing in‑situ doping level not exceeding the counter‑doping level (28–30); metal silicide contact formation (31); (100) substrate surface orientation (32); spacer sidewall angle 60°–90° and alignment with <110> or <100> planes (33–35).

One drafting observation worth flagging: the Summary of the Invention describes "forming a dielectric region on the first portion of the substrate," whereas granted claim 1 instead recites "providing a gate stack … the gate stack comprising a dielectric region." Anyone comparing the specification's broad summary against the claim should note that the claim ties the dielectric to a gate stack rather than claiming a dielectric region standing alone.

Litigation / docket findings (and uncertainty)

• Google Patents/Unified Patents data for this patent lists two 2005 district-court cases: 2:05‑cv‑00449 (E.D. Tex.) and 1:05‑cv‑00682 (D. Del.). A retrieved Delaware opinion (AmberWave v. Intel, via the Harvard/CourtListener PDF) discusses the parties' dispute over "the '371 patent" alongside the '292 and '632 patents, confirming that US 6,946,371 was litigated in the mid‑2000s.
• I found no evidence of any 2026 Court of Appeals for the Federal Circuit docket involving US 6,946,371. My searches for Federal Circuit 2026 activity returned nothing on point. Given the patent is recorded as Expired – Lifetime with an adjusted expiration of July 2, 2023, a 2026 appeal would be unusual, but I cannot rule one out from the sources available to me.
• Confidence: High for all bibliographic data and claim text (taken directly from the patent document). Low/none for any 2026 CAFC proceeding — treat the absence of a 2026 docket as no result found, not as affirmative proof that none exists. I also could not independently open a live USPTO PatentCenter or PACER/CAFC docket in this session, so any current 2026 filing status should be verified directly at USPTO PatentCenter and the Federal Circuit's CM/ECF docket.

I'll research litigation involving US patent 6946371. Let me start with several targeted searches.

Initial searches returned nothing. Let me try more targeted queries.

Good — I found substantive results. Let me dig deeper into case details and other defendants.

Litigation Involving U.S. Patent No. 6,946,371 ("the '371 patent")

Important disambiguation note: The '371 patent here is U.S. 6,946,371 (AmberWave Systems, "Methods of fabricating semiconductor structures having epitaxially grown source and drain elements," issued Sept. 20, 2005). It is frequently confused with other "'371 patents" that appear in search results — e.g., Honeywell's U.S. 5,280,371 (LCD litigation) and a Nasdaq-related '371 patent in Nasdaq v. Miami International Holdings (D.N.J. 3:17-cv-06664). Those are not relevant and are excluded below.

Known litigation

All confirmed litigation over U.S. 6,946,371 was between AmberWave Systems Corp. (patent owner at the time; now assigned to TSMC) and Intel Corp., and arose from the parties' broader strained-silicon patent dispute in 2005. The '371 patent issued on Sept. 20, 2005 and immediately triggered a same-day "race to the courthouse."

Key procedural facts (grounded in court records)

• The same-day filings (Sept. 20, 2005): According to the Delaware court's Memorandum Order (Intel Corp. v. AmberWave Systems Corp., Judge Jordan), AmberWave left a '371 infringement complaint in a drop box at the E.D. Tex. courthouse at 5:50 a.m. CT, and Intel filed its DJ non-infringement complaint in D. Del. roughly two hours later at ~8:30 a.m. ET. (courtlistener opinion)
• Consolidation into Delaware: Intel moved to supplement its complaint (D.I. 30) to add a DJ claim on the '371 patent; Judge Jordan granted the motion, holding the Delaware case (05-301-KAJ) was the first-filed action and that it "makes no sense to burden the Eastern District of Texas with this third and latest version of the substantially overlapping disputes." (casemine summary; CourtListener)
• AmberWave's consolidated complaint asserted the '292, '632, '371, and '449 patents and sought a willfulness finding, injunction, and treble damages. (findforms: Second Amended and Supplemental Complaint)
• The '371 patent was confirmed as among the suits covered by the settlement. (Intel press release, Mar. 5, 2007)

Outcome

• Settlement / license (March 5, 2007): Intel and AmberWave announced they had "settled all patent infringement suits pending between them related to AmberWave Systems' strained silicon patent portfolio." Under the agreement, Intel received a license to all AmberWave patents and patent applications existing at the time or filed during a 10-year term, and Intel agreed to make license payments to AmberWave. All other terms are confidential. (Intel press release; CNET; EE Times; LA Times)
• No appellate (CAFC) decision on the '371 patent is known — the case ended at the district-court settlement stage before trial/judgment.
• The patent is "Expired – Lifetime" (expiration adjusted to July 2, 2023) and was assigned to Taiwan Semiconductor Manufacturing Company, Ltd. on Jan. 26, 2010 (from AmberWave Systems).

Official litigation docket references (from the patent record)

The patent's Google Patents family page lists two litigation matters for this family:

• E.D. Tex.: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A05-cv-00449
• D. Del.: https://portal.unifiedpatents.com/litigation/Delaware%20District%20Court/case/1%3A05-cv-00682
• Darts-ip "first worldwide family litigation," family ID 29736373.

Limitations / caveats

• The litigation I could verify concerns only the '371 patent's use in the AmberWave–Intel dispute. I did not find any separate suit (e.g., against Samsung, Fujitsu, Toshiba, AMD, or others) specifically asserting U.S. 6,946,371; AmberWave's suits against other parties involved different patents in the portfolio, and I could not complete verification within this session. If any such '371-specific suits exist, they are not confirmed here.
• Some docket-level details (e.g., the original 2005 filing date of the consolidated Delaware case 05-301, and precise disposition dates of the later-filed E.D. Tex./D. Del. cases numbers 4 and 5) are drawn from third-party docket aggregators (RPX Insight, Plainsite, CourtListener) rather than from a direct PACER pull, so treat those specific dates as reported, not independently verified.
• The related patents U.S. 7,122,449 and U.S. 7,439,164 are separate continuation patents in the same family — their litigation history is distinct from the '371 patent and is not addressed here.

I'll start by verifying the structured data against live sources, since the canonical block reports zero AIA trials but the patent has a litigation history that often correlates with PTAB filings.

Let me cross-check with targeted searches on the litigation track and any PTAB docket activity, since the 2005 district court cases are often precursors to AIA trials.

Let me run a final confirmation pass on possible ex parte reexamination or AIA trial filings, plus the outcome of the underlying Intel litigation.

Proceedings overview

Total AIA trial proceedings on file: 0. The structured block (§ "PTAB proceedings on file") — sourced from the USPTO Open Data Portal — reports that no AIA trial proceedings (IPR / PGR / CBM) exist for US 6,946,371, and my independent web searches of PTAB dockets, the PTO Litigation Center reports, and the open web surfaced no IPR, PGR, or CBM naming this patent. I also found no ex parte or inter partes reexamination of the '371 patent. Breakout by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom-line defensive posture: This is not a "hardened patent that survived IPRs" story and it is not a "claims are already dead" story — it is a no-PTAB-track-record story. The '371 patent has never been tested at the PTAB, so all 35 claims stand unadjudicated, and the burden of invalidating it has never been shouldered by anyone. Importantly, the patent expired on 2023-07-02 ("Expired - Lifetime," adjusted expiration). For a defendant receiving a demand letter today, that means the exposure is past damages only — but it also means there is no PTAB record to lean on and no petitioner estoppel working in your favor.

No AIA trial proceedings to itemize

Because the canonical list is empty and my searches corroborate it, there is no per-proceeding detail (petition grounds, institution decision, FWD, panel, appeal) to report. I will not invent proceeding numbers. What follows is the activity that does exist on the public record, correctly labeled so it is not mistaken for PTAB work.

Related, NON-PTAB activity (district court litigation — not AIA trials)

AmberWave Systems Corp. v. Intel Corp. — and its mirror declaratory-judgment actions — is the enforcement history, and it is pre-AIA, filed in 2005, seven years before IPR/PGR existed (AIA trials became available 2012-09-16). Do not confuse these with PTAB proceedings.

• Nature: Patent infringement (E.D. Tex.) and declaratory judgment of non-infringement (D. Del.). These are Article III district court cases, not Board trials.
• The '371-specific filings (all 2005-09-20):
  • AmberWave v. Intel, No. 2:05-cv-00449 (E.D. Tex., Marshall Div.) — infringement complaint on the '371 patent, filed the day it issued. (Google Patents litigation link)
  • Intel v. AmberWave, No. 1:05-cv-00682 (D. Del.) — Intel's DJ of non-infringement of the '371, filed ~2.5 hours after AmberWave dropped its complaint. (Google Patents litigation link)
• Panel / judge: The Delaware DJ action was before Judge Kent A. Jordan; the earlier E.D. Tex. case (on the '632 patent) was before Judge Leonard Davis. See the CourtListener memorandum order granting Intel leave to supplement its DJ complaint to add the '371: Intel Corp. v. AmberWave Systems Corp., 233 F.R.D. 416 (D. Del. 2005), https://www.courtlistener.com/opinion/[8759735](/patent/8759735)/intel-corp-v-amberwave-systems-corp/ (quoting the '371 as directed to "methods for fabricating semiconductor devices having substantially facet-less raised source and drain elements").
• Procedural events: The parallel E.D. Tex. '632 case (No. 2:05-cv-321) was transferred to D. Del. on 2005-11-01 under the first-to-file rule. The '371 cases were consolidated for handling in Delaware.
• Settlement / termination: Not confirmed from the sources I retrieved. Public reporting (EE Times, InformationWeek, 2005-09-29) describes the dispute as arising from failed license negotiations, and Intel reportedly alleged non-infringement; I could not verify a settlement date or terms, and any such terms would likely be confidential. I flag this as unverified rather than assert an outcome.
• Appeal: No Federal Circuit appeal of any '371 ruling found — consistent with there being no PTAB FWD to appeal and no confirmable final judgment.
• Defensive value: The 2005 litigation is of historical/original-assignee interest only. The patent is now held by Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC), which acquired it from AmberWave on 2010-01-26. A demand letter today comes from a well-capitalized, non-practicing-in-this-art owner, and the past Intel dispute gives no estoppel or issue-preclusion benefit to a new defendant.

Strategic summary

Claim status. Because no AIA trial ever reached a Final Written Decision — indeed none was ever instituted — none of claims 1–35 of US 6,946,371 has been canceled, narrowed, or held unpatentable by the PTAB. Treat the entire claim set, including independent claim 1 (selective epitaxial deposition with in-situ doping to suppress facet formation, chamber pressure > 5 Torr), as live but wholly untested. The three-member family — US 6,946,371, its continuation US 7,122,449 (from App. 11/103,681), and continuation US 7,439,164 (from App. 11/489,787) — shares the 2002-06-10 priority date and, per the structured data, all show "Expired - Lifetime." Any assertion you receive is necessarily about accrued past damages, not ongoing royalties.

Estoppel landscape. With no petitioner, there is zero § 315(e)(2) estoppel on this patent. Nothing bars you from raising any ground — § 102, § 103, or § 112 — in an IPR/PGR or in district court. That is the silver lining: you have the full prior-art field open. The flip side is that you also get none of the benefit of someone else having already mapped the art. Note that the Board can institute on an expired patent (the claims remain amendable/cancelable and past damages remain at stake), so a defensive IPR is theoretically available — but the cost/benefit is weak given expiration. A district-court § 101/§ 112 or invalidity defense, or a strong non-infringement theory on the "substantially facetless" / "pressure greater than about 5 Torr" limitations, is likely the more efficient path.

Pattern signals. No repeat petitioner, because there is no petitioner at all. The patent owner's enforcement profile is dormant and dated: its only public litigation over the '371 is a 2005–2006 Intel dispute inherited from AmberWave, filed the morning the patent issued (a classic race-to-the-courthouse posture). There is no defensive aggregator (Unified Patents or similar) in the chain on this patent, and no history of aggressive PTAB appeals by the patent owner. The combination — expired status, TSMC ownership, no AIA trial history, 2005-era enforcement — suggests low litigation heat, but you should not assume the claims are weak; they have simply never been challenged.

Recommended next steps

1. Confirm the null result before relying on it. Pull the patent's full PTAB record directly: search PTAB E2E (https://ptacts.uspto.gov) and the USPTO Patent Trial and Appeal Board Decisions page by patent number 6,946,371 and by application 10/458,544. I found no AIA trials, but you should independently verify — the structured source itself notes ODP ingest lag, so a very recent (post-ingest) filing is the one thing that could be missed.
2. Check the family, not just the '371. If a demand letter cites the '371, it may also cite US 7,122,449 and US 7,439,164. I found no PTAB proceedings on those either, but confirm each on PTAB E2E. Their status ("Expired - Lifetime") matters equally to your past-damages exposure.
3. Because there is no FWD to link or quote, do not build a defense around PTAB estoppel or canceled claims. Instead:
   • Attack the limitations that carried the 2005 case: the "in situ doping … to substantially suppress facet formation" limitation and the "pressure in the chamber … greater than about 5 Torr" limitation (claim 1) are the narrow points, and the Langdo thesis (MIT, 2001), WO 01/22482, and US 5,442,205 are the art of record that a defendant could start from.
   • Evaluate § 112 on the quantitative limits ("about 5 Torr," "about 10¹⁷ to about 10¹⁹ cm⁻³") and the functional "substantially facetless" language.
4. Verify the old-litigation disposition. Retrieve the D. Del. docket entries for Nos. 1:05-cv-00682 and the transferred 2:05-cv-321 (via PACER/CourtListener) to learn whether Intel and AmberWave settled, licensed, or dismissed the '371 claims — that history can reveal the patent owner's prior licensing position and any admissions, and it is the only real enforcement record that exists.
5. Treat the absence of PTAB activity as a signal, not a shield. An untested, expired, TSMC-owned patent with only 2005-era enforcement is a plausible target for a first-ever IPR if you are facing a meaningful damages demand — but weigh the near-term trial cost against the past-damages exposure and expiration before committing.

Caveats on sourcing: The claim-level outcome, panel, and FWD sections are intentionally empty because no proceeding reached those stages. All statements about the '371's substance and the Intel litigation are drawn from the patent text provided and the CourtListener/Court filings and 2005 press reports cited above; the settlement status of the 2005 cases and any reexamination history are not confirmed by the sources retrieved and are flagged as such.

I'll research the assignment record for this patent across the sources specified.

Assignment Record — US 6,946,371 B2

Source-retrieval caveat (read first): I was able to confirm the existence and content of the recorded assignment events for this patent from the authored Google Patents legal-events data supplied in the case file (which mirrors the USPTO Assignment Center record). I was not able to open the live Assignment Center / assignment.uspto.gov pages for 10/458,544 in this session, and my searches did not return the reel/frame numbers, the execution dates, or the correspondent of record for either conveyance. I am therefore not printing reel/frame values, because the operating rules forbid fabricating them. Every reel/frame and correspondent field below is marked not retrieved, not guessed. Verify at the Assignment Center search page: https://assignment.uspto.gov/patent/index.html (query: 6946371).

Inventors

Basis for the employer call: both inventors are named as assignors on the inventors→company conveyance recorded 2004‑04‑12 (assignee AMBERWAVE SYSTEMS CORPORATION), which is the standard employment/obligation assignment. The specification itself is the commercialization work of AmberWave: it repeatedly cites the Langdo MIT Ph.D. thesis, "Selective SiGe Nanostructures" (MIT, 2001), and the Langdo thesis is described in the spec as work performed in the context of AmberWave's development program. Langdo's thesis is dated 2001 and the application was filed 2003, consistent with a founder-era MIT-to-AmberWave technology pipeline.

Unusual patterns — one notable absence:

• There is no evidence of inventors departing the original assignee within 12 months of filing — the classic pre-fire-sale tell. In fact the opposite is true: Anthony J. Lochtefeld is still listed as an AmberWave inventor of record on AmberWave's later PCT application WO 2010/033813 A3 (filed 18 Sep 2009, published 25 Mar 2010, applicant AMBERWAVE SYSTEM CORPORATION, 13 Garabedian Drive, Salem, NH), i.e. he remained with the company ~6 years after the '371 filing. That is a continuity fact, not a churn fact.
• No inventor name changes, no certificate of correction for inventorship appears in the record.

Original assignee

AmberWave Systems Corporation (named on the front page; note the name variant flagged below), Salem, New Hampshire.

• Primary line of business: a materials-science R&D and IP-licensing company, not a chip manufacturer. Its own fact sheet describes it as "a materials research science company with an intellectual property (IP) business model," founded 1998 (as AmberWave LLC; per co-founder Eugene Fitzgerald, it "became AmberWave Systems Corporation in 1999"), holding "more than 150 patents issued and pending," with a 30,000 sq ft facility including a class‑10 clean room and state-of-the-art epitaxy/metrology equipment. So it did operate real facilities and employ engineers — it was non-manufacturing but not a passive shell.
• Did it ship a product embodying the claims? No — it licensed. Documented licensees/partners include Applied Materials (agreement announced 14 Dec 2004 to license AmberWave strained-silicon IP for the Applied Centura RP Epi system), and press reporting of work with AMD and UMC. Its revenue model was royalties.
• Funding/status: raised ~$60–91M from 3i, Adams Capital Management, Arch Venture Partners, The Hillman Company, and TeleSoft Partners; acquired Aonex Technologies, Inc. (Caltech-origin materials-integration IP). A patent-bibliometric study of TSMC's external technology acquisitions (IEEE, via Infona) reports that "most of the externally acquired patents at TSMC were acquired from assignors of NCR/MAGNACHIP SEMI, and AMBERWAVE SYS in 2006–2010", i.e. AmberWave's portfolio was absorbed by TSMC in that window.
• Current status: not confirmed in this session. I found no bankruptcy filing and no dissolution record for AmberWave. Its strained-silicon portfolio's transfer to TSMC (recorded 2010‑01‑26, below) is consistent with a portfolio wind-down/sale, but I will not assert dissolution without a source. Flagging explicitly as unverified.

Contradiction / name-variant flag: the previously generated section lists the assignee "as issued" as AmberWave Systems Corporation, while the Google Patents Original Assignee field reads "Amber Wave Systems Inc" (and the 2003‑06‑10 filing event reads "Amber Wave Systems Inc"). The recorded 2004 reassignment uses "AMBERWAVE SYSTEMS CORPORATION". This looks like a front-page transcription/spacing variant of one entity rather than a name change, but it is a discrepancy and should be verified against the Assignment Center record before any chain-of-title opinion relies on it.

Assignment timeline

Two recorded post-filing conveyances exist. (Filing itself — 2003‑06‑10 — is an application event, not an assignment, and is listed for chronology only.)

• 2003‑06‑10 — USPTO receives application 10/458,544; applicant of record Amber Wave Systems Inc / AmberWave. (Not an assignment.)

• Execution date: not retrieved / recorded 2004‑04‑12 — Reel not retrieved/not retrieved

  • Conveyance: Assignment of assignors' interest
  • Assignor: LANGDO, THOMAS A.; LOCHTEFELD, ANTHONY J.
  • Assignee: AMBERWAVE SYSTEMS CORPORATION
  • Correspondent: not retrieved — could not open the Assignment Center record in this session; no recurrence call can be made without it.
  • Context: Original employment/obligation assignment vesting title in the founding company — an ordinary in-house capture of inventor rights, not an acquisition or fire-sale.

• Execution date: not retrieved / recorded 2010‑01‑26 — Reel not retrieved/not retrieved

  • Conveyance: Assignment of assignors' interest (portfolio-level transfer; per the TSMC patent-acquisition study, executed as part of a multi-patent AmberWave→TSMC block in the 2006–2010 window)
  • Assignor: AMBERWAVE SYSTEMS CORPORATION
  • Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Correspondent: not retrieved — same limitation as above.
  • Context: Portfolio sale / strategic acquisition by a manufacturing foundry. Not a transfer-to-asserter and not a securitization: TSMC is an operating manufacturer that practices strained-silicon and raised source/drain process technology.

If the Assignment Center shows additional entries (e.g. a separate recordation for the continuations US 7,122,449 and US 7,439,164, or any security interest), they would not change the two-step structure above — the family-child applications are separate applications with their own reel/frame entries. I found none beyond the two events above.

Timeline diagram

timeline
    title Ownership of US 6946371
    2002 : Provisional filed by inventors
    2003 : Non-provisional application filed
    2004 : Inventors assign to AmberWave Systems
    2005 : AmberWave sues Intel in Texas
         : AmberWave sues Intel in Delaware
    2010 : AmberWave transfers portfolio to TSMC
    2023 : Patent term expires

NPE / troll-pattern signals

Verdict

Operating-company assertion

Justification (2–3 sentences): The complete recorded chain is inventors → AmberWave Systems Corporation (recorded 2004‑04‑12, inventors Langdo and Lochtefeld as assignors) → Taiwan Semiconductor Manufacturing Company, Ltd. (recorded 2010‑01‑26, AmberWave as assignor) — a two-step vertical chain from a VC-funded R&D/licensing company to an operating foundry, with no shell LLC, no listed NPE, and no cascading re-assignment anywhere in it. The only assertion in the record is AmberWave's own 2005 suits (E.D. Tex. 2:05‑cv‑00449; D. Del. 1:05‑cv‑00682, the latter discussing "the '371 patent"), brought by the entity that actually funded and staffed the R&D, months before — not in anticipation of — the 2010 transfer. Confidence: moderate-to-high on the chain structure (two events are well attested), low on reel/frame, execution dates, and correspondents, all of which must be confirmed at https://assignment.uspto.gov/patent/index.html before this is used for any title or standing analysis.

Honest limitation: I could not retrieve reel/frame numbers, execution dates, or the correspondent of record for either conveyance, so signals #3 (repeat correspondent) and parts of #1/#6 rest on incomplete data. If, on direct inspection of the Assignment Center records, the 2010 conveyance turns out to name a licensing intermediary rather than TSMC directly, or shares a correspondent with other AmberWave divestitures, the verdict should be revisited.

I'll research the prior art cited in US 6,946,371. Let me run targeted searches.

Let me dig deeper into the specific prior-art references cited on the face of this patent.

Let me try to retrieve the actual "References Cited" table directly from the patent record.

Prior Art for US 6,946,371 B2 — Analyst Findings

Scope note and an important sourcing limitation

I was asked to "look at each patent citation" on the face of US 6,946,371. I must be explicit about what I could and could not retrieve:

• The authoritative full text provided for this patent does not contain a "References Cited" / "Patent Citations" (backward-citation) table. The extracted record includes the forward citations ("Cited By (37)," "Families Citing this family (107)") but omits the front-page list of U.S. patent documents the examiner/applicant cited. So the canonical list of examiner-cited references is not available to me from the provided record.
• My searches for that list did not return it. Queries returned the citation tables of other, unrelated patents (e.g., US 8,927,378; US 11,110,049; WO 2011/115646) and citation tables of foreign search reports. I will not fabricate examiner citations.
• What I can do with high confidence is enumerate the prior art that the patent's own specification expressly identifies, discusses, and incorporates by reference — this is applicant-identified prior art and is the strongest grounded set available. I present that below, clearly labeled.

Critical labeling rule observed: I have not auto-corrected any identifier. Dates I could verify from retrieved sources are marked "verified"; dates I state from general knowledge but could not re-verify in this session are marked "unverified."

A. Prior art expressly identified in the specification of US 6,946,371

These references are named and characterized in the patent's own text (Background / Detailed Description). Because they are discussed in the specification, they are the references the examiner and applicant were working from.

A1. Langdo, "Selective SiGe Nanostructures," Ph.D. Thesis, MIT, 2001 ("Langdo thesis")

• Full citation: T. Langdo, Selective SiGe Nanostructures, Ph.D. Thesis, Massachusetts Institute of Technology, 2001. (Incorporated by reference in US 6,946,371.)
• Date: 2001 (published before the 2002-06-10 priority date). Verified as cited in the patent text.
• Description (per the patent): Demonstrates facetless selective epitaxial growth by in situ n-type doping of a silicon layer deposited adjacent to an RIE-etched SiO₂ spacer sidewall, in a UHVCVD (ultra-high-vacuum CVD) system. The patent's FIG. 3 is the XTEM image from this work, showing 1×10¹⁸ cm⁻³ n-type doped Si with Si₀.₉Ge₀.₁ marker layers following (100) planes (no facets).
• § 102 analysis — which claim(s) it could potentially anticipate:
  • This is the single most relevant reference to independent claim 1, because it discloses the core concept — "selectively depositing an epitaxial layer … while in situ doping the epitaxial layer … to substantially suppress facet formation."
  • However, it does NOT anticipate claim 1 as granted. Claim 1 requires "the pressure in the chamber during selective deposition … is greater than about 5 Torr." The Langdo thesis uses UHVCVD, whose operating pressures are orders of magnitude below 5 Torr. That limitation is the express distinguishing feature the patent relies on to avoid this reference.
  • It also uses SiO₂ sidewalls only (the patent says UHVCVD selective growth "is not possible with Si₃N₄ dielectric materials"), and the patent frames it as incompatible with the claimed "gate stack comprising a dielectric region" in a commercial CVD reactor.
  • Conclusion: Langdo is best characterized as the primary § 103 (obviousness) reference, not a § 102 anticipatory reference against claim 1. It would be anticipatory only to a hypothetical claim omitting the "> 5 Torr" limitation — which claim 1 does not omit.

A2. U.S. Pat. No. 5,442,205 — Brasen et al.

• Full citation: U.S. Patent No. 5,442,205, "Semiconductor Heterostructure Devices with Strained Semiconductor Layers" (Brasen, Daniel et al.). Family members: US 5,221,413; EP 0514018; JP 2792785 B2 (per the EPO family annex retrieved).
• Date: Issued August 15, 1995 (verified from the EPO/PCT family annex retrieved in search).
• Description (per the patent): One method of producing a strained Si device structure — a heterostructure with strained semiconductor layers.
• § 102 analysis:
  • Directed to substrate/heterostructure construction, not to the selective-epi-with-in-situ-doping method of claim 1. It does not anticipate claim 1 or any of claims 1–35's method steps.
  • It is potentially relevant background to dependent claims 20–24 (substrate definitions: strained semiconductor layer on insulator; relaxed Si₁₋ₓGeₓ with strained Si). Even there it is background art supporting the substrate the method is performed on — it discloses structures, not the claimed fabrication sequence — so it is not anticipatory.

A3. WO 01/22482 — "Method of Producing Relaxed Silicon Germanium Layers"

• Full citation: International Publication No. WO 01/22482, "Method of Producing Relaxed Silicon Germanium Layers."
• Date: Published 2001 (I believe approximately 2001-04-05, but I could not verify the exact publication date in this session — unverified). Predates the 2002-06-10 priority date either way.
• Description (per the patent): Epitaxial growth of a graded Si₁₋ₓGeₓ layer (gradient < 25% Ge/µm, final composition 0.1 < x < 1) using a GeₓH_yCl_z source gas at > 850 °C, then epitaxial growth of a semiconductor material on the graded layer — i.e., a method of making a relaxed SiGe virtual substrate.
• § 102 analysis:
  • Relates to forming the virtual substrate, not to the claim-1 selective epi / in-situ facet-suppressing doping step. Does not anticipate claims 1–35.
  • Potentially background to claim 22 / claim 23 (compositionally uniform relaxed Si₁₋ₓGeₓ layer; compositionally graded Si₁₋ₓGeₓ layer), again as structure/substrate art, not anticipation of the method.

A4. U.S. Pat. No. 6,107,653 — "Controlling Threading Dislocations in Ge on Si Using Graded GeSi Layers and Planarization"

• Full citation: U.S. Patent No. 6,107,653 (title as given in the specification).
• Date: Issued 2000 (I believe 2000-08-22, but the exact issue date was not verified in this session — unverified). Predates the priority date.
• Description (per the patent): Use of planarization (CMP) to improve the quality of graded SiGe (GeSi) layers by controlling threading dislocations.
• § 102 analysis:
  • Directed to planarization of SiGe graded layers — unrelated to selective epi and in-situ doping. Does not anticipate any of claims 1–35.

A5. Kummer et al., "Low Energy plasma enhanced chemical vapor deposition"

• Full citation: M. Kummer et al., "Low Energy plasma enhanced chemical vapor deposition," Materials Science & Engineering B, vol. B89 (2002), pp. 288–295.
• Date: 2002 (verified as cited in the patent text). Note: this reference is dated 2002; if its publication postdates the 2002-06-10 priority date, its prior-art effect would depend on the exact publication date — I could not verify the month (unverified).
• Description (per the patent): LEPECVD for forming a SiGe layer on bulk Si at high growth rates (0.6 µm/min) and low temperatures (500–750 °C).
• § 102 analysis:
  • Discloses low-temperature, high-rate SiGe deposition; potentially relevant background to claims 25–26 (temperature 300–900 °C; further 500–700 °C) and claim 27 (rate > 1 nm/min).
  • It does not disclose in-situ doping to suppress facet formation under claim 1's conditions, and it is not a selective-epi-in-a-gate-stack method. Does not anticipate claims 1–35; at most a § 103 secondary reference.

B. Prior art discussed in the specification without a formal citation

The specification describes two additional facetless/raised-source-drain approaches but gives no patent or literature citation, so these cannot be given a "full citation":

1. "Inverse pattern" selective growth — SiO₂ pillars with a Si field (as opposed to Si windows in a SiO₂ field). No citation given.
2. Undercut-liner-oxide + growth-under-Si₃N₄-spacer approach to suppress faceting by controlling multilayer spacer geometry/sidewall profile. No citation given. (The patent's stated advance is that its in-situ-doping approach avoids the need for this stringent geometry control.)

These are described as prior-art techniques and are the closest subject-matter neighbors to claim 1 — but without a citation, they cannot be pinned to a specific document from this record.

C. Candidate prior art I encountered but could NOT confirm is cited on this patent

During searching, one reference appeared that is topically on point but which I cannot confirm is a citation on the face of US 6,946,371, so I flag it rather than assert it:

• U.S. Pat. No. 5,861,059 (Suzuki) — selective growth of silicon epitaxial films using insulating-film masks and silane/disilane source gases, expressly addressing "facetting" at the film/insulating-mask sidewall and methods (low temperature, high disilane flow) to suppress it. This is highly relevant prior art topically. Unverified as a citation of the '371 patent — do not treat it as an examiner citation without confirming the front page.

I also confirmed the following forward references (documents that cite the '371, not prior art against it — § 102 does not apply):

• KR 10-0876831 B1 (Hynix Semiconductor), lists "US6946371 B2*" as an examiner-cited reference.
• EP 2 079 111 A1, which cites "US 6946371 B, Langdo [0022]."

D. Family members — expressly NOT prior art

• US 2004/0045499 A1 (the '371's own pre-grant publication, pub. 2004-03-11) and continuations US 7,122,449 and US 7,439,164 (from App. 11/103,681 and 11/489,787) share the 2002-06-10 priority date and common inventors/assignee. They are not § 102 prior art against the '371.

E. Bottom-line § 102 assessment

No reference in the record I could ground anticipates independent claim 1 as granted. The reason is structural: claim 1's combination of (a) selective epi in a gate-stack/dielectric context, (b) in-situ doping to suppress faceting, and (c) chamber pressure > about 5 Torr is precisely the combination the specification says the prior art (Langdo/UHVCVD) lacks. The closest reference — the Langdo thesis — is an obviousness reference, not an anticipatory one.

F. What remains unverified — and how to close the gap

Because the task specifically asked me to enumerate each patent citation on US 6,946,371, and I could not retrieve that front-page list, I recommend confirming the following directly (I did not have live database access to do so in this session):

1. USPTO PatentCenter (https://patentcenter.uspto.gov) — pull the "References Cited" and any IDS/PTO-1449 for App. 10/458,544 to get the examiner-cited U.S. and foreign patent documents.
2. The granted patent PDF (patentimages.storage.googleapis.com, US6946371.pdf) — the front page ("(56) References Cited") is the authoritative citation list.
3. Google Patents "Patent Citations" tab for US6946371B2 — my searches returned other patents' citation tables instead; a direct page load should yield the exact table.

Caveats on sourcing: Statements about the content and relevance of the five references in Section A are drawn from the patent text supplied (authoritative) and, for the Brasen et al. family/date, from a retrieved EPO/PCT family annex. Dates marked unverified (WO 01/22482, US 6,107,653, Kummer 2002) should be confirmed against the primary documents before being relied upon. I did not invent any examiner citation; the absence of the front-page "References Cited" list is a genuine limitation of this session, not an assertion that the list is empty.

I'll do one quick verification on the unconfirmed Suzuki reference before building the § 103 combinations.

Obviousness Analysis — U.S. 6,946,371 B2 under 35 U.S.C. § 103

Analyst note on scope. This analysis builds on the Prior Art section already generated (Langdo thesis; US 5,442,205; WO 01/22482; US 6,107,653; Kummer et al.; plus the flagged, unverified US 5,861,059). In this session I ran one verification pass on US 5,861,059 and, in doing so, surfaced two additional pre-2002 references that the Prior Art section did not have — US 5,168,089 and US 5,304,834. They are highly material, so I incorporate them below, clearly labeled as newly-verified rather than as items from the earlier section.

Cross-reference flag (contradiction in prior sections). The Litigation summary states the 2007 Intel–AmberWave settlement is confirmed (Intel press release, CNET, EE Times, LA Times), while the PTAB challenges section states the settlement is "not confirmed." These two prior sections contradict each other on the same fact. For § 103 purposes it does not matter (outcome of the 2005 suit has no bearing on prior-art scope), but the contradiction should be reconciled before the page is published.

Posture. US 6,946,371 is Expired – Lifetime (adjusted expiration 2023-07-02). Obviousness is still fully adjudicable against an expired claim (past damages remain at stake), and the earlier sections correctly note there is no PTAB record and no estoppel — so the full § 103 field is open.

1. Legal framework and the person of ordinary skill

I apply the Graham v. John Deere / KSR Int'l v. Teleflex framework: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations. Under KSR, a combination is obvious where it is "the product of ordinary creativity, not of genius" — including where the prior art provides an explicit design incentive, where there is a finite number of identified, predictable solutions, or where a known technique is used to improve a similar device in the same way.

POSITA (asserted, no claim construction needed to reach this call): a process engineer with an M.S./Ph.D. in materials science, electrical engineering, or applied physics and 3–5 years of experience in silicon epitaxy and CMOS process integration, familiar with LPCVD/APCVD/PECVD/UHVCVD reactors, selective epitaxial growth (SEG), HCl-based selectivity chemistry, spacer/liner dielectric stacks, and raised source/drain architecture. The '371's own specification is written to this person (it assumes fluency in spacer undercut, incubation time, and facet crystallography).

2. The reference set (as used, with status labels)

Key takeaway for § 103: The '371 specification admits that facetless SEG in commercial (i.e., > 5 Torr) reactors was already known — the applicant's own novelty story is that facetlessness was previously achieved by spacer geometry control, and that the new route is in-situ doping. That admission is dispositive of the "> 5 Torr" and "commercial CVD" limitations as known elements.

3. Claim 1 — element-by-element mapping to the primary combination

Primary ground (Ground 1): Langdo thesis in view of US 5,168,089 in further view of the '371 AAPA (optionally with US 5,861,059).

Result: Every limitation of claim 1 is disclosed across this small, same-field set, and the one limitation that distinguishes Langdo (pressure) is the headline of US 5,168,089. The combination is not a "puzzle" — it is the ordinary assembly of three references that all address the identical problem (thickness loss at the epi/dielectric interface from faceting) in the identical art (silicon SEG for device source/drain).

4. Why a POSITA would have been motivated to combine (KSR factors)

Factor (F) — explicit design incentive / market force. The '371 specification itself supplies the motivation in plain text: it states that UHVCVD "is generally not feasible for large-scale commercial applications," that "UHVCVD selective growth is not possible with Si₃N₄ dielectric materials," and that the UHVCVD route is "generally not compatible with multi-layered commercial spacer structures." A POSITA reading Langdo immediately faces the incentive to transplant the in-situ-doping facet-suppression mechanism into the commercial reactors the spec names (LPCVD, APCVD, PECVD) — which by definition operate above 5 Torr. The specification's own motivation section is effectively a § 103 roadmap.

Factor (A)/(C) — known technique, improving a similar device in the same way. US 5,168,089 and US 5,861,059 already teach facet-free/no-facet SEG for MOS source/drain in production-type reactors, and US 5,168,089 already teaches doping during the epi growth. Adding Langdo's doping mechanism to a reactor pressure regime that US 5,168,089 already established as facet-tolerant is a predictable combination of known elements with the same expected result (thicker epi at the spacer edge → better implant/silicide margin).

Factor (B) — simple substitution. Substituting one SEG reactor/pressure regime for another (UHVCVD → LPCVD/APCVD/PECVD; sub-Torr → >5 Torr) is a substitution of known, interchangeable deposition hardware for the same purpose.

Factor (E) — "obvious to try" / finite solutions. Facet suppression had a finite, well-enumerated set of known levers in 2002: (i) spacer geometry/undercut (the '371 AAPA), (ii) HCl partial pressure / Si:Cl ratio (US 5,168,089), (iii) hydrogen termination (US 5,861,059), (iv) in-situ doping (Langdo). A POSITA seeking robustness against spacer-process variability would predictably select the one lever — doping — that is process-geometry-independent, which is exactly the '371's stated goal ("it is not necessary to precisely control the liner oxide undercut").

Factor (D) — known device ready for improvement. Raised S/D on strained-Si/SOI was "ready for improvement" because the '371 itself admits the faceting problem degrades exactly those devices.

Combination verifiability: All four references (Langdo, US 5,168,089, US 5,861,059, US 5,304,834) are in the same field (Si epitaxial growth) and are reasonably pertinent to the problem (facet formation at an epi/dielectric boundary) — the KSR/"analogous art" test is easily satisfied, and no reference needs to be imported from a distant technology.

5. Alternative and secondary combinations

Ground 2 — Langdo + Kummer et al. + AAPA (commercial-reactor rationale). Kummer demonstrates high-rate, low-temperature SiGe epitaxy (0.6 µm/min; 500–750 °C) using a commercializable CVD variant (LEPECVD) — direct evidence that the field was pushing out of UHVCVD into manufacturable, higher-throughput reactors. This reinforces Factor (F) and specifically supports dependent claims 25–27.

Ground 3 — Langdo + US 5,168,089, rendering claim 1 obvious as a two-reference combination without needing the AAPA. If US 5,168,089 is treated as the primary reference (it teaches selective, HCl-mediated, substantially facet-free Si epi at 1–55 Torr with optional in-situ doping on a (100) substrate, in a standard epi reactor), then Langdo supplies the missing reason to dope (doping itself suppresses facets), and the case is a straightforward two-reference obviousness combination. Under KSR, a reference teaching the claimed range plus a reference teaching the claimed function is enough absent a showing of criticality (see § 7).

Ground 4 — US 5,861,059 + Langdo. US 5,861,059 already places facet-eliminating SEG in the MOS source/drain context, contemplates Si₃N₄ and laminated SiO₂/Si₃N₄ masks (claims 17–18 of the '371), and names diborane and germane (claims 13–14, 16). Adding Langdo's in-situ-doping mechanism yields claim 1 and much of the dependent set.

6. Dependent claims — obviousness mapping

Net effect: No dependent claim adds a limitation that is not disclosed or rendered obvious by the above set. The only arguably "new" limitation in the entire claim set is the functional coupling of in-situ doping to facet suppression — and that is Langdo's express teaching.

7. Anticipated rebuttals and how they fare

(a) Teaching away? The most likely patent-owner argument is that Langdo's use of SiO₂-only sidewalls and its statement that "selective growth generally cannot be achieved… on Si₃N₄ spacers without the addition of hydrogen chloride," combined with "the deleterious effects of chloride on a UHVCVD system," teaches away from the claimed Si₃N₄-compatible, >5 Torr route. This argument fails: a statement that a particular reactor type (UHVCVD) cannot tolerate chloride is, if anything, a motivation to leave UHVCVD for reactors where HCl is standard practice — which is precisely what US 5,168,089 and the '371 AAPA describe. Teaching away requires a reference to "criticize, discredit, or otherwise discourage" the claimed solution; Langdo does not discredit in-situ-doped facetless growth in a commercial reactor — it discredits its own reactor. If anything the direction of the art (Kummer; the AAPA's commercial-SEG discussion) points toward the claim.

(b) Criticality of "> about 5 Torr." The specification provides no comparative data establishing 5 Torr as a critical, result-effective threshold. The only facetless-growth data point offered is Langdo's sub-Torr UHVCVD result (FIG. 3). Where a claimed numerical boundary is not shown to be critical, it is an obvious design choice among a finite range of known reactor pressures (US 5,168,089: 1–55 Torr). Note the tension: the claim's "> 5 Torr" boundary is lower than the very ranges the art conventionally used — a "range boundary" that sweeps in the ordinary operating regime is a classic § 103 vulnerability.

(c) Secondary considerations. I find no evidence in the record of unexpected results, a long-felt-but-unmet need, failure of others, or commercial success with a nexus. The '371's own "prior art" discussion concedes that facetless commercial SEG was already achieved by spacer-geometry control, which undercuts any "long-felt need" theory for facetlessness per se; the alleged advantage is only robustness to spacer variability, which is a process-optimization benefit rather than a surprising technical result. Caveat: secondary considerations are fact-dependent; a patent owner with access to AmberWave/TSMC process data could attempt a nexus argument, and I have not reviewed any such evidence.

(d) § 112 overlap (flagged, not developed here). The same absence of criticality data bearing on "about 5 Torr," "about 10¹⁷ to about 10¹⁹ cm⁻³," and the functional term "substantially facetless" also raises written-description/enablement and indefiniteness exposure. That is a § 112 issue, noted only because it reinforces the § 103 case by confirming these are design-choice parameters rather than demonstrated critical limits.

8. Claim-by-claim invalidity strength (analyst estimate)

Bottom line: Claim 1 is the weak point and likely only vulnerable to a well-constructed obviousness attack, not anticipation — precisely because the applicant drafted around Langdo by adding the "> 5 Torr" boundary. But the applicant left that boundary squarely inside the disclosure of US 5,168,089 (1–55 Torr, "substantially facet-free," dopants during growth), and the aperture that the applicant used to distinguish Langdo (a commercial, >5 Torr reactor) is exactly the difference the specification itself says motivated the invention. Under KSR, that is a predictable combination of known elements in the same field solving the same problem, and claim 1 — and therefore all 35 claims that depend from it — appears obvious.

9. Honest limitations on this opinion

1. Prosecution history not reviewed. The strength of any § 103 position depends on what the examiner considered and what the applicant argued (and whether US 5,168,089 or US 5,861,059 appear in the IDS/"References Cited"). The Prior Art section correctly noted that the front-page "References Cited" table could not be retrieved; I still cannot confirm whether these references were before the examiner, which affects the inequitable-conduct and "already considered" dimensions even if it does not affect technical obviousness. Verify at USPTO PatentCenter for App. 10/458,544.
2. Newly surfaced references. US 5,168,089 and US 5,304,834 were located in this session's searches, not derived from the '371's own text; their existence, titles, dates, and quoted teachings are as returned by the search results, and the Sutton US 5,168,089 quotations ("substantially facet-free," 1–55 Torr, dopants during growth) should be confirmed against the full issued text before being relied upon in a filing.
3. Kummer 2002 date. As the Prior Art section flagged, the month of the Kummer publication relative to the 2002-06-10 priority date is unverified; that affects its status as prior art for claims 25–27.
4. This is a technical/analyst opinion, not legal advice or a validity opinion of counsel, and no claim construction has been performed. The phrase "gate stack comprising a dielectric region" in granted claim 1 (versus the specification's broader "dielectric region on the first portion") may be construed either broadly (gate + spacer dielectric) or narrowly; I have assumed the broad construction most consistent with the specification.

Overall confidence: moderate-to-high that claim 1, and consequently all dependent claims, would be held obvious under § 103 over the combination of Langdo + US 5,168,089, with US 5,861,059, US 5,304,834, and the '371's own admissions as reinforcing secondary references — contingent on confirmatory review of the primary documents and the prosecution file history.