US 7122449

I'll search for the patent's current status, any litigation, and CAFC 2026 docket activity.

Let me check for any litigation or PTAB proceedings specifically involving this patent.

Let me check the outcome of the AmberWave v. Intel litigation and any reexamination/appeal history.

US Patent 7,122,449 — Analyst Summary

⚠️ Scope note on docket search

I searched for CAFC 2026 docket activity tied to this patent number and found none. I cannot confirm any 2026 Federal Circuit appeal involving US 7,122,449. What I did find is district-court and PTO activity from 2005–2007. I am flagging that explicitly rather than inferring a 2026 appeal exists. (Note also: an unrelated Japanese document, JP 特許第7122449号, is a Sunstar Engineering curable-composition patent — same numeric string, different document. Reported literally, not auto-corrected.)

Bibliographic data (from the authoritative full text)

Abstract (verbatim)

"Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication."

Plain-language overview of the independent claim

Claim 1 is the only independent claim — claims 2–63 all depend, directly or indirectly, from it. Its four elements:

1. Provide a semiconductor substrate whose surface has a first portion and an adjacent second portion.
2. Form a gate stack over the first portion, where the gate stack includes a dielectric.
3. Thereafter (i.e., after the gate stack exists), selectively deposit an epitaxial layer of at least one semiconductor material on the second portion, adjacent the gate stack — and do so while in situ doping that epitaxial layer to a first predetermined level, so that the doping suppresses facet formation on the growing layer.
4. Process condition: the ambient pressure during that selective deposition is greater than about 5 Torr.

The core inventive insight in plain terms: rather than fighting facet formation by engineering the spacer's shape, composition, and undercut (the prior approach, which the specification criticizes as requiring strict geometric control), you simply dope the epi layer as you grow it. That single change suppresses the slanted low-energy crystal planes that would otherwise form where the epi meets the dielectric spacer, and it works in ordinary production CVD tools (RPCVD/APCVD/PECVD) with standard nitride/oxide spacers — unlike the earlier UHVCVD approach, which the patent says was impractical for volume manufacturing and incompatible with Si₃N₄ spacers.

Notable dependent-claim coverage

• Chemistry/process: source gas = precursor + carrier gas, H₂ carrier (claims 6–8, 52); Si precursors silane/disilane/trisilane/DCS (9–10); Ge precursors germane/digermane/GeCl₄/GeCl₂ (11–12); etchant HCl or Cl₂ (13–14); a specific DCS + GeH₄ + HCl + H₂ process for Si₁₋ₓGeₓ with x≈0.2 (15–20).
• Doping: P, As, Sb, B dopants, via phosphine/arsine/stibine/diborane (21–23); doping level > about 10¹⁷ (claim 24).
• Structure: Ge-containing epi (25–26); epi height 10–100 nm (27); oxide and/or nitride dielectric, two-layer oxide-liner/nitride-spacer (28–29); liner thickness ~25 nm, spacer 30–100 nm (30–31); liner undercut beneath the nitride spacer (32).
• Substrate variants: silicon (33); Si wafer + insulator + strained semiconductor layer (34–35); substrate including an insulating layer (36); strained material beneath the gate stack (38–39, 58–59, 62).
• Contacts: contact material over the epi, from Co/Ti/W/Mo/Pt/Ni/Ta, notably Ni or W (40–43, 55, 60, 63).
• Geometry: (100) substrate surface (44); dielectric sidewall at 60°–90° (45); sidewall aligned to <110> or <100> (46–47); epi adjacent to an isolation region / shallow trench (48–50).
• Tooling: single-wafer RPCVD system (5, 51).

Known enforcement / validity history (beyond the face of the patent)

• AmberWave Systems Corp. v. Intel Corp., C.A. No. 05-301-KAJ (D. Del.) — the '449 patent was added to this consolidated action (Delaware I). Court correspondence (D.I. 191, 197, Oct.–Nov. 2006) shows AmberWave moved to add the newly issued '449 patent and Intel did not oppose consolidation, arguing instead that the '449 and '907 patents should go to the "Delaware II" case (Intel v. AmberWave, 06-429-KAJ).
• Reexamination: AmberWave's Nov. 20, 2006 letter to Judge Jordan states that Intel sought reexamination of the '449 patent (and of US 7,074,655), allegedly in breach of a March 23, 2006 stipulation in which Intel agreed not to seek reexamination of patents in suit. I could not confirm from the search results whether that '449 reexamination was granted, nor its outcome — treat that as unresolved.
• Settlement: Intel and AmberWave settled the pending suits (reported March 6, 2007; LA Times / Bloomberg brief), under which Intel took a 10-year license to AmberWave technology; other terms confidential.
• Family litigation flag: the Google Patents record carries a "Family has litigation" indicator for this family.
• CAFC 2026: no evidence found. The patent's term expired June 10, 2023, which makes a live 2026 merits appeal on the '449 patent itself unlikely — but I state this as an inference, not a verified fact.

Uncertainty notes

• Assignee chain is from the Google Patents reassignment record (AmberWave → TSMC, recorded Jan. 26, 2010); I did not independently verify current TSMC ownership in USPTO assignment records.
• I did not retrieve a live USPTO Patent Center / PAIR record for application 11/103,681, so filing/issue data here rest on the authoritative full text plus the Google Patents legal-events timeline.
• The '449 reexamination's petition date (Oct./Nov. 2006), grant status, and any resulting claims are not established by the sources I retrieved.

I'll search litigation databases for US patent 7122449.

Let me dig deeper into specific litigation databases and the patent's litigation family record.

Let me check additional litigation sources and related AmberWave enforcement actions.

Summary answer

I found no litigation specifically asserting U.S. Patent No. 7,122,449.

Despite multiple targeted searches of patent‑litigation portals (Unified Patents' litigation/PTAB case lists, Google Patents' litigation module, Darts‑ip family data, and CAFC/PACER‑derived reporting), I could not identify any complaint, declaratory‑judgment action, or PTAB proceeding in which US 7,122,449 was named as an asserted patent. I am therefore reporting that no litigation on this specific patent number is known to me, and I am flagging below the one indirect, family‑level indicator I did find so you can run it down yourself.

What I did find

1. Family‑level litigation flag (not patent‑specific)

The Google Patents record for US7122449 carries a Darts‑ip "family has litigation" link:

• URL: https://patents.darts-ip.com/?family=29736373&...&patent=US7122449(B2)
• Text on the page: "Family has litigation — First worldwide family litigation filed."
• Family ID: 29736373

This tells us that some member of the '449 patent family (which also includes US 6,946,371 and US 7,439,164, all claiming priority to provisional 60/387,867 filed 2002‑06‑10) was litigated. It does not establish that the '449 patent itself was asserted, and the Darts‑ip record is behind a paywall that I could not open. Treat this as a lead, not a confirmed case.

2. The AmberWave enforcement campaign (related, but different patent numbers)

AmberWave Systems Corp. (Salem, N.H.) ran a strained‑silicon enforcement campaign in 2005–2007, but the patents actually asserted were '292, '632, and '371 — not '449:

Related filings in the same dispute:

• Intel v. AmberWave (declaratory judgment on U.S. 6,831,292), D. Del., filed May 17/25, 2005 — the first‑filed action that drove the transfer above.
• AmberWave v. Intel (U.S. 6,946,371), E.D. Tex., filed Sept. 20, 2005; Intel responded with a DJ action on the '371 in D. Del.
• Sources: EE Times ("Intel settles strained silicon litigation," 3/5/2007; "AmberWave files suit against Intel," 7/18/2005; "AmberWave adds patent to Intel wrangle," 9/29/2005); Casetext, Amberwave Systems Corp. v. Intel Corporation, 2:05‑CV‑321.

Why this matters for '449 (and why it still isn't '449 litigation): US 7,122,449 is a continuation of application 10/458,544, which issued as US 6,946,371 — i.e., '449 and '371 share the same specification and priority. So the '449 patent is a sibling of an asserted patent. That explains the Darts‑ip family flag. But the patent number asserted in the pleadings was literally the '371, and '449 did not issue until October 17, 2006 — after the Intel complaints were filed — so it could not have been pleaded in them. The March 2007 Intel settlement licensed "all AmberWave patents," which would encompass '449 going forward, but that is a license, not an assertion.

Caveats and limitations (stated explicitly rather than guessed)

1. I could not confirm any case naming US 7,122,449. If such a case exists (e.g., a later assertion after TSMC acquired the portfolio in January 2010, or an unlisted action against Samsung or others), I did not locate it within my search budget and I won't assert it exists.
2. The Darts‑ip "family has litigation" indicator is unresolved. It is the strongest signal I found, but it attaches to family 29736373 as a whole, and I could not retrieve the underlying case records to see which family member(s) were asserted.
3. Do not treat the AmberWave v. Intel case as '449 litigation. The asserted numbers were 6,831,292, 6,881,632, and 6,946,371. Reporting it as a '449 case would be a number‑substitution error of exactly the kind I was instructed to avoid.
4. Verify independently before relying on this. Recommended next steps: (a) run the exact string "7,122,449" in the Unified Patents litigation and PTAB case lists (https://portal.unifiedpatents.com/litigation/caselist, .../ptab/caselist); (b) pull the Darts‑ip family 29736373 record; (c) search PACER/RECAP in D. Del. and E.D. Tex. for "AmberWave" complaints and check the counts/patents‑in‑suit exhibits; (d) check the USPTO assignment record (AmberWave → TSMC, Jan. 26, 2010) for any subsequent enforcement.

Bottom line: To the best of my knowledge and searching, there is no known litigation involving US 7,122,449 as an asserted patent; the only litigation‑related evidence is a family‑level flag on Google Patents/Darts‑ip pointing to the AmberWave strained‑silicon campaign, in which sibling patent '371 — not '449 — was pleaded.

PTAB / AIA Trial Proceedings — US 7,122,449 ("Methods of fabricating semiconductor structures having epitaxially grown source and drain elements")

Patent Owner (current): Taiwan Semiconductor Manufacturing Co. (TSMC), Ltd. — acquired from AmberWave Systems Corp. via assignment recorded 2010-01-26
Inventors: Thomas A. Langdo; Anthony J. Lochtefeld | Priority: 2002-06-10 | Granted: 2006-10-17 | Patent expired 2023-06-10 (anticipated expiration; status per Google Patents: "Expired – Lifetime")

Proceedings overview

Total AIA trial proceedings on file: 0. The USPTO Open Data Portal (ODP) returns no IPR, PGR, or CBM proceedings against US 7,122,449 as of the most recent ingest, and my independent web searches surfaced no petition, institution decision, FWD, or appeal involving this patent — so the breakdown is 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution-denied. Bottom line for a defendant: the patent's 63 claims are entirely untested at the PTAB. There is no claim you can call "dead," no § 315(e) estoppel wall to hide behind, and no FWD to quote — but there is also no PTAB-driven narrowing that would otherwise have forced a patent owner to concede scope. The claims you face are exactly the claims that issued in 2006.

Search limitation, stated plainly: I could not query PTAB E2E/PTACTS or Docket Alarm directly in this session; my confirmation is limited to (a) the structured ODP block supplied in the prompt, which is the canonical source, and (b) general web searches that returned no hits for "7,122,449" + IPR/PGR/CBM. A pre-AIA ex parte reexamination or an Interference (Art. I) would not appear in the ODP AIA-trial feed. I found no evidence of either, but I did not verify reexamination certificates at the file wrapper.

Per-proceeding detail

No proceedings to report. No proceeding number, petitioner, panel, institution decision, FWD, settlement, or Federal Circuit appeal exists to describe for this patent, and I will not invent one. Any output purporting to list an IPR number for the '449 patent would be fabricated.

Related-family and litigation context (non-PTAB, flagging for completeness)

• Family (same specification / common priority 2002-06-10): US 6,946,371 B2 (parent, application 10/458,544, filed 2003-06-10); US 7,122,449 B2 (this patent, continuation, app. 11/103,681, filed 2005-04-12); US 7,439,164 B2 (further continuation, app. 11/489,787, filed 2006-07-20). All three are recorded "Expired – Lifetime." Foreign counterparts: WO 2003/105206 A1 and AU 2003247513 A1.
• Litigation flag: Google Patents reports "Family has litigation / First worldwide family litigation filed" (Darts-IP family 29736373). The public record I surfaced shows AmberWave Systems and Intel exchanging interrogatory responses and production requests in AmberWave Systems Corp. v. Intel Corp., U.S.D.C. (D. Del.), C.A. No. 05-301-KAJ (consolidated), with papers dated 2006. That is a 2005-era district court case — seven years before the AIA created IPR — and nothing in it is a PTAB trial. I have not verified which AmberWave patents were asserted in that case, and I cannot confirm that the '449 patent was among them.
• Technical significance signal: the '449 patent is cited by later IBM, Samsung, Micron, AMD and TSMC filings (37 "cited by" entries), and it appears as a "disruptive" reference in third-party portfolio analyses. High technical relevance does not, however, translate into PTAB attention here.

Strategic summary

Claim status across the '449 patent: all 63 claims are UNTESTED. Claims 1–63 — including independent claim 1 (selective epitaxial deposition after gate-stack formation, in situ doped to suppress faceting, ambient pressure > about 5 Torr) and its many dependent limitations (DCS + GeH₄ + HCl chemistry and x≈0.2 at claims 15–20; two-layer oxide-liner/nitride-spacer structures at claims 29–32 and 56–57; nickel/tungsten contact material at claims 41–43, 55, 60, 63; strained-silicon channel at claims 38–39, 58–59, 62) — have never been construed or adjudicated by the Board, and no claim has been canceled. Unlike the common "hardened patent" narrative, there is no PTAB narrowing to exploit and equally no PTAB record to lean on.

Estoppel landscape: completely open. Because there has been no IPR, there is no § 315(e)(2) estoppel against anyone. A defendant today may raise any § 102/§ 103 ground in district court or file a fresh IPR petition without the successive-petition and estoppel baggage that follows a prior trial. One caveat from the specification itself: the patent expressly distinguishes the Langdo 2001 MIT Ph.D. thesis, "Selective SiGe Nanostructures," and the UHVCVD in situ n-doping work shown in prior-art FIG. 3 as known, non-commercializable art. Because inventor Langdo authored that thesis, treat it as a candidate reference that requires a careful § 102(b)/grace-period and inventor-disclosure analysis before you build a ground on it — do not assume it is available art.

Pattern signals: none of the usual ones. No petitioner has filed even once against this patent, so there is no repeat-petitioner pattern; no Unified Patents or other defensive-aggregator filing is in the chain; and the patent owner has never had occasion to defend an appeal before the Federal Circuit on this patent. The absence of IPR activity is best explained by the patent's age (filed 2003) and the fact that its operating lifetime closed on 2023-06-10 — well-asserted patents of this vintage generally attract petitions only when they are being actively monetized, and this one apparently never was. Note also that today's institutional climate makes a new petition an uphill fight on discretion alone: post-2025 Director-level practice weights "settled expectations," and a patent in force for more than six years is presumptively entitled to them under the Acting/confirmed Director memoranda (Willkie client alert, 2025-10; Irwin IP, PTAB Year in Review 2025). A § 102(b)-based IPR against a 2003-priority patent would face that headwind even though there is no prior validity adjudication to trigger the currently proposed bar on petitions against patents that survive validity challenges.

Recommended next steps

1. Do not expect a PTAB shortcut. There is no final written decision to cite and no canceled claim to link. Any opinion you file asserting otherwise is sanction-bait. The correct citation is the absence of proceedings: the ODP AIA-trial feed for US 7,122,449 is empty.
2. Confirm the file-wrapper history yourself before relying on the "no proceedings" conclusion. Pull the complete file wrapper and any reexamination certificates via USPTO Patent Center (https://patentcenter.uspto.gov) and cross-check PTAB E2E / PTACTS (https://ptacts.uspto.gov) using "7122449" and "11/103,681," plus the sibling applications 10/458,544 and 11/489,787. Also check Docket Alarm / CourtListener (https://www.courtlistener.com) for D. Del. C.A. No. 05-301-KAJ and any later TSMC-side assertion involving the '449 family.
3. Litigate the expiration date as a damages cap. The patent expired 2023-06-10 and maintenance-status records confirm it lapsed; absent a § 286 lookback and any terminal-disclaimer/safe-harbor analysis, recoverable damages run only on pre-expiration conduct within the six-year window. Confirm the expiration date against the face of the patent (which, per the family record, carries a § 154(b) term adjustment) rather than relying solely on the Google Patents banner.
4. If you are sued today and want a PTAB option, act fast and file a supporting merits showing. A petition must clear Director-level institution; build the record with the specific 1998–2002 selective-epitaxy/facet-suppression literature (the specification's own background section is a roadmap of what the applicants admitted was known) and address the "settled expectations" factor head-on by showing active assertion and a live damages case. If a parallel district court case exists, weigh a Sotera-style stipulation — but note that after the 2025 rescission of the 2022 Fintiv guidance, such a stipulation is "highly relevant but not dispositive."
5. Watch the family. US 6,946,371 and US 7,439,164 share the '449 specification and priority date. If a plaintiff has asserted any of them, the same zero-IPR baseline applies and the same prior-art universe is available — but a petition against one sibling does not create estoppel or claim-preclusive effect for the others. Treat each patent number separately and verify per-patent before asserting anything in a brief.

Sources relied on: structured ODP "PTAB proceedings on file" block (no AIA trials); US 7,122,449 full text and prosecution/family record at https://patents.google.com/patent/US7122449/en; PTAB institutional-practice materials cited above. No PTAB decision or Federal Circuit opinion exists for this patent to link.

I'll research the assignment chain for US 7122449, starting with the record sources.

I could retrieve the two recorded ownership events for US 7122449 from the Google Patents legal-events record (which mirrors the USPTO assignment data), but the reel/frame numbers and correspondent-of-record fields did not appear in any source I could reach. I have not fabricated them; they must be verified directly in the Assignment Center. I also hit my research-step limit before I could pull the underlying USPTO record pages, so the sections below are grounded in what is verifiable and flag what is not.

Inventors

Pattern note: No evidence of the "inventors depart within 12 months" fire-sale tell. Both inventors executed an assignment to the original assignee (recorded 2005-06-10, i.e., ~2 months after this continuation was filed on 2005-04-12 and ~2 years after the parent application 10/458,544 was filed on 2003-06-10). I could not verify either inventor's subsequent employment history, so any departure claim would be speculation and I am not making one.

Original assignee

AmberWave Systems Corporation (listed as "Amber Wave Systems Inc" on the 2005-04-12 filing; the assignment names "AmberWave Systems Corporation") — Salem, New Hampshire.

• Business model: AmberWave was an MIT spin-out materials-research and IP-licensing company ("a materials research science company with an intellectual property (IP) business model"), founded 1998/1999, ~20–30 employees, funded with ~$91M of VC (3i, Adams Capital, ARCH Venture Partners, Hillman, TeleSoft). It operated a 30,000 sq-ft facility with a class-10 clean room for epitaxy R&D.
• Did it ship a product embodying the claims? No. AmberWave did not manufacture or sell chips; it licensed strained-silicon process technology. Its revenue model was patent licensing plus technical support — i.e., it did not practice the claimed raised source/drain fabrication methods in commerce.
• Assertion history (family-level): AmberWave sued Intel in E.D. Tex. on 2005-07-15 over US 6,881,632, and added US 6,946,371 — the parent of this patent — on 2005-09-20; Intel filed DJ actions in Delaware over 6,831,292 and subsequently 6,946,371. The Google Patents "Family has litigation" flag for family 29736373 corresponds to this dispute. Settled 2007-03-05 with Intel taking a 10-year license to all AmberWave patents and applications.
• Current status: As a semiconductor IP holder, effectively wound down — its semiconductor patent portfolio was transferred to TSMC, executed/recorded in the 2010-01-26 event. Academic analysis of TSMC's external technology acquisition identifies "AMBERWAVE SYS" as a principal source of TSMC's externally acquired patents in 2006–2010. The AmberWave name persisted in later solar/ART materials work. I could not confirm a Chapter 7/11 filing, so I do not characterize the 2010 transfer as a bankruptcy sale.

Assignment timeline

The record shows two ownership events. Reel/frame numbers are not retrievable from the sources I could reach and are deliberately left blank — do not cite them until verified at the Assignment Center.

• 2005-06-10 (executed and recorded per the Google Patents legal-events entry) — Reel / (not retrieved)

  • Conveyance: Assignment of inventors' interest
  • Assignor: Thomas A. Langdo and Anthony J. Lochtefeld
  • Assignee: AmberWave Systems Corporation
  • Correspondent: Not listed in the record I could retrieve. (No recurrence can be assessed; flag as unverified.)
  • Context: Ordinary employee/inventor assignment to the original assignee, taken in connection with the 2005-04-12 continuation of parent 10/458,544.

• 2010-01-26 (recorded; execution date not shown in the retrieved record) — Reel / (not retrieved)

  • Conveyance: Assignment
  • Assignor: AmberWave Systems Corporation
  • Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
  • Correspondent: Not listed in the record I could retrieve. (Flag as unverified — this is the single most useful field for the analysis you asked for, and it is exactly the field I could not obtain.)
  • Context: Portfolio sale / transfer of AmberWave's semiconductor patent assets to an operating foundry, coincident with the wind-down of AmberWave's strained-silicon licensing business.

Related family (for chain completeness, not separate members of this assignment chain): US 6,946,371 (parent, issued 2005-09-20) and US 7,439,164 (continuation, filed 2006-07-20) — both AmberWave-origin, both now under the same TSMC ownership. Also filed internationally: WO 2003/105206 A1 and AU 2003247513 A1.

No other recorded post-issuance assignments exist in the record I could retrieve. In particular, there is no chain of LLC-to-LLC transfers, and no assignment to any entity on the NPE lists you supplied.

Timeline diagram

timeline
    title Ownership of US 7122449
    2002 : Priority application filed by AmberWave
    2003 : Parent application 10458544 filed
    2005 : Inventors assign rights to AmberWave
         : AmberWave sues Intel over patent family
    2006 : US 7122449 issued to AmberWave
    2007 : Intel settlement and 10 year license
    2010 : Portfolio assigned to TSMC
    2023 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only post-issuance transfer (2010-01-26) runs from AmberWave Systems Corporation to Taiwan Semiconductor Manufacturing Company, Ltd., a major operating semiconductor manufacturer — the opposite of a transfer to an anonymous "IP Holdings" LLC. No LLC suffix, no registered-agent address, no single-purpose entity appears anywhere in the chain.

2. Known asserter in the chain — Unclear / weak. No assignee matches the enumerated lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg). However, AmberWave Systems appears in at least one published NPE survey (a Korean IP-activity report cataloguing NPE status), and AmberWave's own fact sheet confirms a pure IP-licensing model with no product sales, and it asserted the family against Intel. That is business-model evidence, not list-membership. Recorded date supporting the assertion: the E.D. Tex. complaint of 2005-07-15 and the 2005-09-20 complaint on parent US 6,946,371.

3. Repeat correspondent across the chain — Unclear; cannot be assessed. The correspondent-of-record field was not present in any record I could retrieve for either entry. This is the highest-value missing datum; if the 2010-01-26 TSMC recording shows the same correspondent as the 2005-06-10 entry, that would be significant — but I have no basis to assert it either way.

4. Cascading transfers — Not present. One post-issuance transfer, roughly 3 years 3 months after issuance (2006-10-17 → 2010-01-26) and ~5.6 years after the inventors' assignment. No chained LLCs, no shared-principal pattern.

5. Pre-litigation transfer — Not present. The family litigation (AmberWave v. Intel, 2005) was brought by the then-current owner, the original assignee — not by a recently-acquired transferee. The 2010 transfer came ~5 years after the litigation settled and no suit against TSMC competitors followed in the record.

6. Bankruptcy fire-sale — Unclear. The 2010 portfolio transfer to TSMC coincides with the wind-down of AmberWave's semiconductor IP business, which is consistent with a distressed asset sale, but I found no evidence of a Chapter 7 or Chapter 11 filing and the execution date of the 2010-01-26 recording is not shown. Do not assert bankruptcy without the docket.

7. Privateering — Not present. No evidence that AmberWave transferred to an NPE to assert on its behalf, and no SEC disclosure (AmberWave was private) or Patent Progress/EFF coverage surfaced. TSMC, the transferee, is the acknowledged practicing entity and has not been shown to assert this patent.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates at TSMC, a manufacturer, not at RPX, AST, LOT, Unified Patents, or OIN. No neutralization signal.

Verdict

NPE — moderate confidence.

The signal is one of business model and assertion conduct, not shell-entity machinery: the original assignee, AmberWave Systems Corporation, held this patent from the inventors (recorded 2005-06-10) while describing itself in its own materials as an "intellectual property business model" company that licensed rather than sold products, and it enforced the family — including parent US 6,946,371, asserted 2005-09-20 in E.D. Tex. against Intel. That is a non-practicing entity asserting against a practicing one. Against that, every one of the classic high-confidence signals is absent: the single post-issuance transfer (recorded 2010-01-26) moved the patent to TSMC, a large operating manufacturer, not to a licensing LLC; there is no cascading LLC chain, no pre-litigation transfer, no defensive-aggregator terminus, and no confirmed bankruptcy. Confidence is capped at moderate because the two most diagnostic fields — reel/frame and correspondent of record — could not be retrieved, and because AmberWave was a genuine VC-funded R&D company with a clean room rather than an anonymous assertion vehicle.

Verification links:

• USPTO Assignment Center search: https://assignmentcenter.uspto.gov/
• Assignment Search (indexed): https://assignment.uspto.gov/patent/index.html
• Confirm the two entries above by searching patent number 7122449 and capture: (a) reel/frame for the 2005-06-10 inventors→AmberWave recording, (b) reel/frame, execution date, and correspondent for the 2010-01-26 AmberWave→TSMC recording. If you supply those four fields, I can upgrade or overturn this verdict and complete signal #3.

I'll research US patent 7122449 and its prior-art citations. Let me run several targeted searches.

Let me pull the specific patent citation lists from the patent's front page.

Summary of what I could and could not verify

Important caveat up front. I identified the correct patent — US 7,122,449 B2 (not a look‑alike number) — and confirmed its bibliographic record. However, the authoritative text of the patent provided to me (the Google Patents fetch) contains the front page, description, claims, forward citations ("Cited By" / "Families Citing this family") and family data, but the §(56) "References Cited — U.S. Patent Documents" list (the applicant/examiner‑cited U.S. patents) is not present in that text. My searches did not surface that list verbatim. Rather than reconstruct it from memory (which would risk fabricating patent numbers — a violation of your strict‑ID rule), I separate below:

• (A) Prior art I can ground — references cited inside the patent's own text, plus the applicant‑cited non‑patent literature that mirrors do expose; and
• (B) An explicit statement of what I could not retrieve, so you can pull the official list from USPTO PatentCenter.

I also note that every entry in the "Cited By" and "Families Citing this family" tables is later‑dated than this patent and is therefore NOT prior art — those are forward citations.

1. Confirmed identity of the patent (grounded in the provided text)

2. The legally relevant must‑have elements to search against

For §102 analysis the independent claims drive everything. The critical limitations are:

• Claim 1 — semiconductor substrate; gate stack with a dielectric over a first portion; thereafter selectively depositing an epitaxial layer of at least one semiconductor material on a second portion adjacent to the gate stack while in situ doping the layer to a first predetermined level to suppress facet formation; and ambient pressure during selective deposition greater than about 5 Torr.
• Claim 24 — doping level greater than about 10¹⁷.
• Claim 15/16 — DCS + GeH₄ + H₂ + HCl source gas → Si₁₋ₓGeₓ with x ≈ 0.2; claim 17 (<20 Torr), 18 (500–900 °C).
• Claims 21–23 — in‑situ dopant P/As/Sb/B (claim 23 boron).
• Claims 40–43, 55, 60, 63 — metal contact (Co, Ti, W, Mo, Pt, Ni, Ta; claim 42/55/60/63 Ni or W).
• Claims 34–39, 58–62 — strained‑semiconductor substrate / strained material beneath gate.

Any §102 reference must disclose all of these for the claim at issue; the facet‑suppression‑by‑in‑situ‑doping plus pressure limit is the novel core, so most of the art below is realistically §103 material, not standalone anticipation.

3. (A) Prior art I can ground

A‑1. References cited in the patent's own background/description

Note: the inventor Langdo is also the author of the thesis relied upon in the background — a §102(b)/§103 grace‑period and inventorship point worth verifying against the 2002‑06‑10 priority date.

A‑2. Applicant‑cited non‑patent literature exposed by the patent mirror

The Justia "Referenced Cited" record for 7,122,449 lists a large body of SEG/raised‑S/D/facet literature. The entries most relevant to the claimed subject matter are:

(The Justia record also contains many boron/phosphorus‑diffusion, SiGe‑HBT and annealing references — e.g., Cressler, Patton, Fahey, Moriya (Phys. Rev. Lett.), Cowern — that appear less on‑point for the raised‑S/D facets claims and may originate from a sibling filing; I flag them as "provenance unverified" rather than mapping them.)

4. §102 mapping of the strongest candidates

Bottom line under §102: none of the references I could verify discloses every element of independent claim 1 (in‑situ doping to suppress facet formation combined with ambient pressure > about 5 Torr in a commercial CVD system, performed after gate‑stack formation). The strongest single‑reference case is the Langdo thesis, but the >5 Torr and Si₃N₄‑spacer limitations are the distinguishing features the patent itself emphasizes. The rest are best deployed as §103 combinations (e.g., Langdo thesis + Tanno/Fitch for pressure/etchant, or Nakahara + Drowley).

5. What I could not retrieve (and how to close the gap)

• I could not obtain the verbatim (56) "References Cited — U.S. Patent Documents" list printed on the face of US 7,122,449. Searches for that block returned unrelated patents and the forward‑citation tables only. I therefore decline to list U.S. patent numbers as cited prior art beyond those the patent's own text names (US 5,442,205; US 6,107,653; WO 01/22482), to avoid fabricating identifiers.
• To complete the §102/§103 sweep authoritatively, pull the front page of the grant PDF (or the file wrapper) for:
  • US 7,122,449 – https://patentcenter.uspto.gov / https://patents.google.com/patent/US7122449/en (see "Patent Citations" block on the grant image)
  • parent US 6,946,371 and child US 7,439,164 (same §56 list is often shared)
  • the PCT/ISA search report for family member WO 2003/105206 A1 (the international counterpart), which will carry the examiner's X/Y category citations — often the most probative §102/§103 references.
• Also worth verifying: (i) whether the Langdo 2001 thesis qualifies as a §102(b) printed publication / is subject to the grace‑period or the inventor's‑own‑work exception given the 2002‑06‑10 priority; and (ii) the Darts‑ip litigation flag (family 29736373), since litigation may have already produced invalidity contentions identifying the operative prior art.

If you can supply the (56) U.S. patent list (or the WO 2003/105206 search report), I will map each cited U.S. patent against claims 1, 15–24, 40–43 and 53–63 element‑by‑element under §102.

I'll ground a few facts about the references listed on this page before building the §103 analysis.

Obviousness Analysis — US 7,122,449 B2 (35 U.S.C. § 103)

Patent: US 7,122,449 B2, "Methods of fabricating semiconductor structures having epitaxially grown source and drain elements"
Inventors: Thomas A. Langdo, Anthony J. Lochtefeld — Original assignee: AmberWave Systems; current assignee: Taiwan Semiconductor Manufacturing Co. (TSMC)
Appl. No. 11/103,681, filed 2005‑04‑12; continuation of 10/458,544 (filed 2003‑06‑10, now US 6,946,371); priority to provisional 60/387,867 filed 2002‑06‑10. Granted 2006‑10‑17. Status: Expired‑Lifetime (anticipated expiration 2023‑06‑10).
Legal regime: Application filed before 2013‑03‑16 → pre‑AIA §§ 102/103 govern.

1. What the "Prior Art" content of this page actually supplies (and what it doesn't)

Two cautions before the merits:

(a) The page does not contain a backward "References Cited" list. The prior‑art‑relevant fields on the fetched page are only: the Prior art keywords (epitaxial layer, silicon, semiconductor, layer, chemical vapor), the Prior art date (2002‑06‑10), the Background discussion (which names specific documents), and two forward citation tables — "Cited By (37)" and "Families Citing this family (107)." Forward citations are generally not prior art. This analysis is therefore bounded by what the page shows; a definitive §103 opinion requires the file wrapper/IDS, including any examiner citations from 10/458,544.

(b) Almost the entire "Cited By" list post‑dates the 2002‑06‑10 priority date and is therefore not §102 art. Scanning the 37 entries, only two carry pre‑2002‑06‑10 priority dates:

• US 2005/0095790 A1 (Xerox, priority 2002‑02‑22) — integration of heterogeneous circuit devices. Only marginal relevance (isolation/contact integration).
• US 8,586,452 B2 (TSMC, priority 2002‑06‑07) — "Methods for forming semiconductor device structures." Its U.S. application is 13/227,077, filed 2011‑09‑07 (https://patents.google.com/patent/[US8586452B2](/patent/US8586452B2)/en), so any §102(e) date depends on the earliest U.S. filing in its chain (and §112 support for the subject matter relied on). Three days separate its priority date from the '449 provisional; this is the one forward citation worth pulling from the file wrapper. I could not confirm its earliest U.S. non‑provisional filing from the page, so I do not treat it as established art here.

(c) What the page does give as usable art (all from the Background section):

Anticipation check: No single reference on this page discloses every element of claim 1. Langdo (UHVCVD, ~10⁻³–10⁻⁶ Torr, no HCl) does not disclose the claim‑1 "ambient pressure ... greater than about 5 Torr." This is, therefore, a §103 case, and the pressure limitation is essentially the only difference over Langdo's teaching.

2. Claim 1 — the crux of the patent

Claim 1 requires: (i) a substrate with first/second surface portions; (ii) a gate stack comprising a dielectric over the first portion; (iii) thereafter selectively depositing an epitaxial layer on the second portion adjacent the gate stack while in situ doping to a first predetermined level to suppress facet formation; and (iv) ambient pressure > about 5 Torr.

Claims 2–63 are all dependent (directly or through other dependents) on claim 1 — there is no second independent claim. So the obviousness of claim 1 controls the rest of the set.

Ground 1 (strongest): Langdo thesis + Applicant's admitted prior art (commercial LP/AP CVD facetless SEG)

Correspondence

• (i)–(iii): Langdo teaches exactly this — facet‑free selective Si/SiGe growth for raised source/drain (i.e., a gate‑adjacent selective epi element), with facet suppression achieved by in situ doping rather than by spacer geometry, at a doping level (1×10¹⁸ cm⁻³, FIG. 3 of the '449 patent) squarely inside claims 24 (">about 10¹⁷") and the 10¹⁷–10¹⁹ description.
• (iv): The Background admits that facetless SEG for raised S/D was already being done in commercially available LPCVD and APCVD reactors (controlling spacer geometry/liner undercut, HCl for selectivity), and those reactors inherently operate at torr‑level to atmospheric pressure. The specification itself names the commercial single‑wafer platforms (Applied Materials EPI Centura; ASM Epsilon), corroborating that >5 Torr operation was routine (claims 4, 5, 51).
• The chemistry of claim 1's supporting claims (DCS, HCl, H₂: claims 9–14, 15) is the **admitted ** selectivity chemistry for Si₃N₄ spacers.

Motivation to combine (articulated)

1. The reference itself supplies the motivation. Langdo expressly identifies UHVCVD as unsuitable — UHVCVD is "generally not feasible for large‑scale commercial applications," chloride addition is "impractical," and selective growth on Si₃N₄ is not possible — which is a direct invitation to move the (known) in‑situ‑doping facet‑suppression technique into the (known) commercial chloride‑based LP/AP CVD platform. See the '449 Background and the thesis abstract.
2. Known technique, same problem, same field. Facet suppression is the identified problem in both references; the field was already pursuing facetless SEG in commercial CVD ("inverse patterns," liner undercut) — Langdo/Background at p. "Recently, facetless epitaxy has received much attention…"
3. Predictable result. Faceting is a surface‑energetics/kinetics phenomenon at the epi/dielectric interface (the patent's own definition of "facet"). One of ordinary skill would reasonably expect adsorbate‑mediated (dopant) modification of growth kinetics to operate independent of reactor type, particularly since the patent presents no comparative RPCVD data showing that facet suppression fails at >5 Torr without the invention. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a predictable substitution/combination of known elements is obvious; the rationales of MPEP 2143 (A), (C), (F) apply.
4. Reactor pressure as a design choice. Choosing a commercial RPCVD/APCVD/PECVD reactor (Background; Kummer) necessarily places the ambient above 5 Torr; absent evidence of criticality, the numerical limit is a result of the equipment selection, not an inventive step (In re Aller-type design‑choice reasoning).

Ground 2: Ground 1 + Kummer et al. (PECVD)

Kummer supplies: CVD epi of Si/SiGe at 500–750 °C (claims 18–20), growth rates far exceeding ">1 nm/min" (claim 37), in‑situ doping with phosphine, and explicit migration to a 300‑mm single‑wafer production reactor (claims 3, 4, 5, 51). Combined motivation: Langdo's own temperature window (650–850 °C, selectivity at 750 °C) plus Kummer's demonstration that commercial single‑wafer CVD runs SiGe epi in this range — i.e., the claimed process window is the overlap of two known windows.

Ground 3: Ground 1 + WO 01/22482 (and the US 5,442,205 / US 6,107,653 "virtual substrate" art)

• Claims 15–17, 25–26, 53–54, 61 (SiGe/Si epi; DCS + germane + HCl + H₂; x ≈ 0.2): WO 01/22482 teaches epitaxial Si₁₋ₓGeₓ CVD with chlorine‑bearing precursors, graded/relaxed buffers, and preferential reduced‑pressure regimes — i.e., the reactor/precursor framework onto which claim 1's process is grafted.
• Claims 34–36, 38–39, 58–59, 62 (SOI; strained layer above an insulator; strained Si beneath the gate stack): US 5,442,205 (strained Si heterostructures) + US 6,107,653 (planarized graded SiGe buffer), combined with the admitted prior art of raised S/D on SOI/strained Si ("raised source/drain contacts have been proposed as a means of forming shallow dopant junctions…"; "provide sacrificial silicon useful for silicide consumption").
• Motivation: The '449 specification argues that faceting is especially harmful in strained‑Si/SOI devices because silicide can punch through the strained layer into relaxed SiGe. That motivation is supplied by the applicant's own background — a POSITA seeking to commercialize raised S/D for strained‑Si CMOS would apply the known facet‑suppression doping technique to those known substrates.

Ground 4: any of the above + admitted SALICIDE art

Claims 40–43, 55, 60, 63 (Co, Ti, W, Mo, Pt, Ni, Ta contacts; Ni; W). The Background admits the self‑aligned silicide ("SALICIDE" per the specification: "a self‑aligned silicide process, in which the contacts are formed only in the areas where the deposited metal is in direct contact with the source/drain regions") for raised S/D. Choosing among recognized refractory‑metal silicides for a given junction depth is routine optimization (MPEP 2144.04).

3. Dependent‑claim vulnerability map

Weakest link in the patent's position: every independent‑claim‑level limitation beyond Langdo is a reactor/pressure/geometry selection that the applicant's own Background concedes was conventional in commercial CVD. The claims with the most resilience are those coupling (a) chloride chemistry + (b) Si₃N₄ remaining in place + (c) in‑situ doping sufficient to suppress facets but below CMOS counter‑doping levels (claims 21–24, 53–55, 56–60, 63) — because the specification argues that Langdo's UHVCVD could not add HCl and could not grow selectively on nitride.

4. Counter‑arguments the patent owner will (and can) make

1. "Teaching away" from chloride‑based in‑situ doping. Langdo states HCl addition is impractical in UHVCVD and that selective growth on Si₃N₄ fails without HCl. But this is a teaching away only from UHVCVD with chloride, not from the doping technique or from RPCVD — it is more accurately the motivation to change reactors. Under KSR, "the fact that the inventor was the first to recognize the problem is not the inventive contribution"; a teaching away requires that the prior art's criticism actually direct a POSITA elsewhere (In re Fulton‑type analysis).
2. The Langdo thesis may be the inventor's own work. Because it is not "by others," pre‑AIA §102(a) coverage is doubtful, and its 2001 issue date falls after the 2001‑06‑10 §102(b) critical date. Practically, this means the primary reference must be used as an applicant admission (it is discussed in the specification and incorporated by reference) and/or the examiner must locate independent pre‑2001‑06‑10 art for the in‑situ‑doping‑suppresses‑faceting teaching. This is the single most important vulnerability of the §103 case as framed by the page's references.
3. Criticality of the >5 Torr limitation. The patent could argue that facet suppression by doping was demonstrated only in high‑vacuum, low‑pressure conditions and that its transfer to torr‑level APCVD/RPCVD was unexpected. The problem: the '449 specification presents no RPCVD comparative data; the only XTEM evidence (FIGS. 1 and 3) is from Langdo's UHVCVD work. Absent data, the argument collapses into attorney argument.
4. Secondary considerations. The family is flagged on the page for "First worldwide family litigation filed" (Darts‑ip). I could not confirm from the page which proceedings are involved, and I could not verify any specific invalidity holding in the searches run. If a patent owner can show a nexus to commercial success, long‑felt need, or failure of others (e.g., failed attempts to obtain facetless SEG with nitride spacers in commercial RPCVD), those Graham factors are the strongest available rebuttal. Note that the earlier spacer‑undercut approach is described in the Background as having been proposed but as suffering from stringent geometric requirements and thin‑spacer incompatibility — that is useful "failure of others"/"long‑felt need" material.

5. Bottom line

• Claim 1 is highly vulnerable to §103 over (Langdo thesis + the Applicant's admitted prior art of facetless SEG in commercial LPCVD/APCVD), with Kummer et al. supplying commercial/high‑rate/low‑temperature CVD and single‑wafer reactor context (MPEP 2143 rationales (A), (C), (F) and KSR). The only element absent from Langdo, ">5 Torr," follows from the admitted commercial‑reactor platform and is unsupported by any criticality data in the specification.
• Claims 2–14, 21–22, 24–52, 61 are also likely obvious, being conventional process parameters, spacer stacks, substrates, and SALICIDE contacts admitted in the Background itself.
• The best candidates for non‑obviousness are the dependency chains that fix the combination of chloride‑based SiGe SEG at torr‑level pressure with p‑type (boron) in‑situ facet‑suppression doping below CMOS counter‑doping levels, on a nitride‑containing commercial spacer stack, in a strained‑Si/SOI substrate — e.g., claims 15–20, 23, 53–55, 56–60, 62–63. Even these, however, read largely as a predictable overlap of Langdo's doping technique, the admitted HCl/nitride selectivity chemistry, and WO 01/22482/Kummer process windows.
• Evidentiary gap to close: the page provides no backward "References Cited" list and no examiner citations. A complete opinion requires (i) the 10/458,544 and 11/103,681 file wrappers/IDS, (ii) confirmation of the earliest U.S. filing date in the US 8,586,452 chain (priority 2002‑06‑07, application 13/227,077 filed 2011‑09‑07) to test a §102(e) date, and (iii) any pre‑2001‑06‑10 third‑party publication independently teaching in‑situ‑doping facet suppression in low‑pressure epitaxy — which would remove the "inventor's own work" weakness of the Langdo‑based ground.

Caveat: this is a technical obviousness assessment based on the reference content on the fetched Google Patents page and the sources cited above; it is not a legal opinion or a validity determination.