US 6881632

I'll search for the specific patent number across USPTO and CAFC sources, then assemble the summary.

Let me run more targeted searches for the specific number and for CAFC 2026 dockets.

US Patent 6,881,632 — Identification Summary

Scope and method note. I searched for the exact number 6,881,632 (and the unpunctuated form 6881632) across publicly indexed USPTO-derived data (Google Patents, uspto.report, patent-family citations), the Unified Patents/Google Patents litigation links, and general web/legal sources for a CAFC 2026 docket. I did not obtain a live, queryable read of USPTO PatentCenter/PAIR or the Federal Circuit's PACER docket in this session, and I did not find any Federal Circuit docket entry (2026 or otherwise) naming this patent. My summary of the patent itself is grounded in the authoritative full text supplied, which is the Google Patents/patent-office copy.

1. Bibliographic record (authoritative, from the full text)

2. Abstract (verbatim)

"A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si₁₋ₓGeₓ layer on the Si substrate, and a strained surface layer on said relaxed Si₁₋ₓGeₓ layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si₁₋ₓGeₓ layer on the Si substrate, and a strained layer on the relaxed Si₁₋ₓGeₓ layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit."

3. Plain-language overview of the independent claims

Claim 1 — Method of fabricating a CMOS inverter

A manufacturing method with two steps:

1. Provide a heterostructure built from: a silicon substrate → a Si₁₋ₓGeₓ (silicon-germanium) layer on it → a strained layer on top of that. Two roughness conditions must be met: an interface located between the strained layer and the Si substrate must exhibit roughness less than 1 nm, and as a consequence the strained layer's own surface must also be less than 1 nm rough.
2. Integrate a pMOSFET and an nMOSFET into that heterostructure, where both the p-channel and the n-channel are formed in the strained surface layer — i.e., both transistors are surface-channel devices sharing one strained layer.

In plain terms: make a very flat strained-silicon-on-relaxed-SiGe wafer, then build both halves of a CMOS inverter (the pull-up PMOS and the pull-down NMOS) in that same strained surface film. The novelty as drafted sits almost entirely in the sub-1-nm roughness element; the SiGe/strained-Si stack and CMOS pairing were known.

Claim 5 — Method of fabricating an integrated circuit

A related but broader method:

1. Provide a heterostructure having a Si substrate and a strained layer thereover, the strained layer exhibiting surface roughness less than 1 nm (note: no explicit interface-roughness recital, and no SiGe layer expressly required in the claim as issued).
2. Form a p transistor and an n transistor in that heterostructure, where the strained layer comprises the channel of at least one of the transistors (not necessarily both, unlike claim 1), and the two transistors are interconnected in a CMOS circuit.

In plain terms: a broader claim covering the general idea of making CMOS (any CMOS circuit, including logic gates) in a very flat strained layer — but it only requires the strained layer to be the channel of one of the two device types.

Dependent claims add: relaxed SiGe layer (2); underlying insulator / SOI, including SiGe-on-insulator (3, 6); Ge fraction 0.1 < x < 0.5 (4, 9); a graded SiGe buffer between the SiGe layer and the substrate (7); strained layer comprises Si (8); the CMOS circuit is a logic gate — NOR (11), XOR (12), NAND (13); PMOS as pull-up and NMOS as pull-down (14); a Si₁₋ₓGeₓ layer below the strained layer (15); and an unexposed (buried) face of the strained layer with roughness < 1 nm (16).

4. CAFC 2026 docket search — result

No Federal Circuit appeal naming US 6,881,632 was found. Specifically:

• My targeted searches for "6,881,632" / "6881632" combined with Federal Circuit / CAFC / appeal returned no docket, opinion, or briefing identifying this patent as the subject of a Federal Circuit case — in 2026 or in any year.
• This is consistent with the previously-generated litigation and PTAB sections: the only adversarial record on this patent is the 2005–2007 AmberWave Systems Corp. v. Intel Corp. dispute (E.D. Tex. 2:05-cv-00321, transferred to D. Del. 1:05-cv-00837), settled 2007-03-05 with no judgment and no appeal. The patent then expired 2021-06-19. There is accordingly no live controversy that would generate a 2026 appeal, and none is docketed.
• Important caveat: the fact that no docket surfaced is not, by itself, proof that none exists. I did not query the Federal Circuit's own PACER/CMECF docket system directly, so a negative finding here should be independently re-verified at https://cafc.uscourts.gov (CM/ECF / oral argument and opinion archives) using the full number.

False positives to avoid when searching "'632"

My searches repeatedly surfaced unrelated patents that share the "'632" shorthand — a real hazard for a docket lookup:

None of these is US 6,881,632.

5. Uncertainty and gaps (stated plainly)

• High confidence: title, inventors, assignee chain (AmberWave → TSMC), application/filing/issue dates, priority date, and claim text — all taken from the authoritative full text.
• High confidence: the 2005–2007 Intel litigation and the 2007 settlement (corroborated by Chinese-language and English press reports in my searches, e.g. the Chinese report stating AmberWave sued Intel in 2005 over US 6881632 and US 6,831,292).
• Lower confidence / not verified: (a) whether a CAFC 2026 docket truly does not exist — I could not query the court's docket system directly; (b) whether any ex parte reexamination, reissue, or certificate exists in the file wrapper (I found none, but absence of a search hit is not proof of absence); (c) the exact expiration mechanics (terminal disclaimer, any PTA) — I have used the anticipated 2021-06-19 date from the record rather than a PatentCenter-confirmed term calculation; (d) PTAB status of sibling family member US 9,219,065, which I have not verified.
• One minor source conflict, flagged not harmonized: a Chinese press item dates AmberWave's founding to 1999, whereas the previously-generated assignment section cites 1998. This affects only corporate background, not any patent data.

Primary sources consulted:

• https://patents.google.com/patent/US6881632/en (authoritative full text; bibliographic and legal-events data)
• https://uspto.report/patent/grant/6,881,632 (cited references and foreign citation list)
• https://patents.google.com/patent/WO2002013262A3/en and https://patents.google.com/patent/[US6329063](/patent/US6329063) (family/citation cross-references confirming number 6881632)
• Chinese-language litigation press accounts (iianews.com, bjta.com.cn) confirming the 2005 AmberWave v. Intel suits over US 6881632 and US 6,831,292

Recommended verification steps: (1) run 6,881,632 — not "'632" — against Federal Circuit CM/ECF and CourtListener for 2026; (2) pull the file wrapper at USPTO PatentCenter (https://patentcenter.uspto.gov) to confirm expiration/terminal disclaimer and rule out reexamination/reissue; (3) re-check the assignment reel/frame and execution dates at https://assignmentcenter.uspto.gov.

I'll search litigation databases for this specific patent number.

Litigation Report — U.S. Patent No. 6,881,632

Scope and method. I searched for the literal identifier 6,881,632 and for the assignee/patentee names tied to it (AmberWave Systems Corp., TSMC), then cross-checked every hit at the case level rather than by patent shorthand. Because "'632" is badly over-loaded in this space (see §4), I verified each candidate case against the patent title, the parties, and the date. Bottom line: one infringement action was ever filed on this patent, and it was transferred, consolidated, and settled without any merits judgment.

1. Results table — cases in which US 6,881,632 was a patent-in-suit

That is the complete list. No other case — state, federal, ITC, or foreign — is on record asserting or adjudicating this patent.

2. Case detail

Case 1 — AmberWave Systems Corp. v. Intel Corp., 2:05-cv-00321 (E.D. Tex.)

• Cause of action: patent infringement of US 6,881,632 only. Accused products: Intel's 90-nm strained-silicon Pentium microprocessors (Prescott-generation). Cause pleaded as willful infringement; jury demand.
• Filing date: July 15, 2005 — consistent across the transfer opinion, the Delaware opinion, and contemporaneous press (CNET, EE Times, InformationWeek, Compound Semiconductor). Note that some coverage is datelined July 18, 2005 (the date the company announced it); the docket filing date is July 15, 2005.
• Pre-filing context: AmberWave sent Intel a cease-and-desist letter May 9, 2005; Intel filed a Delaware DJ action on May 17, 2005 (on the '292 patent, not the '632); AmberWave filed its answer and '292 counterclaim July 15, 2005, the same day it sued on the '632 in Texas.
• Key ruling: AmberWave Systems Corp. v. Intel Corp., No. 2:05-CV-321 (E.D. Tex. Nov. 1, 2005) — Judge Davis granted Intel's motion to transfer under the first-to-file rule. The opinion states: *"AmberWave Systems Corporation brought this suit on July 15, 2005 accusing Intel Corporation of infringing U.S. Patent No. 6,881,632… The '632 patent teaches a method of constructing inverters and other circuits using strained semiconductor transistors."* He found the '632 and '292 patents "do not raise identical issues, but the subject matter is closely related" and that the same Intel products were accused in both.
• Intel's answer (Sept. 2, 2005) in that docket raised the substantive defenses that were never adjudicated: invalidity under 35 U.S.C. §§ 101 et seq.; double patenting; improper inventorship "maintained with deceptive intent"; unclean hands; laches/prosecution laches; non-infringement; no willfulness. None of these was ever ruled on.
• Outcome: transferred out; no merits disposition in E.D. Tex.
• Sources: https://www.courtlistener.com/opinion/[8759735](/patent/8759735)/intel-corp-v-amberwave-systems-corp/ ; http://g.casetext.com/case/amberwave-systems-corp-v-intel-corporation

Case 2 — AmberWave Systems Corp. v. Intel Corp., 1:05-cv-00837-MPT (D. Del.)

• This is the same '632 action, transferred in from Texas on Nov. 1, 2005 and docketed in Delaware as C.A. No. 05-837. AmberWave's counsel of record included Jack B. Blumenfeld (Morris, Nichols, Arsht & Tunnell) with Irell & Manella LLP as of counsel.
• Consolidation context (necessary to read the outcome): Judge Jordan's court was already handling Intel Corp. v. AmberWave Systems Corp., C.A. No. 05-301-KAJ (DJ of non-infringement of the '292 patent, filed 2005-05-17) and C.A. No. 05-682-KAJ (DJ on the '371 patent, filed 2005-09-20). In Intel Corp. v. AmberWave Systems Corp., 233 F.R.D. 416 (D. Del. 2005), the court granted Intel leave to supplement and observed it "will already be dealing with the '292 and the '632 patents." The cases were consolidated in the Delaware court in February 2006. The '292 and '371 DJ/counterclaim cases are related but are not suits on the '632 patent — I list them only because they are the reason the '632 case ended where and how it did.
• Outcome — settlement, March 5, 2007: Intel and AmberWave announced settlement of all pending suits over AmberWave's strained-silicon portfolio. Intel received a license to all AmberWave patents and applications existing then or filed during a 10-year term, with license payments over the term; other terms confidential. The court actions were then dismissed. There is no holding on the validity, enforceability, or infringement of any claim of the '632 patent.
• Sources: https://insight.rpxcorp.com/litigation/dedce-35740-amberwave-systems-v-intel ; https://www.eetimes.com/intel-settles-strained-silicon-litigation/ ; https://pcper.com/2007/03/intel-and-amberwave-systems-corporation-announce-settlement/ ; https://www.cnet.com/tech/tech-industry/intel-amberwave-settle-patent-suit/

3. What does not exist (searched, not found)

• No post-2010 assertion. The patent was assigned to TSMC on 2010-01-26; after that there is no infringement suit, no ITC action, and no demand-and-file campaign naming this patent that I could locate. The claim has been unasserted since the 2007 settlement.
• No PTAB proceeding — no IPR, PGR, or CBM ever petitioned against 6,881,632 (consistent with the earlier PTAB section of this analysis; no petitioner work product exists to borrow).
• No Federal Circuit appeal on the '632 patent. The 2005–2007 dispute ended by settlement, so nothing was appealed. I found no CAFC docket naming this patent.
• No ex parte reexamination or reissue surfaced in my searches (stated as an absence-of-finding, not proof of absence).

4. Critical disambiguation — patents and cases that are NOT US 6,881,632

Generic searches for "6881632" or "'632" return several unrelated matters. I confirmed each is a different patent:

No litigation report should merge any of the above with US 6,881,632.

5. Bottom line

US 6,881,632 has exactly one litigation history: AmberWave Systems Corp. v. Intel Corp., filed 2005-07-15 in E.D. Tex. (2:05-cv-00321) and transferred 2005-11-01 to the D. Del. (1:05-cv-00837), where it was consolidated with Intel's '292/'371 declaratory-judgment actions and settled on 2007-03-05 via a 10-year Intel license to AmberWave's portfolio. Outcome: settlement/dismissal; no adjudication of validity or infringement. The patent subsequently passed to TSMC (2010), was never asserted again, and expired 2021-06-19 (Expired – Lifetime).

One correction to the prior "Patent summary" section: the earlier note that contemporaneous reporting said Intel "sued in July" in Delaware is imprecise — Intel's Delaware DJ action was filed May 17, 2005; July 15, 2005 is AmberWave's Texas filing (and its Delaware answer/counterclaim). See §2, Case 1. This does not change any conclusion, but the dates should be stated correctly in any filing.

Confidence and limits, stated plainly. High confidence on the two cases above, their numbers, dates, transfer, consolidation, and the 2007-03-05 settlement, because each is corroborated by a primary court document and multiple contemporaneous reports. I did not have authenticated PACER access, so docket entries between 2005 and 2007 (e.g., exact dismissal-entry dates and any sealed claim-construction or Markman activity) are unverified; and I cannot rule out an unfiled/never-docketed demand letter or a foreign counterpart action. No litigation, PTAB, or appeal activity on this patent after 2007 was found.

I'll verify the structured "no proceedings" result with targeted searches before writing up the analysis.

Confirming the negative finding and checking sibling patents and any third-party challenges.

Let me check the sibling family patent and any third-party challenges on the AmberWave/TSMC strained-silicon portfolio.

Proceedings overview

Total AIA trial proceedings on file: 0. The USPTO Open Data Portal (ODP) structured record supplied for US 6,881,632 returns no IPR, PGR, or CBM proceedings — no petitions filed, no institution decisions, no final written decisions, no settlements, and no PTAB appeals. Targeted web searches for "6,881,632" / "6881632" paired with IPR / inter partes review / PTAB / reexamination likewise returned zero PTAB dockets naming this patent. There is therefore no PTAB outcome table to report, no claim-level disposition, and no IPR certificate canceling any claim.

Bottom-line defensive posture: the patent is completely untested at the PTAB, and all 16 claims (1–16) stand exactly as issued. This is not "the patent survived two IPRs and is hardened" — it is the far rarer posture of a never-challenged patent. The reason it was never challenged is temporal and transactional, not evidentiary: the only window in which anyone had a motive to file (the 2005–2007 AmberWave v. Intel dispute) closed five years before AIA trials existed, and the parties had contractually barred themselves from Office challenges in any event (see below). The patent then changed hands to TSMC (2010-01-26) and expired on its anticipated date of 2021-06-19. For a defendant today, the operative defense is expiration and the § 286 damages window — not § 315(e)(2) estoppel, which does not exist here.

Proceedings on file

None — no AIA trial proceeding has ever been instituted on US 6,881,632

• Type: N/A (no IPR / PGR / CBM petition on record)
• Filed: N/A
• Status: No proceedings on file. The structured "PTAB proceedings on file" block (USPTO ODP) returns an empty set as of the most recent ingest; I found no contrary web evidence of an older or unindexed proceeding.
• Judge panel: N/A
• Petition grounds: N/A — no petition has been filed by any party
• Institution decision: N/A
• Final Written Decision: N/A — no claim of US 6,881,632 has been canceled, confirmed, or construed by the Board
• Settlement / termination: N/A
• Appeal: N/A — no FWD to appeal. (This is consistent with the earlier-generated Patent summary section, which searched for a CAFC 2026 docket naming this patent and also found none.)
• Defensive value: Without an FWD, there is no § 315(e)(2) estoppel and no IPR certificate. A defendant gets no free invalidity finding from the Board, but also faces no adverse PTAB ruling. The claims are presumptively valid and never narrowed by amendment — claim 1 still carries its "roughness less than 1 nm" interface and surface limitations as issued.

Why the PTAB docket is empty (documented, not inferred)

Three verifiable reasons explain the absence of AIA trials on this patent:

1. The controversy predates the AIA trial regime. The Board's AIA trial jurisdiction began 2012-09-16. AmberWave sued Intel on the '632 patent on 2005-07-15 (E.D. Tex. 2:05-cv-00321, transferred to D. Del. 1:05-cv-00837 on 2005-11-01), and all suits settled 2007-03-05. Every moment in which the patent was under adversarial attack occurred roughly five years before an IPR was even available. Sources: CourtListener — Intel Corp. v. AmberWave Systems Corp., 233 F.R.D. 416 (D. Del. 2005); Google Patents litigation links for US 6,881,632.

2. The parties contractually forebore from Office challenges. In the Delaware coordinated proceeding, the parties filed a Stipulation dated 2006-03-23 (Case 1:05-cv-00301-JJF-MPT, Doc. 95) stating that neither party "has filed or caused to be filed, directly or indirectly, a reexamination request pursuant to 35 U.S.C. § 302 or 35 U.S.C. § 311" on, inter alia, U.S. Patent Nos. 6,831,292, 6,881,632, and 6,946,371, and that neither party will file one or assist a third party to file one. Source: Stipulation, D. Del. Case 1:05-cv-00301-JJF-MPT, Doc. 95. Two caveats I want to state plainly: (a) in March 2006, "§ 311" referred to inter partes reexamination (the AIA IPR, also § 311, came later), so this was an anti-reexam pact, not an IPR pact; and (b) the agreement bound only the parties and their privies — it never bound third parties, who remained free to request reexamination at any time from issuance to expiry.

3. The patent was never asserted again. After the 2007 settlement and the 2010-01-26 assignment to TSMC, no assertion, ITC action, or third-party Office challenge appears in the record. The patent lapsed at its 2021-06-19 anticipated expiration. This is consistent with the previously-generated Litigation and Assignment sections (single-dispute history; no NPE in the chain).

Claims 1–16 status: UNTESTED at the PTAB. Zero canceled. Zero sustained. Zero amended.

Strategic summary

Claim status and estoppel landscape. Because no AIA trial was ever instituted, the entire § 315(e)(2) estoppel framework is inapplicable. There is no petitioner, no real party in interest, and no privy of any petitioner carrying an estoppel. Equally, there is no IPR certificate canceling claims under § 318(b), and no Board claim construction to borrow. A defendant today can raise § 102/§ 103 against all 16 claims using any prior art — including the two references flagged in the previously-generated Prior-art and Obviousness sections as the crux of a § 103 case: US 5,534,713 / EP 0 683 522 A2 (common strained-Si/SiGe CMOS heterostructure) combined with US 6,107,653 (Fitzgerald planarization driving relaxed-SiGe roughness below 1 nm). Those references were never tested by the Board on this patent, because the patent's litigation life ended before the Board had jurisdiction over it. Estoppel is a non-issue; the practical problem is that there is no live infringement to defend against.

Pattern signals. There is no serial-petitioner pattern (no petitioner at all), no patent-owner PTAB-appeal history (no FWD, hence no appeal — consistent with the 2026 CAFC search in the previously-generated Patent summary section), and no defensive aggregator in the chain. Per the previously-generated Assignment analysis, the chain is inventors → AmberWave → TSMC, terminating at an operating foundry with no NPE-named entity anywhere. Unified Patents, RPX, AST, and LOT appear nowhere in this patent's ownership or challenge record. A company that wanted to pre-empt this patent would have had to do so as a third-party requester — not via IPR, but via ex parte reexamination under § 302, which remained available throughout the patent's life and was never invoked.

The expiration point is the whole story. US 6,881,632 is Expired – Lifetime with an anticipated expiration of 2021-06-19. That date constrains every remaining theory: infringement liability can only attach to acts on or before that date, and the § 286 six-year lookback means the recoverable window is conduct from roughly 2015-06-19 through 2021-06-19 — a window that closes entirely around 2027-06-19. So a 2026 demand letter citing claim 1 is not "sanction-bait" in the PTAB sense (there is no canceled claim to cite); it is simply a claim whose damages tail is nearly run out, and whose sole viable invalidity route — because IPR is unavailable for an expired patent in any practical sense — is district court § 282 or ex parte reexamination of the historical claims.

Recommended next steps

If you are a defendant receiving a demand or complaint citing claims 1–16 today:

1. Lead with expiration, not with the PTAB. There is no FWD to point to, so do not build a defense narrative around an IPR you cannot cite. Cite instead the 2021-06-19 anticipated expiration and, separately, the § 286 six-year bar (35 U.S.C. § 286) — the record shows no assertion between 2007 and expiry, so the recoverable damages window is bounded and shrinking. The authoritative bibliographic/status source is Google Patents — US 6,881,632; confirm the term calculation and any terminal disclaimer at USPTO PatentCenter.
2. Attack any surviving claim on the merits using untested art. Because no estoppel attaches and no claim has ever been construed by the Board, the § 103 combination identified in the Obviousness section — US 5,534,713 + US 6,107,653 — is fully available. It has never been adjudicated anywhere: the 2005–2007 case settled with no judgment on infringement, validity, or enforceability (per the Litigation section), and no Office proceeding ever considered it.
3. Confirm there is no unindexed Office proceeding. The ODP result is a negative finding from a structured dataset, not a docket pull. Verify independently that no ex parte reexamination, inter partes reexamination, reissue, or certificate of correction exists in the file wrapper — check the "Continuity Data" / "Post-Grant" tabs at USPTO PatentCenter and search the PTAB's E2E / Patent Trial and Appeal Board (PTAB) Decisions system by the full number 6,881,632. An IPR certificate would be the only thing that could have canceled claims, and none is reflected in the record I retrieved.
4. Note the one family member I could not verify. The later-issuing sibling US 9,219,065 B2 (application 12/573,589, same 2000-12-04 priority) has a different claim set and a longer life than the '632 patent. My searches for PTAB activity on the '219,065 patent were inconclusive (results were dominated by the unrelated US 9,313,065 and other similarly numbered patents). This gap was flagged in the previously-generated Patent summary section as well and should be closed by a number-specific check, since any challenge activity there does not transfer estoppel or validity findings to US 6,881,632.
5. If you are the patent owner (TSMC) side: the absence of any IPR is a genuine asset in the sense that no claim has been canceled or narrowed. But it is not leverage you can use in 2026 — the patent's enforceable damages window is nearly closed, and there is no pending litigation to attach it to.

One contradiction to flag, per the operating rules: the 2006-03-23 stipulation is sometimes read as evidence that the parties "could not" be challenged at the PTAB. That is wrong on the law: it was a private agreement between Intel and AmberWave addressing ex parte and inter partes reexamination, signed six years before AIA trials existed, and binding on no third party. Treat it as historical color explaining the thin post-grant record — not as a bar, an estoppel, or a defense available to anyone today.

Primary sources for this section:

• USPTO Open Data Portal structured "PTAB proceedings on file" block for US 6,881,632 — empty set (canonical)
• Stipulation, D. Del. Case 1:05-cv-00301-JJF-MPT, Doc. 95, filed 2006-03-23 (parties' no-reexam agreement covering the '632 patent)
• CourtListener — Intel Corp. v. AmberWave Systems Corp., 233 F.R.D. 416 (D. Del. 2005) (litigation timeline placing the '632 dispute in 2005–2007)
• Google Patents — US 6,881,632 B2 (litigation links; status "Expired – Lifetime"; anticipated expiration 2021-06-19)

I'll research the assignment record for US 6881632 across USPTO Assignment Center, Google Patents legal events, and related sources.

Let me search more specifically for the assignment records and reel/frame data.

Inventors

Pattern notes. No unusual inventor-side signal is present. There is no evidence of all named inventors departing the original assignee within 12 months of filing (the classic precursor to a portfolio fire-sale). To the contrary, the invention stayed with AmberWave for roughly seven years after filing (2003 continuation → 2010 transfer), and Fitzgerald's AmberWave relationship persisted through the company's later ART/packaging research (the AmberWave fact sheet advertises 150+ issued/pending patents and an acquisition of Aonex Technologies). One caveat on the historical record: I did not verify Gerrish's or Fitzgerald's exact titles or separation dates; only their roles as named assignors are documented.

Original assignee

AmberWave Systems Corporation (Salem, New Hampshire). Named on the issued patent, and the entity to which both inventors assigned.

• Product embodying the claims? No — not in the literal sense. AmberWave was not a commercial chipmaker. Its own fact sheet describes it as "a materials research science company with an intellectual property (IP) business model," which "patents and licenses technologies." It operated a 30,000 sq-ft facility with a class-10 clean room for epitaxy/metrology demonstrations, and it licensed strained silicon to Intel and others. It did not sell CMOS inverters; it monetized the method claims by licensing.
• Primary line of business: R&D and IP licensing of advanced semiconductor materials (strained silicon; later Aspect Ratio Trapping, III-V-on-Si, and packaging).
• Current status: Wound down as a patent filer around 2010. Its patent portfolio was assigned to Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) by the recording of 2010-01-26 (per the Google Patents legal-events block). A separate study of TSMC's external patent acquisitions places "AMBERWAVE SYS" among its principal assignors in the 2006–2010 window, consistent with an asset/portfolio transfer rather than a continuing operating business. I did not confirm via an SEC filing or corporate registry whether this was a stock acquisition of AmberWave or an outright portfolio sale — treat that characterization as unverified.

Assignment timeline

Data limitation stated plainly. A live, itemized pull from USPTO Assignment Center (https://assignmentcenter.uspto.gov/) was not obtained in this session — I exhausted my retrieval budget before the Assignment Center returned a record set. I therefore did not capture reel/frame numbers or the correspondent of record, and I will not fabricate them. What follows is drawn from the authoritative legal-events block of the patent's own full text (Google Patents, which mirrors the USPTO assignment record). There are recorded assignments for this patent — so this is not the "no records / original assignee still owns it" case — but the granular reel/frame and correspondent fields are marked [not retrieved] pending a direct Assignment Center pull.

• 2003-07-01 (executed date not retrieved) / recorded 2003-07-01 — Reel/Frame [not retrieved]

  • Conveyance: Assignment of assignors' interest (inventor → company)
  • Assignor: Nicole Gerrish; Eugene A. Fitzgerald
  • Assignee: AMBERWAVE SYSTEM CORPORATION (note the singular "SYSTEM" as recorded)
  • Correspondent: [not retrieved]
  • Context: Original inventors' assignment to the company, recorded contemporaneously with the 2003-07-01 filing of continuation 10/611,739. Flag: the recordation date coincides exactly with the continuation's filing date, which is typical of a re-recording made to perfect title in a new continuation.

• 2003-11-24 (executed date not retrieved) / recorded 2003-11-24 — Reel/Frame [not retrieved]

  • Conveyance: Assignment of assignors' interest (recorded as a "reassignment")
  • Assignor: Eugene A. Fitzgerald; Nicole Gerrish
  • Assignee: AMBERWAVE SYSTEMS CORPORATION (now the plural "SYSTEMS")
  • Correspondent: [not retrieved]
  • Context: A second, near-duplicate recording within five months, changing the assignee name from "AMBERWAVE SYSTEM CORPORATION" to "AMBERWAVE SYSTEMS CORPORATION." This is consistent with a corrective/name-correction recording rather than a substantive transfer — but I cannot confirm that without the underlying document. It is not a cascading-transfer signal (both entries name the same company).

• 2010-01-26 (executed date not retrieved) / recorded 2010-01-26 — Reel/Frame [not retrieved]

  • Conveyance: Assignment (portfolio/asset transfer)
  • Assignor: AMBERWAVE SYSTEMS CORPORATION
  • Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (TSMC)
  • Correspondent: [not retrieved]
  • Context: Portfolio acquisition by an operating manufacturer. Coincides with the end of AmberWave's patent-filing activity.

Two important negatives:

1. No post-2007 assertion-driven transfer. The chain does not show a transfer arranged for enforcement — the only transfer after the 2005–2007 Intel litigation is the 2010 sale to TSMC.
2. No chained LLC cascade. There is exactly one corporate-to-corporate transfer (AmberWave → TSMC), with no intermediate holding/LLC entities.

Timeline diagram

timeline
    title Ownership of US 6881632
    2000 : Provisional 60250985 filed
    2001 : Parent app 09884172 filed
    2003 : Continuation 10611739 filed
         : Inventors assign to AmberWave
         : AmberWave name corrected Nov 24
    2005 : Patent issues Apr 19
         : AmberWave sues Intel in Texas
    2007 : Intel settles and takes license
    2010 : Assigned to TSMC Jan 26
    2021 : Patent expires Jun 19

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only transfers are inventors → AmberWave Systems Corporation (2003) and AmberWave → TSMC (2010). Neither assignee is a single-purpose "IP/Holdings/Ventures" LLC; TSMC is a major operating foundry. No registered-agent address, no Delaware/Texas shell entity appears in the record.
2. Known asserter in the chain — Not present (with one nuance). Neither AmberWave nor TSMC appears on the enumerated public NPE lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Erich Spangenberg entities). The nuance: AmberWave did assert this patent (AmberWave Systems Corp. v. Intel Corp., E.D. Tex. 2:05-cv-00321, then D. Del. 1:05-cv-00837, settled 2007-03-05), and it did so as a licensing-only owner rather than a product seller. That is NPE-adjacent behavior, but AmberWave was a genuine R&D company (facility, staff, clean room), not a serial-assertion shell.
3. Repeat correspondent across the chain — Unclear / no data. Correspondent of record was [not retrieved] for any entry. I found no evidence of a recurring recording attorney, and I will not infer one. Note that this is a three-entry chain; even with the data, a two-appearance pattern would be weak.
4. Cascading transfers — Not present. There is a single corporate transfer (2010), not a sub-24-month chain of LLC-to-LLC assignments. The two 2003 entries are same-party duplicate/name-corrective recordings, not successive transfers.
5. Pre-litigation transfer — Not present. AmberWave owned the '632 continuously from the 2003 recordings through the 2005 Intel suit and the 2007 settlement. The earliest in-chain transfer predates the first suit by ~2 years; the TSMC transfer postdates the settlement by ~3 years.
6. Bankruptcy fire-sale — Not present / unclear. No bankruptcy sale is documented for AmberWave. The 2010 transfer reads as a negotiated portfolio acquisition by TSMC. I could not verify AmberWave's ultimate corporate disposition (dissolution vs. acquisition), so this signal is unclear rather than affirmatively negative — but there is no evidence of a Chapter 7/11 sale.
7. Privateering — Not present. Privateering means an operating company pushing patents to an NPE that sues the operating company's competitors. Here the direction is the opposite: the patent moved from a licensing company to an operating manufacturer. No evidence of an operating company funding assertions through a proxy.
8. Defensive aggregator (anti-NPE) — Not present. The chain terminates at TSMC, which is not RPX, AST, LOT Network, Unified Patents, or OIN. The patent has not been neutralized by a defensive aggregator; it simply expired (anticipated 2021-06-19).

Verdict

Operating-company assertion.

The ownership chain contains no shell entity, no known NPE/aggregator, no cascading LLC transfers, and no pre-litigation venue-engineering transfer. The patent passed from its inventors to AmberWave Systems Corporation (a real R&D-and-licensing company, per the 2003 recordings and the file's own assignee records) and then, by the 2010-01-26 recording, to Taiwan Semiconductor Manufacturing Company, Ltd. — an operating manufacturer. The only enforcement in the patent's history was AmberWave v. Intel (filed 2005-07-15; settled 2007-03-05), i.e., the company that developed the technology asserting against a direct competitor that used it. The one NPE-adjacent feature — AmberWave's licensing-only business model (it did not sell CMOS products) — is a real observation but is insufficient for an NPE verdict given AmberWave's genuine R&D operations, the absence of every enumerated shell/troll indicator, and the fact that the chain terminated at a product-shipping manufacturer rather than at an assertion vehicle. If a stricter taxonomy is applied that treats any non-practicing licensor's assertion as NPE-type, the most that could be supported is a single weak/moderate signal; I would not assign a confidence-bearing NPE verdict.

Verify the chain directly (reel/frame and correspondent require this): USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search by patent number 6,881,632; note that the legacy URLs assignment.uspto.gov / assignments.uspto.gov were scheduled for retirement on 2026-02-02). Cross-check the 2010 TSMC recording against TSMC's SEC filings and against RPX/Unified asserter directories. Flag my gaps explicitly: reel/frame numbers, execution dates, and correspondents were not retrieved in this session and remain the top verification items; the "corrective recording" reading of the 2003-11-24 entry is my inference, not a document-confirmed fact; and AmberWave's end-state (asset sale vs. acquisition) is unverified.

I'll build this on the prior-art citation list already in the record, but first verify the citation set and dates against live sources rather than relying solely on my earlier retrieval.

Good — the key references are verifying. Let me pull dates and disclosures for several more of the cited references I'll need to characterize.

Prior‑Art Analysis — US 6,881,632 B2

Step 1 — Number verification (per the strict "exact number only" rule). I searched the literal string 6881632 (and formatted forms 6,881,632 / US6881632B2). The only patent matching is:

Searches for the numeric strings returned no other patent bearing this number. Note as false‑positive traps in this number space (do not conflate): US 8,194,632 (Uniloc, IPR2020‑00463), US 6,843,632 (Hollander), US 6,891,633 (Ruby Sands), US D405,632 — none is US 6,881,632.

Step 2 — The citation set, and an important scope limit. The Google Patents record for the '632 lists "Citations (201)" with the header "* Cited by examiner, † Cited by third party." The authoritative full text supplied to me truncates that list at US 6,130,453. I can therefore characterize and date‑stamp the references the record exposes up to that point (≈110 entries), and I flag the remainder (US 6,13x,xxx onward) as not visible to me in this session. I have not invented entries to fill the gap. Where I only have a title/abstract (rather than full text), I say so.

Critical § 102 methodology note before the tables: anticipation requires a single reference to disclose every limitation of the claim, arranged as claimed. Under that rule, every dependent claim (2–4, 6–16) incorporates its independent claim, so no dependent claim can be anticipated by a reference that fails to anticipate claim 1 or claim 5. The analysis therefore collapses to two questions: (a) does any single reference disclose the sub‑1 nm roughness limitation (claims 1, 5, 16), and (b) does any single reference disclose both the n‑channel and p‑channel in the same strained surface layer (claim 1)? The answer to both is no, and I explain why below.

Group A — Strained‑Si/SiGe CMOS and heterostructure FETs (the only genuine § 102 candidates)

Group B — Graded buffers, SiGe/Si epitaxy, defect and roughness reduction

Group C — Layer transfer, bonding, and SOI/insulator platforms (relevant to claims 3, 6, 7, 12A–12E)

Group D — Peripheral/semiconductor‑adjacent references (mostly memory, display, gettering, and unrelated process art)

These appear in the (56) list but disclose nothing bearing on the strained‑Si CMOS inverter claims. I list them for completeness; none anticipates any claim, and I do not recommend spending diligence on them.

Date‑classification note (pre‑AIA § 102). Using the 2000‑12‑04 priority date: references published before 1999‑12‑04 are § 102(b) art; references published between 1999‑12‑04 and 2000‑12‑04 (e.g., US 6,111,267, US 6,110,549, WO 00/54338, EP 1 020 900) qualify only under § 102(a); US patents whose applications were filed before that date but granted later may also be § 102(e) art. I have not run a filing‑date‑vs‑grant‑date § 102(e) screen for every entry.

Synthesis: what the citations actually establish under § 102

Strict conclusion: no reference cited on the face of US 6,881,632 anticipates any claim of the patent.

1. The roughness limitation has no counterpart in the cited set. Claims 1, 5 and 16 all require < 1 nm roughness (at the buried interface and/or at the strained‑layer surface). The only cited reference that speaks to roughness at all is Fitzgerald's WO 98/59365 / US 6,107,653 — and its § 102 value is zero because it is a buffer‑layer materials patent, not a method of integrating a pMOSFET and an nMOSFET into a heterostructure. Under § 102 a reference must disclose the claimed method, not merely an ingredient of it.

2. No single reference discloses both channels in the same strained surface layer. US 5,534,713 comes closest (common layers shared by p‑ and n‑channel CMOS devices), but it teaches the p‑channel in a compressively strained layer while claim 1 requires both the pMOSFET and nMOSFET channels in the strained surface layer. US 5,155,571 puts its n‑ and p‑channels in separate isolated regions. Neither anticipates.

3. The dependency structure forecloses anticipation of the dependent claims. Because claims 2–4 and 6–16 each incorporate claim 1 or claim 5, a reference that cannot anticipate the independent claim cannot anticipate any claim that depends from it. The many "circuit‑level" references — US 5,808,344 (CMOS inverters), US 5,777,347 (vertical CMOS logic), and the NOR/NAND/XOR‑adjacent art for claims 10–13 — are insufficient standing alone; they disclose the gate topology, not the strained‑Si CMOS method with sub‑1 nm roughness.

4. Where each reference's real force lies. The cited set functions as a § 103 combination pool, not a § 102 set:

• US 5,534,713 + US 6,107,653 = the previously‑developed primary § 103 combination (common strained‑Si/SiGe CMOS heterostructure + CMP‑planarized graded buffer yielding ≲1 nm roughness, with the applicant's own specification supplying the motivation re: lithography yield).
• US 5,906,951 supplies claims 3, 6, 7 (insulator/graded buffer) — again § 103 only.
• US 6,111,267 supplies the claim 4/9 Ge‑fraction range (25–50 % ⊂ 0.1–0.5) — § 103 only.

I therefore respectfully depart from the framing of the request insofar as it presumes that some cited reference anticipates specific claims. On the record visible to me, the answer is that none does; the references are § 103 material, and the only § 102‑strength positions (if any) would have to come from art outside the (56) list — e.g., a pre‑1999 publication describing a planarized relaxed SiGe virtual substrate with a strained Si surface channel used simultaneously for nMOS and pMOS. I have not identified one.

Caveats and gaps (stated plainly)

• Truncated citation list. The supplied full text ends the "Citations (201)" table at US 6,130,453; roughly the last third of the examiner/third‑party citations (US 6,13x,xxx and later, plus any non‑patent literature) is not assessable from what I hold. Re‑pull the complete (56) list from USPTO PatentCenter (https://patentcenter.uspto.gov) or the US6881632B1/EN PDF front page to close this gap.
• Full‑text verification status. I verified full text for US 5,155,571, US 5,534,713, US 5,906,951, US 6,107,653/as‑WO98/59365, and the '632 itself. For the remainder I relied on the Google Patents citation metadata (title/assignee/priority/publication dates) and abstracts. US 5,461,243 and US 5,683,934 are title/abstract‑level only and should be pulled in full if either is to be relied on as more than cumulative art.
• No auto‑correction applied. Where an identifier in the record looks irregular (e.g., the "US 6,110,549 / US 6,103,559" adjacency above), I have flagged rather than silently fixed it, per the operating rule.
• Date basis. All "filed/published" pairs are taken verbatim from the Google Patents citation table (priority date | publication date). I have not independently confirmed each filing date against PAIR.

Verification links used: https://patents.google.com/patent/US6881632/en · https://patents.google.com/patent/US5534713 · https://patents.google.com/patent/[US5155571A](/patent/US5155571A)/en · https://uspto.report/patent/grant/[5155571](/patent/5155571) · https://uspto.report/patent/grant/[5,906,951](/patent/5906951) · https://patents.google.com/patent/[US5906951A](/patent/US5906951A)/en

I'll analyze the prior art references cited on this page to assess obviousness. Let me first gather details on the most relevant references.

Let me gather details on several more key references from the citation list.

Obviousness Analysis — U.S. Patent No. 6,881,632 B2

"Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS"
Assignee (current): Taiwan Semiconductor Manufacturing Co. (TSMC); Original: AmberWave Systems Corp.
Inventors: Eugene A. Fitzgerald, Nicole Gerrish
Effective priority: December 4, 2000 (provisional 60/250,985), via continuation of US09/884,172 (filed June 19, 2001)
Framework: pre‑AIA 35 U.S.C. § 103(a); Graham v. John Deere, 383 U.S. 1 (1966); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP § 2143.

1. Scope of the claims to be tested

The claims fall into three functional groups:

The only limitations that distinguish over the bulk of the art are (i) both channels (n and p) in the strained surface layer, and (ii) the numerical roughness limitations (< 1 nm at the buried interface and at the strained-layer surface). Everything else — Si substrate, Si₁₋ₓGeₓ layer, strained Si layer, p‑MOS + n‑MOS interconnection in a CMOS circuit/inverter — is squarely in the prior art.

2. The relevant prior art from the citation list (all pre‑date the Dec. 4, 2000 priority)

3. Combination 1 (primary): Ismail US 5,534,713 + Fitzgerald US 6,107,653

Renders claim 1 (and claims 2, 5, 8, 15) obvious.

What '713 teaches. A common layered heterostructure on a Si substrate containing a relaxed SiGe layer and a tensilely strained Si layer, with n‑ and p‑channel transistors integrated in that same heterostructure and interconnected to form CMOS circuits. That maps onto:

• "providing a heterostructure including a Si substrate, a Si₁₋ₓGeₓ layer on the Si substrate, and a strained layer on the Si₁₋ₓGeₓ layer" ✔
• "integrating a pMOSFET and an nMOSFET in the heterostructure … interconnected in a CMOS circuit" ✔ (claim 5)
• p‑channel as pull‑up / n‑channel as pull‑down (claim 14) ✔ (inherent in CMOS inverter topology; the specification at Fig. 4 says exactly this)

What '653 teaches. Growing a compositionally graded GeSi buffer on Si, planarizing the surface (CMP) to reduce roughness, then growing a device layer on the planarized surface. The reference reports RMS roughness values that, after planarization/regrowth, fall at or below ~1 nm (the '653 family and its Chinese counterpart describe the CMP surface as reaching ≈1 Å RMS).

The motivation to combine is express and strong. The challenged patent's own specification concedes the point:

"U.S. Pat. No. 6,107,653 issued to Fitzgerald, incorporated herein by reference, describes a method of planarization and regrowth that allows all devices on relaxed SiGe to possess a significantly flatter surface. This reduction in surface roughness is critical in the production of strained Si CMOS devices since it increases the yield for fine-line lithography." (col. describing FIG. 3)

That is an admission that (a) '653 is prior art, (b) a POSITA would look to it precisely when building CMOS on relaxed SiGe, and (c) the reason to combine — lithography yield — was known and articulated. Under KSR, a limitation that is the known, predictable result of a known process step applied to a known structure is obvious. The claims' "< 1 nm" numbers are therefore not a patentable distinction; they are the measured consequence of the CMP‑planarization step of '653 applied to the heterostructure of '713.

On "both channels in the strained surface layer." '713 (and its EP counterpart) frames the transistor as formed "with a silicon or silicon germanium layer under tension"—i.e., the strained layer of the common stack. Even if '713's illustrated embodiments emphasize buried‑channel PMOS, the claim language does not require comparable electron/hole mobility or a wholly surface‑channel device; the surface‑channel preference is a design choice among a finite number of identified, predictable options (KSR; In re Keller). Moreover, Candelaria '934 and Wang '571 both disclose strained surface/stressed channels, confirming that the surface‑channel option was known in the field.

4. Combination 2: Ismail '713 + Chu US 5,906,951 (+ optional '653)

Renders claims 3, 6, 7 obvious.

• Claim 3 ("heterostructure further comprises an underlying insulator layer") and claim 6 ("insulating layer below the strained layer") — supplied by Chu '951, which discloses a graded Si₁₋ᵧGeᵧ buffer, a relaxed SiGe layer, and a strained Si layer all standing on an insulating substrate (bonding + substrate removal), expressly for CMOS.
• Claim 7 ("SiGe graded buffer layer positioned between the relaxed Si₁₋ₓGeₓ layer and the Si substrate") — supplied verbatim by Chu '951 and by Fitzgerald '653 (graded GeSi buffer on Si).

Motivation: Both '713 and '951 are IBM patents in the same technical vein (strained Si/SiGe heterostructures for CMOS); '951 explicitly motivates the SOI variant by pointing out the conducting‑substrate problem and the SOI advantages, and the challenged patent's own specification lauds the "about an 18% performance improvement from the SOI architecture." A POSITA optimizing CMOS performance would combine the common‑layer CMOS stack of '713 with the SOI/graded‑buffer platform of '951 to gain junction‑capacitance and isolation benefits. Combining known prior‑art elements to obtain predictable advantages is obvious (KSR; MPEP § 2143).

5. Combination 3: + Fischer US 6,111,267 (and/or '713's own range)

Renders claims 4 and 9 obvious.

Claims 4 and 9 recite 0.1 < x < 0.5 for the Si₁₋ₓGeₓ layer.

• Fischer '267 expressly discloses a CMOS IC with a stressed SiGe layer where Ge is between 25 and 50% — squarely within 0.1–0.5.
• Wang '571 and Solomon '882 likewise describe Ge fractions spanning the same region (e.g., Ge₀.₂Si₀.₈).
• The challenged patent's own specification treats x = 0.2 and x = 0.3 as the operative embodiments and notes hole‑enhancement saturation "predicted to occur at a Ge concentration of about 40%."

A claimed numerical range is obvious where the prior art discloses values within or overlapping the range, or where routine optimization within a disclosed range would yield the claimed range (In re Peterson, 315 F.3d 1325 (Fed. Cir. 2003); In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990)). Fischer '267 meets this directly.

6. Combination 4 (alternative primary): Wang US 5,155,571 + '653 + '951

Also renders claims 1 and 5 obvious.

Wang '571 discloses complementary FET structures in which strained GeₓSi₁₋ₓ/Si layers form the carrier conduction channels of both the n‑channel and p‑channel devices, on a relaxed GeₓSi₁₋ₓ layer, expressly to "enhance and equalize current carrier mobilities" and for complementary logic. That is the structural core of the claims. Adding '653 (flat relaxed buffer) and '951 (SOI/graded buffer) supplies the roughness and insulator limitations with the same rationale set out above.

The fact that Wang '571 locates the n‑ and p‑channel devices in separate isolated regions, whereas the challenged claims place both channels in the same strained surface layer, does not defeat obviousness: the '713 reference already teaches a common layer stack shared by both transistor types, and the claimed architecture is the predictable union of '571's strained‑channel complementary devices with '713's common‑layer CMOS stack.

7. The remaining dependent claims

8. Anticipating and rebutting the likely non‑obviousness arguments

(a) "The art taught away from surface‑channel PMOS."
The applicant's specification argues that "the low hole mobility in surface channel devices has caused other researchers to move to higher mobility, buried channel devices for the PMOSFET." Even taking that at face value:

• The claims do not require the n and p channels to have comparable or balanced mobility; claim 1/5 recite only that the channels are (or include) the strained layer.
• Candelaria '934 and Wang '571 both disclose strained surface channel structures, so the art did not uniformly discourage surface channel.
• Where the reference teaches a range of options, selection of one predictable option is not inventive (KSR; In re Keller; In re Merck). A "teaching away" argument requires the reference to criticize, discredit, or otherwise discourage the claimed solution (In re Fulton); a mere preference for buried channels in some published work falls short.

(b) "The roughness values produce unexpected results."
There is no evidence in the record of an unexpected property attributable to the numerical roughness limitation. The specification links low roughness only to lithography yield — precisely the benefit '653 already discloses. A result that the prior art attributes to the same variable (surface roughness) cannot supply patentability (In re Boesch; MPEP § 716.02).

(c) "The claims require a common strained surface layer for both devices."
This is the strongest distinction, but it is squarely met by US 5,534,713, which discloses a plurality of layers common to both subsequently formed p‑ and n‑channel transistors, "which may be interconnected to form CMOS circuits." The combination of '713's common‑layer architecture with '653's planarized relaxed buffer yields every element of claim 1.

(d) KSR "predictable variations" reprise.
The claimed method consists entirely of known steps (graded SiGe epitaxy, CMP planarization, strained‑Si regrowth, CMOS transistor integration) applied to a known structure (relaxed SiGe‑on‑Si), yielding a predictable improvement (mobility enhancement). KSR teaches that "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill."

9. Conclusion

On the record of the cited art, claims 1 and 5 — the only independent claims — appear obvious under § 103(a). The combination of US 5,534,713 (which discloses the common‑layer strained‑Si/SiGe heterostructure with interconnected p‑ and n‑channel CMOS devices) with US 6,107,653 (which discloses the planarization/regrowth process that drives surface roughness below 1 nm and expressly identifies improved fine‑line lithography yield as the reason to planarize) supplies every element of the two independent claims. The remaining dependent claims add only conventional design choices (SOI platform, Ge fraction, pull‑up/pull‑down arrangement, selection of logic gate), each of which the cited art or the applicant's own specification treats as routine. The principal weakness of this prima facie case is evidentiary rather than legal: the exact roughness numbers attributed to the '653 process should be verified against the four corners of '653 itself (the family reports post‑CMP roughness in the ~1 Å–1 nm range) before relying on it to meet the "< 1 nm" limitation with certainty.

Claims/features I could not fully verify from retrieved text (stated explicitly): the complete disclosure contents of US 5,461,243 (IBM, "Substrate for tensilely strained semiconductor"), US 5,683,934 (Candelaria), and US 5,847,419 (Toshiba) were not retrievable in this session; my analysis relies on their titles/abstracts as surfaced in the page's citation list and should be supplemented with full‑text review if those references are to be used as primary art rather than cumulative support.