US 6470007

Summary of U.S. Patent 6,470,007 (US6470007B1)

Search note / methodology: I searched for the literal identifiers "6470007," "US6470007," and "6,470,007." Results returned only the correct patent (plus its family members and citing references). No CAFC 2026 docket entries were found in any search; I could not confirm any pending Federal Circuit appeal for this number and will flag that as unresolved.

Bibliographic data (verified against the issue record and Google Patents)

• Title: Interconnect system for fiber channel arbitrated loop including private loop devices
• Patent number: US 6,470,007 B1
• Inventor: Stuart B. Berman (Irvine, California)
• Original applicant/assignee at grant: Individual (Stuart B. Berman)
• Filing date: July 6, 2000 (Appl. No. 09/611,173)
• Issue date: October 22, 2002
• Priority date: February 18, 1997 (chain: continuation of 08/907,385, filed Aug. 7, 1997, now US 6,118,776, which is a continuation-in-part of 08/801,471, filed Feb. 18, 1997, now US 6,185,203)
• Status: Expired – Lifetime (anticipated expiration Feb. 18, 2017); subject to a terminal disclaimer (per the issue record)
• Classifications: Int. Cl. H04L 12/28; U.S. Cl. 370/351
• Number of claims: 137

Assignee chain (note of caution): Google Patents lists "Current Assignee" as Pantech Co Ltd and Avago Technologies International Sales Pte Ltd, which appears to reflect downstream assignments. The recorded chain per the assignment events includes Hyundai Syscomm (2004) → Vixel/Emulex Design & Manufacturing → Emulex → Avago (2015–2017). I cannot independently verify which entity holds current title, and the Google "current assignee" listing is not authoritative.

Abstract (condensed)

The invention provides methods and apparatus for Fibre Channel interconnection of multiple private loop devices through a Fibre Channel private loop device interconnect system (preferably a fabric or an intelligent bridging hub). The interconnect system includes routing filters that filter incoming Arbitrated Loop Physical Addresses (ALPAs) to decide which Fibre Channel frames must be routed through the fabric. It supports numerous topologies (e.g., redundant fabrics, cascaded fabrics). Also disclosed: a method of segmenting one logical loop into multiple physical Arbitrated Loops; a method of restricting attached devices to selected ALPA ranges during loop initialization; a method of resetting host loops when storage is added elsewhere; and SCSI-initiator handling in which PLOGI probes with no matching device receive a link-service reject (LS_RJT) from the interconnect system.

Independent claim 1 – verified text and plain-language overview

Verified text (from the issue record and FreePatentsOnline): Claim 1 is an apparatus claim reciting:

• a first Arbitrated Loop containing one or more private loop devices;
• a second device;
• a Fibre Channel private loop device interconnect system having:
  • a first port (port control module) coupled to the first Arbitrated Loop at a first link speed;
  • a second port (port control module) coupled to the second device at a second link speed, where the first and second link speeds are different;
  • each port control module containing a Fibre Channel Arbitrated Loop Port State Machine including an active L_Port implementing the Arbitrated Loop protocol (generation of ARBs, OPNs and Closes), the first loop port state machine providing a point-to-point connection between itself and a private loop device on the first Arbitrated Loop;
  • route determination apparatus for selecting a route between the port control modules; and
  • connectivity apparatus (switching fabric) coupled to the port control modules and route determination apparatus.

Plain language: Claim 1 covers a switch/hub system that lets Fibre Channel devices on an Arbitrated Loop (devices that only "speak" private-loop protocol) talk to another device through an interconnect box, where the two sides of the box can run at different link speeds, and each port runs an active loop state machine that generates loop primitives (ARB/OPN/CLS) to create point-to-point sessions with the attached loop devices; frames are switched between ports under route control.

Other independent claims – uncertainty disclosure

The patent has 137 claims, so there are almost certainly multiple additional independent claims beyond claim 1. Based on the specification's Summary of the Invention, the likely independent subject matter includes method claims for (a) segmenting a logical loop into physical loops, (b) ALPA range restriction during loop initialization, (c) resetting host ports on storage addition, (d) SCSI-initiator PLOGI probe handling with LS_RJT responses, and (e) an intelligent bridging hub apparatus. However, I was unable to retrieve the authoritative full text of those later independent claims (my searches returned claim 1 and dependent claims only, and the tool-call limit was reached before I could retrieve the complete claim set). I therefore cannot state the exact number, wording, or boundaries of the remaining independent claims with confidence — treat any description of them as inferred from the specification, not verified claim text.

CAFC / litigation status

• The Google Patents record flags the patent family as having litigation (Darts-ip family ID 25424009), but I found no 2026 CAFC docket entries for patent number 6470007 in my searches. This is an absence of found results, not a confirmation that no appeal exists.

The initial searches surfaced litigation only for other patents (e.g., Papst's 6,470,399 — a different patent number). Let me run more targeted searches for 6,470,007 specifically.

Litigation Involving US Patent 6,470,007

Based on my searches, US Patent 6,470,007 ("Interconnect system for fiber channel arbitrated loop including private loop devices," inventor Stuart B. Berman) is confirmed to have been asserted in at least the following two lawsuits, both brought in 2003 by Vixel Corporation (which owned the patent at the time via its CTO/inventor Berman's 1997 applications):

1. Vixel Corp. v. Brocade Communications Systems, Inc.

• Plaintiff: Vixel Corporation
• Defendant: Brocade Communications Systems, Inc.
• Jurisdiction: U.S. District Court for the Northern District of California
• Filing date: On or about May 23, 2003 (reported May 28, 2003, as filed "last Friday")
• Patents asserted: 6,185,203 ("Fibre Channel Switching Fabric"), 6,470,007, and 6,118,776 ("Methods and Apparatus for Fibre Channel Interconnection of Private Loop Devices")
• Accused products: Brocade SAN switching products, including SilkWorm features QuickLoop and Fabric Assist
• Status/outcome: Not confirmed from available sources. (Vixel later changed name/assigned rights through Emulex; the patent is now expired-lifetime per USPTO/Google Patents status.)

Source: https://prod.networkcomputing.com/data-center-networking/vixel-slings-suit-at-brocade

2. Vixel Corp. v. QLogic Corp.

• Plaintiff: Vixel Corporation
• Defendant: QLogic Corporation
• Jurisdiction: U.S. District Court for the District of Delaware
• Filing date: On or about February 28, 2003 ("the last day of February," per the report)
• Patents asserted: The reporting article describes the QLogic suit as involving "the very same patent" as the third patent in the Brocade suit — i.e., 6,118,776. The article does not explicitly confirm that 6,470,007 was asserted in the QLogic Delaware case; that particular patent is expressly confirmed only in the Brocade suit.
• Status/outcome: Not confirmed from available sources.

Source: https://prod.networkcomputing.com/data-center-networking/vixel-slings-suit-at-brocade

Corroborating note

The Google Patents record for US6470007B1 carries a "Family has litigation" flag and links to Darts-IP family 25424009 (https://patents.darts-ip.com/?family=25424009), which confirms at least one litigation event in this patent family but does not by itself identify the specific cases. That family also includes related patents 6,185,203 and 6,118,776, so the litigation flag may cover any of those.

Caveats

• I could not retrieve case numbers, docket entries, or final judgments/outcomes for either 2003 suit within the available search results. Case numbers such as the N.D. Cal. and D. Del. civil action numbers are not confirmed and should not be assumed.
• The patent's assignment history (Vixel → Curitell Communications/Vixel → Emulex Design & Manufacturing → Emulex Corp. → Avago/Broadcom) suggests later owners could have litigated it after 2004, but I found no confirmed post-2003 litigation specifically naming 6,470,007. Any such cases remain unverified.
• If you need definitive docket/outcome detail, the next step would be PACER lookups in N.D. Cal. (2003) and D. Del. (2003) under Vixel as plaintiff, or the Darts-IP litigation dataset behind the Google Patents link.

Proceedings overview

Total AIA trial proceedings on file: 0 — no Inter Partes Reviews, Post-Grant Reviews, or Covered Business Method reviews have ever been filed against US 6470007, and none are pending. The USPTO Open Data Portal ingest for this patent is empty, and targeted web searches surfaced no PTAB petition, institution decision, final written decision, or CAFC appeal bearing this patent number (the only litigation found is a pre-AIA 2003 district-court campaign by Vixel against Brocade and QLogic, which is not a PTAB proceeding). The bottom line for a defendant: the patent expired by operation of law on 2017-02-18 (status: "Expired - Lifetime"), and it has never been tested in an AIA trial — but because it is expired, no injunction and no post-2017 damages exposure exists; any current exposure is limited to alleged pre-expiry damages.

Per-proceeding analysis

There are no AIA trial proceedings to report. Accordingly, there are no judge panels, petition grounds, institution decisions, final written decisions, settlements, or Federal Circuit appeals of PTAB decisions to summarize. I am deliberately not inventing proceeding numbers, and I flag that one search attempt returned only unrelated content and a second was cut off before returning results — but nothing in any retrieved source (USPTO ODP, Google Patents, Justia, Unified Patents portal, or trade press) references an IPR/PGR/CBM on US 6470007.

For completeness, the patent's non-PTAB history includes:

• District court (pre-AIA, not a PTAB trial): Vixel Corp. sued Brocade Communications Systems in the Northern District of California in May 2003, asserting 6,185,203, 6,470,007, and 6,118,776 against SilkWorm switches (QuickLoop/Fabric Assist); a similar Vixel suit against QLogic was referenced in the same trade coverage. These actions predate the AIA (effective 2012-09-16) and are not AIA trial proceedings. I did not verify their final dispositions and will not speculate on them.
• Ownership chain: Individual (Berman) → Vixel/Curitell → Emulex Design & Manufacturing → Emulex → Avago Technologies (now part of Broadcom). Google Patents lists current assignee as Pantech Co Ltd / Avago Technologies International Sales Pte Ltd, which reflects a complex chain I have not independently verified.
• Status: Expired – Lifetime, with anticipated expiration listed as 2017-02-18 (20 years from the 1997-02-18 priority application).

Strategic summary

Claim-level status — CANCELED vs. SUSTAINED vs. UNTESTED. Because no IPR/PGR/CBM was ever instituted, no claims of 6470007 have been canceled or even examined by the PTAB. All claims are "UNTESTED" in the AIA-trial sense — but that framing is largely academic: the patent expired on 2017-02-18. Assertion of an expired patent supports no injunctive relief and no ongoing royalty, and post-expiry conduct cannot infringe. A defendant facing a demand letter today should treat the letter as at most a claim for pre-expiry damages (subject to the 6-year § 286 damages bar, which reaches back only to ~2020 for a 2017-02-18 expiry — meaning virtually the entire damages window is already time-barred). Indeed, with expiry in February 2017, the last date on which any infringing act could have occurred is more than six years before today (2026-09-09), so a § 286 time-bar defense likely eliminates all recoverable damages entirely.

Estoppel landscape. Section 315(e)(2) estoppel is a non-issue here because no IPR was ever instituted and no petitioner exists. For the same reason, there is no PTAB estoppel constraining any invalidity defenses a defendant could raise in district court — all prior-art grounds under §§ 102/103 remain fully available, subject only to the usual pre-AIA/AIA prior-art analysis dictated by the patent's 1997 effective filing date.

Pattern signals. No defensive aggregator (e.g., Unified Patents), no serial petitioner, and no PTAB-appeal pattern exists for this patent — because the patent's active enforcement era (Vixel v. Brocade/QLogic, ~2003) predates the AIA, and by the time IPR became available (2012-09-16), the patent was within roughly 4.5 years of natural expiry. The absence of IPRs is therefore unsurprising and not a signal of strength; it is a signal of vintage. Note also that the broader Berman fibre-channel family (6,185,203; 6,118,776; 7,012,914; 7,522,619; etc.) was litigated and continued via continuations into the 2010s, so if a demand letter cites a different family member that is still in force, the PTAB analysis would need to be redone for that specific patent — I have not verified PTAB activity on any of those.

Recommended next steps

1. If you are a defendant facing a demand letter citing US 6470007: There is no PTAB Final Written Decision to link because none exists. Instead, lead with the terminal facts: the patent is Expired – Lifetime as of 2017-02-18 (see the USPTO assignment/status record and Google Patents legal-status timeline for US6470007B1), so no injunction and no ongoing damages are available. Then run the § 286 clock: expiry more than six years ago means any claimed damages are time-barred unless the plaintiff can show a tolling theory — a motion to dismiss or early summary judgment on laches/statute-of-limitations grounds is the fastest exit.
2. Confirm the exact defendant product/accused timeframe before investing in validity work. If the accused activity is all post-2017, validity is irrelevant — the patent was dead. If the plaintiff somehow alleges pre-2017 activity, only then would §§ 102/103 prior art matter, and you are free to use any ground because no IPR estoppel exists. Given the 1997 priority date, pre-AIA § 102 (e.g., § 102(e)/(g) and on-sale/use bars) and § 103 art from the mid-1990s Fibre Channel standards (FC-AL, FC-PLDA, ANSI X3T11 drafts cited throughout the patent) are the natural ammunition — the patent's own Background section concedes the loop-topology limitations the "Stealth Mode" purportedly solved, which can frame an obviousness story.
3. Check the rest of the family before dismissing entirely. If the demand letter also cites a still-in-force continuation (e.g., 7,012,914; 7,522,619; 8,121,137; 8,780,912; 8,902,911; 8,831,022), the analysis changes completely: those are separate patents with separate terms, and an IPR petition on the live family member would be the appropriate vehicle. I did not verify PTAB activity on those patents and recommend a fresh ODP/PTAB API lookup for each number actually asserted.
4. Monitor for new filings anyway. The ODP note says its ingest may lag; PTAB E2E searches for "6470007" and the assignee names (Emulex/Avago/Broadcom) should be re-run at the time of any actual suit, and any newly surfaced proceeding should be checked against the § 315(b) one-year bar from service of the complaint.

Bottom line, stated plainly: No PTAB proceeding has ever touched US 6470007. That absence is not a sign the patent is strong — it is a sign the patent is old, expired, and was enforced in the pre-IPR era. A current defendant's best play is the expiry/statute-of-limitations defense, not an IPR.

I'll research the assignment record for US 6470007. Let me start with targeted searches.

The Google Patents events give me the chain, but I need reel/frame numbers and correspondents. Let me dig deeper.

Let me try to reach the USPTO Assignment Center data directly.

I was unable to retrieve reel/frame numbers or correspondent names before exhausting my search budget — the USPTO Assignment Center pages did not render through my available tooling, and free-text searches for "Curitell Communications," "Arcxel Technologies," and "Hyundai Syscomm" assignment records returned nothing usable. Rather than fabricate reel/frame entries or correspondent names, I reconstruct the chain from the assignment events indexed on the authoritative Google Patents record (which mirrors the USPTO assignment data), and I flag every gap explicitly.

Inventors

Pattern note (partial flag): There is no evidence of the classic "inventors depart within 12 months of filing" fire-sale precursor here, and no co-inventor team to disperse — this is a single-inventor portfolio. One genuine oddity is on the assignment side, not the inventor side: US 6,470,007 issued naming the assignee as "Individual" (Berman personally), whereas its two sibling patents issued to Vixel Corporation. Berman then had to execute a later corrective assignment to Arcxel Technologies in 2007 to repair the chain (see timeline). That is a chain-of-title defect pattern, not an inventor-departure pattern.

Original assignee

As issued (2002-10-22): "Individual" — Stuart B. Berman personally. This is the literal original-assignee designation on the face of US 6,470,007 and it is unusual: the two sibling patents in the same family (US 6,185,203 and US 6,118,776) issued to Vixel Corporation. The inventor personally held the 6,470,007 record until the 2007 corrective chain (Berman → Arcxel Technologies → Vixel Corporation).

• Primary line of business (Vixel Corporation, the de facto operating owner): Fibre Channel Arbitrated Loop hubs, switches, and SAN interconnect products — i.e., Vixel shipped products squarely in the field of the claims (loop hubs/switch fabrics), and it sued Brocade and QLogic as competitors in 2003.
• Current status of Vixel: Acquired by Emulex (the Vixel → Emulex Design & Manufacturing Corporation recording is dated 2004-05-19). Emulex was itself later acquired by Avago Technologies (the 2015-10-23 recording to Avago Technologies General IP (Singapore) Pte. Ltd.). Avago is now part of Broadcom. Vixel as an independent entity no longer exists.
• Caveat: I could not independently confirm whether the "Individual" listing reflects a deliberate retainage of 6,470,007 by Berman or an issuance error later cured by the 2007 Arcxel chain. The record shows the cure; it does not show the cause.

Assignment timeline

Data-limitations statement (read first): The events below are the fully enumerated assignment/legal events as indexed on the Google Patents record for US6470007B1 (https://patents.google.com/patent/US6470007/en), which mirrors USPTO assignment data. Reel/frame numbers and correspondent-of-record names are NOT present in the records I was able to retrieve, and I will not invent them. Each entry therefore carries a [reel/frame: not retrieved] and [correspondent: not retrieved] tag. The single date shown per event is the USPTO recording/assignment date as indexed; I did not retrieve separate execution dates.

• 2004-04-05 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: Assignment of assignors' interest
  • Assignor: HYUNDAI SYSCOMM, INC.
  • Assignee: CURITELL COMMUNICATIONS INC.
  • Correspondent: [not retrieved]
  • Context: Anomalous / unexplained. This link does not fit the Berman–Vixel–Emulex chain and appears in the recorded events for this patent. I could not retrieve any corroborating source for Hyundai Syscomm's connection to this patent. Flag as unclear — do not treat as a fire-sale without confirmation.

• 2004-05-19 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: Change of Name
  • Assignor: VIXEL CORPORATION
  • Assignee: EMULEX DESIGN & MANUFACTURING CORPORATION
  • Correspondent: [not retrieved]
  • Context: Acquisition / internal reorg. Emulex's absorption and renaming of Vixel post-acquisition (recorded as a Change of Name even though these are distinct legal entities).

• 2007-02-27 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: Assignment of assignors' interest
  • Assignor: BERMAN, STUART B.
  • Assignee: ARCXEL TECHNOLOGIES, INC.
  • Correspondent: [not retrieved]
  • Context: Chain-of-title cleanup. Corrective assignment curing the fact that 6,470,007 had issued to Berman personally.

• 2007-02-27 (recorded; same day as above) — Reel / [not retrieved]

  • Conveyance: Assignment of assignors' interest
  • Assignor: ARCXEL TECHNOLOGIES, INC.
  • Assignee: VIXEL CORPORATION
  • Correspondent: [not retrieved]
  • Context: Chain-of-title cleanup (second leg). Same-day two-hop transfer Berman → Arcxel → Vixel.

• 2014-01-17 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: Assignment of assignors' interest
  • Assignor: EMULEX DESIGN AND MANUFACTURING CORPORATION
  • Assignee: EMULEX CORPORATION
  • Correspondent: [not retrieved]
  • Context: Internal reorg.

• 2015-10-23 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: Assignment of assignors' interest
  • Assignor: EMULEX CORPORATION
  • Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
  • Correspondent: [not retrieved]
  • Context: Acquisition. Emulex assets folded into Avago (now Broadcom).

• 2016-02-11 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: PATENT SECURITY AGREEMENT
  • Assignor: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (and affiliated Avago entities)
  • Assignee: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
  • Correspondent: [not retrieved]
  • Context: Securitization. Collateral pledge of the patent as part of a corporate credit facility — a hallmark of an operating company, not an NPE.

• 2017-02-03 (recorded; execution date not retrieved) — Reel / [not retrieved]

  • Conveyance: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS
  • Assignor: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
  • Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
  • Correspondent: [not retrieved]
  • Context: Securitization release / reorg. Lien released; lien re-perfected under the successor credit facility.

Note on current assignee: Google Patents lists the current assignee as Pantech Co Ltd and Avago Technologies International Sales Pte Ltd. The Pantech listing is unexplained by any assignment event above and I could not verify it. Per my operating instructions I do not auto-correct it, but I flag it as an unverified outlier.

Timeline diagram

timeline
    title Ownership of US 6470007
    1997 : Priority application filed
         : Berman named sole inventor
    2000 : Continuation application filed
    2002 : Patent issues to Stuart B Berman
         : Original assignee listed as Individual
    2004 : Hyundai Syscomm to Curitell Communications
         : Vixel to Emulex Design and Manufacturing
    2007 : Berman to Arcxel Technologies
         : Arcxel to Vixel Corporation
    2014 : Emulex Design to Emulex Corporation
    2015 : Emulex to Avago Technologies
    2016 : Bank of America security agreement
    2017 : Security interest released
         : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. Every link in the body of the chain is an operating entity: Vixel (Fibre Channel hub/switch maker), Emulex Design & Manufacturing (operating), Emulex Corporation (operating, NASDAQ-listed), Avago Technologies (operating semiconductor company, now Broadcom). No "IP / Holdings / Ventures" shell is the transferee, and no single-purpose LLC appears. The one entity I cannot classify is Curitell Communications Inc. (2004-04-05 link) — UNCLEAR, because the assignor is the unexplained Hyundai Syscomm and I retrieved no corroboration. This single link is the only place a shell-entity argument could even be raised, and it is unproven.

2. Known asserter in the chain — NOT PRESENT. No link matches Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or any Spangenberg entity. The only litigation-plaintiff entity in the chain is Vixel Corporation, which was an operating competitor that made its own switching products — the opposite of an NPE.

3. Repeat correspondent across the chain — UNCLEAR (not retrievable). Correspondents of record are not exposed in the data I could retrieve, so I cannot test the "same lawyer runs every shell" tell. This is a genuine gap in my analysis, not a negative finding. Anyone needing this signal should pull each reel/frame's correspondent from the Assignment Center UI.

4. Cascading transfers — PRESENT but benign. Two assignments recorded on the same day, 2007-02-27, chaining Berman → Arcxel Technologies → Vixel Corporation within 24 hours. Mechanically this matches the "chained transfers in <24 months" pattern, but the substance is a chain-of-title repair (curing a patent that issued to the inventor personally rather than to Vixel), not an NPE cascade — there is no multi-LLC hop-scotch, and the chain terminates at the original operating family, not at an asserter.

5. Pre-litigation transfer — NOT PRESENT. The first infringement suit (Vixel v. Brocade, N.D. Cal., ~May 2003) predates the earliest recorded assignment here (2004-04-05). No assignment is dated within 6 months before the 2003 suit; the transfers are downstream of it.

6. Bankruptcy fire-sale — UNCLEAR. Vixel was acquired by Emulex, not liquidated in bankruptcy, so the main line of the chain is an acquisition. However, the unexplained Hyundai Syscomm → Curitell Communications (2004-04-05) link is the kind of disposition that often arises out of a Korean corporate restructuring/insolvency, and I could not confirm or refute that. Marked unclear.

7. Privateering — NOT PRESENT. No operating company transferred to an NPE to assert on its behalf. Emulex/Avago retained and internalized the portfolio; Avago even pledged it as collateral (2016-02-11, Bank of America security agreement), which is the behavior of an operating company monetizing and financing real products.

8. Defensive aggregator — NOT PRESENT. The chain terminates at Avago Technologies General IP (Singapore) Pte. Ltd. (operating semiconductor company, now Broadcom), not at RPX, AST, LOT, Unified, or OIN. The patent was not neutralized by a defensive aggregator; it simply expired (2017-02-18).

Verdict

Operating-company assertion.

Justification: The chain runs from inventor Berman through Vixel Corporation and its acquirer Emulex Design & Manufacturing Corporation (2004-05-19, recorded as a Change of Name), then Emulex Corporation (2014-01-17), then Avago Technologies General IP (Singapore) Pte. Ltd. (2015-10-23) — every transferee is a product-shipping Fibre Channel / semiconductor company, and the chain even carries an operating-company hallmark, a Bank of America collateral security agreement recorded 2016-02-11 and released 2017-02-03, which NPEs do not typically execute. The only assertion in the record is Vixel v. Brocade (N.D. Cal., ~2003), where the then-owner Vixel shipped competing loop/switch products and sued actual competitors Brocade and QLogic — the definition of an operating-company assertion, not troll behavior. The sole noise in the chain is the unretrieved-detail 2004-04-05 Hyundai Syscomm → Curitell Communications link, which I have flagged as unclear rather than characterizing.

Verify at: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search "6470007" or "09/611,173"); alternate index at https://assignment.uspto.gov/patent/index.html. Full event list also at https://patents.google.com/patent/US6470007/en under "Reassignment."

Reminder of what I could not retrieve (do not treat as findings): reel/frame numbers for any of the eight recorded events; correspondent-of-record names; separate execution dates; and any corroboration for the Hyundai Syscomm → Curitell link or the mysterious "Pantech Co Ltd" current-assignee listing.

I was able to retrieve a partial "US Patent References" list for US 6,470,007 from the FreePatentsOnline record, and I compared it against the Google Patents record. Before the analysis, three important caveats:

Caveats on data completeness

1. The citation list I retrieved is truncated. The FreePatentsOnline snippet ends with an ellipsis ("...") after US 5,610,745, meaning there are very likely additional cited U.S. patents, foreign patent documents, and/or non-patent literature (e.g., ANSI FC-PH/FC-AL standards) on the official front page that I could not retrieve before the search limit was reached. Treat this as a partial list.
2. Only independent claim 1 has been verified verbatim. The patent has 137 claims; I have not verified the wording of the other independent claims. Claim-mapping below is therefore anchored to verified claim 1 and to subject matter in the specification (logical-loop segmentation; ALPA range restriction; host-port reset on storage addition; PLOGI probe handling with LS_RJT), with the boundaries of those later claims inferred rather than quoted.
3. Effective priority date. US 6,470,007 (filed July 6, 2000) claims priority through 08/907,385 (→ US 6,118,776) to 08/801,471 (→ US 6,185,203), i.e., February 18, 1997. Whether any given reference is §102 prior art depends on its own filing date, its publication date, and whether it is "by another" — data I do not have for every reference below. I flag each where this materially matters.

Cited U.S. patents retrieved for US 6,470,007 (partial list)

A. Same-inventor / in-family references (NOT §102 prior art)

US 6,118,776 — "Methods and apparatus for fiber channel interconnection of private loop devices," Stuart B. Berman, issued September 12, 2000.

• Description: The direct parent of US 6,470,007 (application 08/907,385). Discloses interconnecting private loop devices across multiple Arbitrated Loops through a fabric, ALPA filtering, and host/PLOGI handling — i.e., essentially the same disclosure family as the patent at issue.
• §102 analysis: Not prior art. Same inventive entity, and US 6,470,007 validly claims priority through it. It cannot anticipate under §102 (not "by another"; same disclosure chain). It is relevant only to potential obviousness-type double patenting, which was already addressed via a terminal disclaimer (noted in the issue record).

US 6,185,203 — "Fibre channel switching fabric," Stuart B. Berman, issued February 6, 2001.

• Description: The grandparent (application 08/801,471, filed February 18, 1997). Discloses the fabric architecture later described in US 6,470,007: fabric control module, router with address/mask match, port control modules, switch core.
• §102 analysis: Not prior art for the same reasons (same inventor, in the priority chain). Do not rely on it for anticipation.

B. Third-party references most relevant to claim 1 and the Stealth-Mode subject matter

US 6,160,813 — "Fibre channel switching system and method," Banks et al., issued December 12, 2000.

• Description: A Fibre Channel switch system for routing frames among attached ports, including loop-capable ports and switching fabric elements — close to the general architecture of claim 1 (ports, route determination, connectivity apparatus).
• §102 analysis: Potentially the strongest third-party reference against the hardware architecture of claim 1. Whether it anticipates depends on its filing date (unconfirmed). It does not appear to teach the two different link speeds or the private-loop "Stealth" ALPA-filtering behavior, so full anticipation of claim 1 is doubtful; it is more useful in an obviousness combination.

US 5,894,481 — "Fiber channel switch employing distributed queuing," Book, issued April 13, 1999.

• Description: Fibre Channel switch with distributed queuing and routing of frames between ports.
• §102 analysis: Relevant to the route-determination/connectivity elements of claim 1 and to method claims on frame routing/filtering. No teaching of private-loop segmentation or differing link speeds identified; partial-element anticipation only.

US 5,751,715 — "Accelerator fiber channel hub and protocol," Chan et al., issued May 12, 1998.

• Description: A Fibre Channel hub that redrives/accelerates loop traffic between attached loop devices, using bypass functionality — directly in the field of FC Arbitrated Loop hubs (the "background" art the patent distinguishes in FIG. 22 discussion).
• §102 analysis: Relevant to dependent claims on port bypass circuits and hub/loop structures, and to the intelligent-bridging-hub apparatus. Because it is a passive/accelerating hub rather than a routing interconnect that segments loops and bridges between them, it likely does not meet all of claim 1.

US 5,638,518 — "Node loop core for implementing transmission protocol in fibre channel," Malladi, issued June 10, 1997.

• Description: Implements the Fibre Channel Arbitrated Loop transmission protocol — relevant to the "active L_Port implementing the Arbitrated Loop protocol (ARBs, OPNs, Closes)" element of claim 1.
• §102 analysis: Potentially anticipates the loop-protocol port-state-machine element of claim 1, but does not address multi-port routing between separate physical loops or differing link speeds. Partial-element reference.

US 5,828,475 — "Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch using a bypass bus and buffer," Bennett et al., issued October 27, 1998.

• Description: Fiber optic switching with bypass switching/buffering for intermixed data transfer.
• §102 analysis: Relevant to the buffering/cut-through and bypass features discussed in the specification; secondary against claim 1's core combination.

US 5,841,990 — "Network connector operable in bridge mode and bypass mode," Picazo, Jr. et al., issued November 24, 1998.

• Description: Network connector that can operate as a bridge or a bypass — conceptually similar to a port that forwards frames locally (bypass) or routes them off-loop (bridge), the core of the patent's receive-frame filtering algorithm.
• §102 analysis: Relevant to the "forward on the first Arbitrated Loop vs. route off-loop" method of selectively filtering frames, and possibly to dependent claims on port bypass circuits. Ethernet-oriented, so likely deficient on Fibre Channel ALPA specifics.

C. Other cited references (secondary relevance)

US 6,014,383 — "System and method for controlling multiple initiators in a fibre channel environment," McCarty, issued January 11, 2000.

• Description: Controlling multiple SCSI initiators on a Fibre Channel loop.
• §102 analysis: Relevant to the PLOGI/probing and SCSI-initiator method claims (LS_RJT/probe spoofing subject matter), and possibly to dependent claims; not relevant to claim 1's apparatus combination.

US 6,014,715 — "Method and apparatus for assigning port addresses," Stoevhase, issued January 11, 2000.

• Description: Assigning addresses to ports.
• §102 analysis: Relevant to the ALPA range-restriction method claims (dividing addresses into non-overlapping sets assigned per loop/port); limited bearing on claim 1.

US 6,041,381 — "Fibre channel to SCSI addressing method and system," Hoese, issued March 21, 2000.

• Description: Address mapping between Fibre Channel and SCSI domains.
• §102 analysis: Relevant to address-lookup/PLOGI-routing method claims; not to claim 1's switch structure.

US 5,941,972 — "Storage router and method for providing virtual local storage," Hoese et al., issued August 24, 1999.

• Description: A router providing virtual local storage to hosts.
• §102 analysis: Storage-network routing context; possible relevance to the host/storage reset and probe-routing methods. Secondary.

US 6,192,048 — "Method and apparatus for implementing hunt group support for a crosspoint controller," Nelson et al., issued February 20, 2001.

• Description: Crosspoint-controller connection management.
• §102 analysis: Marginal; at most background for connection setup between ports (route determination/connectivity element of claim 1). Note its issue date (February 2001) is after the July 6, 2000 filing date, so it could only be §102(e)/(g) prior art if its own filing date precedes the effective priority date — unconfirmed.

US 6,031,842 — "Low latency shared memory switch architecture," Trevitt et al., issued February 29, 2000.

• Description: Shared-memory switch fabric architecture.
• §102 analysis: Relevant only to the connectivity-apparatus (switch core) element generically; no loop/private-device teachings.

US 5,956,723 — "Maintaining identifier information in a memory using unique identifiers as a linked list," Zhu, issued September 21, 1999.

• Description: Identifier management in memory.
• §102 analysis: Marginal; at most relevant to address-table/lookup implementation details of the routing filter. Not an anticipation candidate for claim 1.

US 5,872,822 — "Method and apparatus for memory sequencing," Bennett, issued February 16, 1999.

• Description: Memory sequencing technique.
• §102 analysis: Peripheral; no Fibre Channel loop bridging content.

US 5,768,530 — "High speed integrated circuit interface for fibre channel communications," Sandorfi, issued June 16, 1998.

• Description: Integrated circuit interface for Fibre Channel (e.g., an FC controller/interface with a port state machine).
• §102 analysis: Relevant to the port-control-module/state-machine element of claim 1, but not to inter-loop routing of private loop devices or mixed link speeds.

US 5,619,497 — "Method and apparatus for reordering frames," Gallagher et al., issued April 8, 1997.

• Description: Frame reordering in a switch.
• §102 analysis: Secondary; frame-order handling only.

US 5,610,745 — "Method and apparatus for tracking buffer availability," Bennett, issued March 11, 1997.

• Description: Buffer-availability (credit) tracking — relevant to the patent's discussion of six-word device buffering and cut-through buffering.
• §102 analysis: Secondary; at most support for an obviousness argument on buffering limitations.

Overall §102 assessment

• No single retrieved reference appears to fully anticipate verified claim 1. Claim 1's distinctive combination — (i) two ports running Fibre Channel Arbitrated Loop port state machines that establish point-to-point sessions with private loop devices, (ii) different link speeds on the two ports, (iii) route determination apparatus, and (iv) a switching/connectivity fabric — is not taught as a whole by any one of the cited references I could examine. The closest single references on the hardware architecture are US 6,160,813, US 5,894,481, and (for the loop-port state machine element) US 5,638,518.
• The strongest §102 candidates by subject matter map to the later method/apparatus claims, whose exact text I have not verified:
  • ALPA range restriction during loop initialization (LIFA manipulation): US 6,014,715, US 6,041,381.
  • Frame filtering / forward-vs-route decision: US 5,841,990, US 6,160,813.
  • SCSI initiator PLOGI probing / multi-initiator control: US 6,014,383, US 6,041,381.
  • Intelligent bridging hub / port bypass circuits: US 5,751,715, US 5,841,990.
• Filing dates and "by another" status for most third-party references were not confirmed from my search results, so I cannot definitively state whether each reference is §102(a)/(e) prior art against the February 18, 1997 effective priority date (several issued in 1997–2001 and may have filing dates on either side of that date). This timing question, plus the missing tail of the citation list (foreign patents and NPL, likely including ANSI FC-PH/FC-AL documents), should be resolved against the USPTO full-text record (PATFT or Patent Center) before any reliance.

I'll firm up a few unverified facts from the Prior Art section (filing dates of the key third-party references, and the text of the later independent claims) before building the §103 combinations.

Confirmed Banks (US 6,160,813) was filed 1997-03-21 by Brocade — a critical date fact. Let me check two more things: whether the later independent claims of 6,470,007 can be retrieved, and what Banks actually discloses about loop ports.

One more check on a highly relevant reference not on the retrieved front page (Gadzoox's loop bridge patent), which sits in the critical priority window.

Obviousness Analysis — US 6,470,007 B1 under 35 U.S.C. § 103

Scope and verification status. This analysis uses the prior art identified in the earlier Prior Art section (as instructed), and adds two facts verified by search in this pass. Claim 1 is verified verbatim (FreePatentsOnline claims record for 6,470,007); claims 2–31 are now also verified verbatim. Claims 32–137 remain unverified — the retrieved claim text truncates at claim 31 (it literally breaks off at "31 . . . 3..."). Any mapping to independent method claims below is therefore grounded in the specification's Summary of the Invention, not in quoted claim language, and is labeled as such.

Two corrections/additions to the previously generated sections (flagging contradictions explicitly):

1. US 6,160,813 (Banks et al.) filing date is now confirmed: March 21, 1997, application 08/823,025, assigned to Brocade Communications Systems. (Source: https://uspto.report/patent/grant/[6160813](/patent/6160813).) The Prior Art section listed this date as "unconfirmed." This is legally decisive and is analyzed in §1 below. Note the irony worth flagging: the closest prior art to the asserted patent is Brocade's own patent, and Brocade was the defendant in the 2003 Vixel suit described in the Litigation section.
2. A materially important reference is missing from the retrieved citation list: US 5,978,379, "Fiber channel learning bridge, learning half bridge, and protocol," Chan & Black, Gadzoox Networks, application 08/786,891 filed January 22, 1997, granted November 2, 1999 (EP counterpart EP 0 858 190 A2, published Aug. 12, 1998). (Sources: https://portal.unifiedpatents.com/patents/patent/US-[5978379](/patent/5978379)-A; http://data.epo.org/publication-server/rest/v1.2/patents/EP0858190NWA2/document.html.) Because its U.S. filing date (Jan. 22, 1997) precedes even the Feb. 18, 1997 priority date, it is §102(e) prior art against every claim of 6,470,007 regardless of how the priority dispute resolves. This reference is far more damaging than anything on the cited front page, and its absence from the earlier section is a gap, not a contradiction.

1. The two §103 threshold issues: governing law and effective filing date

Governing law. The application that issued as 6,470,007 was filed July 6, 2000 — before March 16, 2013 — so pre‑AIA §103(a) and pre‑AIA §§102(a)/(b)/(e)/(g) apply. Graham v. John Deere, KSR Int'l v. Teleflex (the "expansive and flexible" approach, TSM as one permissible rationale), and In re Kahn frame the analysis.

Effective filing date — this is the whole ballgame. The chain is 09/611,173 (Jul. 6, 2000) → continuation of 08/907,385 (Aug. 7, 1997, now US 6,118,776) → CIP of 08/801,471 (Feb. 18, 1997, now US 6,185,203). Three distinct dates are in play, and each claim gets only the benefit that its own subject matter supports under §112 ¶1:

Consequence. If any claim limitation is not supported by Feb. 18, 1997, the effective date moves to Aug. 7, 1997 — and Banks/6,160,813 (filed Mar. 21, 1997) becomes §102(e) prior art ("by another," different inventive entity). If it is not supported even by Aug. 7, 1997, it moves to July 6, 2000, and the whole field of 1997–2000 FC switching art (including EP 0 858 190 A2, Book/5,894,481, McCarty/6,014,383, Stoevhase/6,014,715, Hoese/6,041,381) becomes available under §102(b)/(e).

The single limitation most exposed to this attack is claim 1's "first link speed . . . second link speed where the first link speed and second link speed are different." The specification's only arguably supportive text is the FIG. 13 passage: "All links to the fabric can operate at either 266 Mbps, 533 Mbps or 1.063 Gbps speeds and operate over either copper or fiber media." Whether that passage appears in the Feb. 18, 1997 or Aug. 7, 1997 disclosure is a §112 written-description question that must be resolved before any §103 opinion can be finalized, because it determines whether the strongest references are §102(e) art or mere §103 "background."

Also note the same-entity references (US 6,118,776; US 6,185,203) are not §102 prior art — same inventive entity, not "by another." They can only support obviousness-type double patenting (already addressed by the terminal disclaimer noted in the issue record). One caveat: if either patent names a co-inventor not named on 6,470,007, the "by another" requirement is met even as to a single differing inventor, and both become §102(e) art. Verify the inventive entity of 6,118,776 and 6,185,203.

2. Level of ordinary skill

A POSITA here is a B.S. in EE/CS with ~3–5 years in high-speed serial I/O, or equivalent, and would know the ANSI X3T11 family cold: FC‑PH (and FC‑PH‑2/‑3), FC‑AL (X3.272), FC‑AL‑2, FC‑PLDA, the loop tenancy protocol (ARB → OPN → RRDY → data → CLS), LIP/LISM/LIFA/LIRP/LILP, AL_PA addressing, and standard switch internals (D_ID routing tables, crossbar/shared-memory fabrics). Every reference below is addressed to exactly that person; all are in the same field of endeavor (Fibre Channel switching/interconnection), which satisfies KSR's field-of-endeavor and "reasonably pertinent" tests.

3. Claim 1 — element-by-element mapping

Take-away: claim 1 is a two-structure-plus-one-parameter claim. The structures (loop-capable port state machines, router, switching fabric) are individually and collectively old. The only limitation not squarely met by the retrieved art is the mixed link speed element.

4. The one novelty gap: different link speeds — and why it does not save claim 1

No retrieved reference (Banks; Book; Malladi; Chan 5,751,715; Picazo 5,841,990; Bennett 5,828,475) discloses two switch ports running at different rates. Anticipation of claim 1 on this record therefore fails; the attack must be §103. The §103 case is strong:

• Admission by the specification. The patent repeatedly treats link rate as a configurable parameter, not an invention: "All links to the fabric can operate at either 266 Mbps, 533 Mbps or 1.063 Gbps speeds and operate over either copper or fiber media" (FIG. 13 discussion), and defines a "Gigabit Link Module" as a module that "interfaces to the Endec through either a 10-bit or 20-bit interface and interfaces to the Fibre Channel link through either a copper or fiber interface" — i.e., the media/speed interface is already decoupled from the port logic. Where the patentee's own specification presents the limitation as a selectable design option, In re Aller / KSR teach that selection of a known option is obvious, and the patent discloses no unexpected result, no criticality, and no technical difficulty in running ports at different rates.
• Known, finite options. FC‑PH/FC‑AL defined 133/266/533/1062 Mbps operation; the property the claim recites is simply backward compatibility with the installed 266/533 Mbps base while adopting 1.063 Gbps for new links. That is a classic KSR "design incentive . . . market forces" rationale, and "a finite number of identified, predictable solutions."
• Predictability/structural argument. Because the Endec/serdes and the speed-specific link interface are decoupled from the routing and switch-core logic (Banks' G_Port ASIC, 6,160,813 Fig. 4; the patent's own GLM definition; Book's distributed queuing switch), running two ports at different rates requires no change to the inventive combination — merely two instances of a known port at two known rates. KSR: "the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results."
• Evidentiary gap to close. I have not verified a specific pre‑1997 reference expressly disclosing a Fibre Channel switch with per-port speed agility (e.g., the FC‑AL‑2 / FC‑PH‑2 speed-negotiation provisions, or a multi-speed port ASIC datasheet). This should be located, because it converts the mixed-speed element from a §103 argument into a §102 one. Given the §1 priority problem, art dated between Feb. 1997 and July 2000 would also suffice.

5. Combination A (primary, against claim 1)

Banks 6,160,813 + Gadzoox 5,978,379 + Malladi 5,638,518 (+ optionally Chan 5,751,715).

• Banks alone supplies: a Fibre Channel switch ("switch circuit 101," central memory, message crossbar) with per-port ASICs, D_ID-based routing (D_ID dissecting circuit 503 and routing tables 501/502), an embedded port 104 that receives frames that are unroutable and generates a reject response, and frame buffers/timeout logic. This maps to "port control modules," "route determination apparatus," and "connectivity apparatus."
• Gadzoox alone supplies: an FC‑AL device with ports implementing the loop protocol itself via state machines — ARB, OPN, RRDY, CLS, AL_PA-based arbitration, OPN preemption by highest-priority address — attached to a local loop segment, that "selectively couples first and second local loop segments to form a single Fibre Channel Arbitrated Loop in certain circumstances and two isolated independently functioning Fibre Channel Arbitrated Loops in other circumstances."
• Malladi supplies the node-loop-core/loop-port state machine implementation detail (the "active L_Port" element).

Motivation to combine (specific, articulated):

1. Same field, same problem, stated in the art itself. Gadzoox states the problem in the patent's own words twenty months earlier: physical loops make all traffic traverse every node; "the two primary sources of latency on an arbitrated loop come from link propagation latency . . . [and] node latency, which is a maximum of 6 Fibre Channel . . . words"; and "a need has arisen for a bridge product which can reduce loop latency as well as reduce contentions for the loop." The 6,470,007 specification concedes the identical problems ("six word buffer," "additive delay," "blocking topology," "jitter"). Motivation is thus supplied by the references themselves, not by hindsight.
2. Banks' fabric is the natural substitute for Gadzoox's bridge switching means. Both partition/reconcile traffic between loop domains; a POSITA seeking higher aggregate bandwidth would replace Gadzoox's forwarding-table half-bridge (which only partitions into two segments and preempts conflicting tenancies) with Banks' non-blocking shared-memory fabric, which resolves the very "conflicting OPN" preemption problem Gadzoox must handle with CLS preemption rules.
3. Predictable result: the combination yields the claimed benefit (concurrent conversations across segments) with no change in the operation of the attached private loop devices.

Dependent claims particularly exposed: claim 22 (port control module includes a "direct fabric attached state machine" — Banks' G_Port acts as F_Port/E_Port, Fig. 4); claim 23 (frame buffers — Banks' frame buffers 1002); claim 24 (RRDY primitive flow-control state machine — Banks' Buffer‑to‑Buffer Credit logic 413; Gadzoox's RRDY handling); claim 26 (D_ID extractor — Banks' "D‑ID dissecting circuit 503," a near-verbatim structural read); claims 2–6, 27–31 (storage/host/JBOD/RAID/tape/bridge types — routine, and Hoese 6,041,381 and 5,941,972 supply FC↔SCSI/storage routing); claim 15 (loop comprises a hub — Chan 5,751,715); claims 17–19 (LIP on predefined events — LIP is the standard FC‑AL reset primitive, and Chan 5,751,715/Gadzoox both teach loop reset/bypass behavior).

6. Combination B (alternative primary, less dependent on Banks' status)

Book 5,894,481 + Malladi 5,638,518 + Picazo 5,841,990 + Chan 5,751,715.
Book supplies a Fibre Channel switch with distributed queuing and per-port routing (route determination + connectivity). Malladi supplies the loop port state machine. Picazo supplies the bridge-vs-bypass decision logic that is structurally identical to the patent's ALPA filter algorithm ("forward frame on the local loop / receive frame off-loop depending on match"). Chan 5,751,715 supplies the FC hub with port bypass circuits (claims 15, 17–19, and the intelligent-bridging-hub aspect). Motivation: same as Combination A, plus Picazo's express teaching that a connector may operate in either "bridge mode" (route off-segment) or "bypass mode" (remain local) — which is precisely claim 1's route-or-stay decision and the selective-filtering method.

7. The "Stealth Mode" methods (inferred independent claims; text unverified)

If, as the Summary of the Invention indicates, there are independent claims to (a) segmenting one logical loop into physical loops, (b) restricting ALPAs to assigned ranges during loop initialization, (c) resetting host loops when storage is added, and (d) PLOGI probe spoofing with LS_RJT, the following combinations apply. I flag again that I could not verify these claims' wording.

(a) Logical-loop segmentation. Gadzoox 5,978,379, alone, is close to anticipatory. Its stated object is "the partitioning of a long or heavily populated FC‑AL into multiple shorter or lightly populated loop segments so that: 1) concurrent conversations can take place on the multiple loop segments . . . 2) long latencies . . . can be avoided." That is the patent's own object ("to segment one logical loop composed of private loop devices into several physical Arbitrated Loops") and its own benefit ("Host number 41 and JBOD 43 can simultaneously communicate . . . while Host number 42 and RAID 44 communicates"). Add Malladi and Banks for the fabric/hub implementation. §102 is a live argument here, not merely §103 — subject to whether the claims add anything (e.g., ALPA range forcing) not present in Gadzoox.

(b) ALPA range restriction via LIFA manipulation. Stoevhase 6,014,715 + Hoese 6,041,381 + Malladi 5,638,518 + Gadzoox. Stoevhase teaches assigning port addresses; Hoese teaches FC↔SCSI address mapping; Malladi/FC‑AL teach the LISM/LIFA loop-initialization mechanism the patent uses (lowest WWN wins loop master; LIFA bitmap claims ALPAs). Motivation: reduce routing-table size and guarantee address uniqueness across segments (the patent's stated reason: "to simplify system routing"), and avoid ALPA collisions when addressing a partitioned loop — a problem the references themselves create and therefore motivate solving. The technique claimed (setting reserved ALPAs to 1 in the LIFA bitmap and forcing selection from one range) is the straightforward application of a known primitive for a known purpose, i.e., KSR's "use of a known technique to improve a similar device in the same way" — especially given that the patent's own specification concedes the LIFA mechanism is pre-existing ANSI protocol.

(c) PLOGI I/O probe spoofing / LS_RJT. McCarty 6,014,383 + Hoese 6,041,381 + Banks 6,160,813 + Book 5,894,481. McCarty/“System and method for controlling multiple initiators in a fibre channel environment” and Hoese address multi-initiator probing and address mapping. Banks is the key reference: its switch already routes unroutable frames to an embedded port ("D‑ID not in routing tables" → frame "is forwarded to the embedded G‑Port 104 (the embedded fabric port) instead") precisely to generate a reject rather than discard. Motivation: eliminate the 10‑second PLOGI timeout the specification admits ("the initialization time is not acceptable unless the fabric acts on the PLOGI frame"). Banks' embedded-port handling plus the standard FC‑PH LS_RJT link service (expressly defined in the standard, per the patent's definitions section) make the specific response a mere substitution of one known reject for another.

(d) Resetting host ports on storage addition. Chan 5,751,715 / Gadzoox / Malladi (LIP generation) + Hoese 5,941,972 (storage router / host awareness). Generating LIP to force re-initialization is standard FC‑AL; the motivation (a private-loop SCSI initiator only probes once, so it must be reset to discover new targets) is dictated by the admitted behavior of unmodified initiator drivers — a KSR "known problem, known solution" scenario. Claims 17–19 (LIP on device addition / link errors) are directly supported by this art regardless of the later claims' exact wording.

(e) Intelligent bridging hub apparatus. Chan 5,751,715 + Picazo 5,841,990 + Bennett 5,828,475 + Gadzoox 5,978,379 + Malladi 5,638,518 (+ Nelson 6,192,048 for crosspoint control, Trevitt 6,031,842 for the switch core; processor: routine). Chan supplies hub submodules with port bypass circuits; Bennett supplies bypass switching and buffering; Picazo supplies the bridge/bypass mode logic; Gadzoox supplies the ALPA-filtering/routing port and state machines; Malladi supplies the loop core. Motivation: add routing intelligence to a conventional hub to break the blocking topology without changing attached devices — the express purpose of the "intelligent bridging hub" definition.

8. Overall §103 conclusion

• Anticipation of claim 1: none of the retrieved references discloses the mixed-link-speed limitation; on the retrieved record, claim 1 survives §102 (though Banks anticipates many dependent claims, notably claims 23, 24, 26, and 22, if it is §102(e) art).
• Obviousness of claim 1: strong. Claim 1 is a combination of (i) a known FC switch fabric with D_ID routing (Banks, Book), (ii) a known FC‑AL loop-port state machine (Malladi, Chan, Gadzoox), and (iii) a known design option — different link rates per port — which the patent's own specification presents as an available, unremarkable configuration. All three KSR rationales apply: predictable use of prior-art elements according to known methods; use of a known technique (loop-port state machine + D_ID router) to improve a similar device in the same way Gadzoox and Banks set out to do; and design incentive/market forces for backward compatibility with the installed 266/533 Mbps base.
• Obviousness of the Stealth Mode claims: strongest of all, and US 5,978,379 (Jan. 22, 1997) may be independently anticipatory as to the logical-loop-segmentation concept, given its identity of stated problem, mechanism (FC‑AL primitives, loop segments, concurrency), and benefit.
• The decisive procedural question is not the merits but §1: if the mixed-speed limitation (or any Stealth-Mode limitation) lacks written-description support in the Feb. 18, 1997 or Aug. 7, 1997 applications, the effective date shifts and the strongest references convert from §103 background into §102(e)/(b) prior art. That is where a validity challenge should be anchored.

9. Objective indicia (to be rebutted or accounted for)

Potential secondary considerations exist and should be evaluated with a nexus requirement: the Vixel→Brocade/QLogic 2003 campaign and the accused QuickLoop/Fabric Assist features; the assignment chain (Curitell → Emulex Design & Manufacturing → Emulex → Avago/Broadcom); and long-lived family continuations into the 2010s. Against these: (i) the market-adoption evidence is largely attributable to the Brocade and Gadzoox products, not the patentee's teaching (Gadzoox's bridge and Brocade's fabric both pre- or co-date the asserted disclosure); (ii) the patent's own Background concedes every problem it claims to solve, weakening any "unexpected results" or "teaching away" argument; and (iii) there is no evidence before me of a long-felt-but-unsolved need — the Gadzoox reference shows the need was recognized and addressed by others in the same window.

10. Unresolved items / do not rely without verification

1. Claims 32–137 verbatim text — not retrieved; independent method/hub claims are inferred, not quoted.
2. Priority support analysis (§112 ¶1) of the mixed-link-speed limitation and of the LIFA/ALPA-filtering, PLOGI-spoofing, and host-reset disclosures against 08/801,471 and 08/907,385.
3. Inventive entity of US 6,118,776 and US 6,185,203 (determines whether the "same-family" references are §102(e) art).
4. Filing dates/publication dates of the remaining cited references (US 5,894,481; 5,751,715; 5,638,518; 5,828,475; 5,841,990; 6,014,383; 6,014,715; 6,041,381; 5,941,972; 6,192,048; 6,031,842; 5,956,723; 5,872,822; 5,768,530; 5,619,497; 5,610,745) — several issued 1997–2001 and turn on dates I have not confirmed.
5. Whether US 5,978,379 and/or EP 0 858 190 A2 were before the examiner in 09/611,173 or its parents — it appears on neither the retrieved front-page list nor the truncated FPO citation list, which if true is a material §102/§103 oversight.
6. A pre-1997 reference expressly disclosing per-port speed agility in a Fibre Channel switch — needed to convert the last claim-1 element from §103 to §102.