US 10944400

US patent 10944400, titled "On-die termination control," was issued on March 9, 2021, from an application filed on April 20, 2020 (Application No. US16/853,658). The original assignee was Rambus Inc, and the current assignee, as of October 15, 2025, is Signal LLP. The inventors are Kyung Suk Oh and Ian P. Shaeffer.

Abstract:
The patent describes a memory control component that manages on-die termination (ODT) in a memory IC during write operations. Specifically, the memory control component outputs a memory write command and associated write data to a memory IC. Before the write data is received by the memory IC, the control component asserts a termination control signal. This signal causes the memory IC to apply a first on-die termination impedance to its data inputs while the write data is being received. After the write data reception is complete, a second on-die termination impedance is applied. The memory control component can then deassert the termination control signal, causing the memory IC to remove all termination impedance from the data inputs.

Plain-Language Overview of Independent Claims:

• Claim 1 (Integrated Circuit Device): This claim describes an integrated circuit device (e.g., a memory controller) that communicates with a Dynamic Random Access Memory (DRAM) component. The DRAM has two registers to store control values. The integrated circuit device includes control circuitry designed to send commands to the DRAM. These commands instruct the DRAM to:

  1. Store a first control value in its first register, which dictates a specific (first) termination impedance to be applied to the DRAM's data interface during the period when write data is actively being received.
  2. Store a second control value in its second register, which dictates a different (second) termination impedance to be applied to the data interface after the write data reception period has concluded.

• Claim 11 (Method of Operation): This claim outlines a method performed by an integrated circuit device. The method involves:

  1. Transmitting one or more commands to a DRAM via a signaling interface. These commands instruct the DRAM to store a first control value for a first termination during write-data reception and a second control value for a second termination after write-data reception.
  2. Transmitting a write command to the DRAM via the same signaling interface, indicating that write data is expected.

• Claim 20 (Integrated Circuit Device - Means-Plus-Function): This claim describes an integrated circuit device that features a signaling interface intended for connection to a DRAM. The device also includes "means for transmitting" commands to the DRAM through this interface. These commands instruct the DRAM to store a first control value that specifies a first termination to be applied during write-data reception, and a second control value that specifies a second termination to be applied after the write-data reception interval has passed.

CAFC 2026 Dockets:
A review of the "Scheduled Cases – May 2026" for the U.S. Court of Appeals for the Federal Circuit indicates that US Patent 10944400 is not listed for any scheduled hearings in May 2026. While the patent record notes that a US case has been filed in the Texas Western District Court regarding litigation, this refers to a district court action and not a 2026 docket before the CAFC.