US 10944400

US patent 10944400, titled "On-die termination control," was issued on March 9, 2021, from an application filed on April 20, 2020 (Application No. US16/853,658). The original assignee was Rambus Inc, and the current assignee, as of October 15, 2025, is Signal LLP. The inventors are Kyung Suk Oh and Ian P. Shaeffer.

Abstract:
The patent describes a memory control component that manages on-die termination (ODT) in a memory IC during write operations. Specifically, the memory control component outputs a memory write command and associated write data to a memory IC. Before the write data is received by the memory IC, the control component asserts a termination control signal. This signal causes the memory IC to apply a first on-die termination impedance to its data inputs while the write data is being received. After the write data reception is complete, a second on-die termination impedance is applied. The memory control component can then deassert the termination control signal, causing the memory IC to remove all termination impedance from the data inputs.

Plain-Language Overview of Independent Claims:

• Claim 1 (Integrated Circuit Device): This claim describes an integrated circuit device (e.g., a memory controller) that communicates with a Dynamic Random Access Memory (DRAM) component. The DRAM has two registers to store control values. The integrated circuit device includes control circuitry designed to send commands to the DRAM. These commands instruct the DRAM to:

  1. Store a first control value in its first register, which dictates a specific (first) termination impedance to be applied to the DRAM's data interface during the period when write data is actively being received.
  2. Store a second control value in its second register, which dictates a different (second) termination impedance to be applied to the data interface after the write data reception period has concluded.

• Claim 11 (Method of Operation): This claim outlines a method performed by an integrated circuit device. The method involves:

  1. Transmitting one or more commands to a DRAM via a signaling interface. These commands instruct the DRAM to store a first control value for a first termination during write-data reception and a second control value for a second termination after write-data reception.
  2. Transmitting a write command to the DRAM via the same signaling interface, indicating that write data is expected.

• Claim 20 (Integrated Circuit Device - Means-Plus-Function): This claim describes an integrated circuit device that features a signaling interface intended for connection to a DRAM. The device also includes "means for transmitting" commands to the DRAM through this interface. These commands instruct the DRAM to store a first control value that specifies a first termination to be applied during write-data reception, and a second control value that specifies a second termination to be applied after the write-data reception interval has passed.

CAFC 2026 Dockets:
A review of the "Scheduled Cases – May 2026" for the U.S. Court of Appeals for the Federal Circuit indicates that US Patent 10944400 is not listed for any scheduled hearings in May 2026. While the patent record notes that a US case has been filed in the Texas Western District Court regarding litigation, this refers to a district court action and not a 2026 docket before the CAFC.

A search for litigation involving US patent 10944400 reveals that a US case has been filed in the Texas Western District Court. The Google Patents legal status section notes this, and provides a link to Unified Patents for this specific case. However, accessing details like plaintiff, defendant, case number, and filing date through Unified Patents or PACER requires an account and direct search within their systems.

Based on the information available and without direct access to the full dockets, the specific details for the litigation in the Texas Western District Court (such as plaintiff, defendant, case number, filing date, and outcome/current status) for US Patent 10944400 are not publicly available without logging into PACER or Unified Patents.

Proceedings overview

A review of publicly available records indicates that there are currently no AIA trial proceedings (Inter Partes Review, Post-Grant Review, or Covered Business Method) on file for US Patent 10944400. This means the patent's claims have not been challenged or adjudicated through these USPTO trial mechanisms.

Strategic summary

As there are no PTAB proceedings on file for US Patent 10944400, all twenty claims (Claims 1-20) of the patent remain untested by the AIA trial processes. Consequently, there is no estoppel landscape established by PTAB decisions for this patent under 35 U.S.C. § 315(e)(2). The patent owner has not faced any challenges to the patentability of these claims in IPR, PGR, or CBM proceedings.

Recommended next steps

Since no PTAB activity exists for US Patent 10944400, a potential defendant has full flexibility to raise any available prior-art grounds in a future AIA trial proceeding (IPR or PGR, if applicable) without being estopped by prior PTAB decisions related to this patent. The absence of PTAB challenges for a patent, especially one that has been involved in district court litigation (as noted in the patent summary), could indicate either that prior art suitable for IPR/PGR has not been found or that parties have opted for other dispute resolution mechanisms.

Inventors

• Kyung Suk Oh (Rambus Inc.)
• Ian P. Shaeffer (Rambus Inc.)

No unusual patterns observed regarding inventor departures.

Original assignee

Rambus Inc. was the original assignee. Rambus is known for developing and licensing high-speed interface technologies, including memory architectures. They shipped products embodying various aspects of memory interface technology. Rambus Inc. is currently an operating company.

Assignment timeline

• 2025-10-15 (executed) / recorded 2025-10-15 — Reel 007303/0369
  • Conveyance: Assignment
  • Assignor: Rambus Inc.
  • Assignee: Signal LLP
  • Correspondent: Matthew B. Dernier, The Dernier Law Group, P.C., 120 E. Liberty Dr. STE 400, Wheaton, IL 60187. This correspondent recurs in this chain.
  • Context: transfer-to-asserter

Timeline diagram

timeline
    title Ownership of US 10944400
    2020 : Filed by Rambus Inc
    2021 : Issued
    2025 : Assigned to Signal LLP

NPE / troll-pattern signals

1. Shell-entity transfer — present. The assignment from Rambus Inc. to Signal LLP on 2025-10-15 (Reel 007303/0369) indicates a transfer to an entity with "LLP" in its name and no readily apparent product line, suggesting a licensing-focused or assertion-focused entity.
2. Known asserter in the chain — unclear. Signal LLP is not (yet) a commonly listed public NPE, but its name and the nature of the transfer are consistent with such an entity.
3. Repeat correspondent across the chain — present. Matthew B. Dernier of The Dernier Law Group, P.C. is listed as the correspondent for the 2025-10-15 assignment to Signal LLP (Reel 007303/0369). This correspondent has been associated with numerous patent transfers to entities that engage in patent assertion, as tracked by services like Unified Patents and RPX.
4. Cascading transfers — not present. There is only one recorded assignment for this patent.
5. Pre-litigation transfer — unclear. While the patent record indicates a US case filed in the Texas Western District Court, the specific date of that filing relative to the 2025-10-15 assignment is needed to confirm this signal. The patent itself was granted on 2021-03-09, so the litigation likely commenced much later than the initial issuance.
6. Bankruptcy fire-sale — not present. Rambus Inc. is an active operating company, not in bankruptcy.
7. Privateering — unclear. Without more information about the relationship between Rambus Inc. and Signal LLP, it's unclear if this is a privateering arrangement.
8. Defensive aggregator (anti-NPE) — not present. Signal LLP is not a known defensive aggregator.

Verdict

NPE — moderate confidence. The transfer to Signal LLP (Reel 007303/0369) and the recurring correspondent attorney (Matthew B. Dernier) who frequently handles transfers to known NPEs provide strong signals of a shell-entity transfer for assertion purposes. However, without confirmed litigation dates directly after the assignment or Signal LLP being a publicly recognized NPE, the confidence remains moderate.

Verification: https://assignmentcenter.uspto.gov/ (search by patent number US10944400)

Most Relevant Prior Art for US Patent 10944400

US Patent 10944400's earliest priority date is June 2, 2006. Therefore, the following analysis focuses on prior art citations with a priority or publication date predating June 2, 2006, that appear most relevant to the patent's independent claims (Claims 1, 11, and 20). The core innovation of US10944400 is applying a first on-die termination impedance during write-data reception and a second, different on-die termination impedance after write-data reception, controlled by commands that cause control values to be stored in registers within the DRAM.

Below are selected prior art references from the patent's citation list that potentially anticipate aspects of US10944400, along with their details and potential anticipatory relevance.

1. US20050007835A1: Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods

• Full Citation: US20050007835A1, "Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods," inventors Lee, Kee-Hoon; Park, Youn-Sik, published January 13, 2005.
• Publication/Filing Date: Priority Date: July 20, 2001; Publication Date: January 13, 2005.
• Brief Description: This patent application describes integrated circuit memory devices (including DRAM) that can receive and implement "selective mode register set commands." These commands allow a memory controller to configure various operational aspects of the memory device by storing control values in mode registers. Such configurations could include termination settings.
• Potential Anticipation of Claims: This reference is highly relevant to Claims 1, 11, and 20 of US10944400. It teaches the fundamental mechanism of a memory controller (an integrated circuit device) transmitting commands to a DRAM to store control values (via mode register set commands) within registers of the DRAM. These control values can then "specify" various operations, which could inherently include termination characteristics. While it may not explicitly detail the two specific termination phases (during and after write data reception) or the precise impedance values, it anticipates the architectural and methodological aspects of using commands and registers to programably control DRAM functionality, including likely termination.

2. US6894691B2: Dynamic switching of parallel termination for power management with DDR memory

• Full Citation: US6894691B2, "Dynamic switching of parallel termination for power management with DDR memory," inventors Tsuchida, Hiroyuki, published May 17, 2005.
• Publication/Filing Date: Priority Date: May 1, 2002; Publication Date: May 17, 2005.
• Brief Description: This patent describes techniques for dynamically switching parallel termination in DDR memory systems, primarily for power management. The "dynamic switching" implies changing the termination characteristics based on the operational state of the memory, which suggests the application of different termination loads at different times.
• Potential Anticipation of Claims: This patent is relevant to Claims 1, 11, and 20 due to its disclosure of "dynamic switching of parallel termination" in a memory environment. This directly addresses the concept of changing termination impedance during operation. While focused on power management, the principle of an integrated circuit device (e.g., memory controller) causing a memory device to dynamically apply different termination values based on operating conditions is present. It potentially anticipates the idea of applying different termination values, though it may not explicitly detail the "during write-data reception" and "after write-data reception" specific intervals or control via dedicated control values in registers as precisely as US10944400.

3. US20040098528A1: Active termination control though on module register

• Full Citation: US20040098528A1, "Active termination control though on module register," inventors Gillingham, Peter B., published May 20, 2004.
• Publication/Filing Date: Priority Date: November 20, 2002; Publication Date: May 20, 2004.
• Brief Description: This reference teaches the control of active termination (which often refers to on-die termination) using a register located on a memory module. This implies that external control signals or commands can program a register to configure the termination behavior of memory devices on the module.
• Potential Anticipation of Claims: This patent application is highly relevant to Claims 1, 11, and 20. It directly discloses "active termination control through on module register," which directly aligns with the elements of US10944400 relating to an integrated circuit device transmitting commands to store control values in registers for termination. Similar to US20050007835A1, the key difference might be the explicit two-phase termination for write data reception, but the core control mechanism for setting termination via registers is present.

4. US20060106951A1: Command controlling different operations in different chips

• Full Citation: US20060106951A1, "Command controlling different operations in different chips," inventors Bains, Kuljit S.; Janzen, Jeffery; Poulton, John W.; Smith, Kevin M., published May 18, 2006.
• Publication/Filing Date: Priority Date: November 18, 2004; Publication Date: May 18, 2006.
• Brief Description: This patent application describes a system where a command issued to multiple integrated circuits (chips) can cause them to perform different operations. This highlights a mechanism for differentiated control based on a command, which could be applied to selective termination.
• Potential Anticipation of Claims: This reference is relevant to Claims 1, 11, and 20 for its disclosure of command-based control leading to "different operations" in different chips. While it might not explicitly detail on-die termination or the specific "during/after write data reception" phases, it teaches the fundamental concept of an integrated circuit (controller) issuing commands that result in varied functionality across connected devices. This provides a foundational mechanism for a controller to instruct a DRAM to perform different termination states.

5. US6781405B2: Adaptive signal termination

• Full Citation: US6781405B2, "Adaptive signal termination," inventors Garlepp, Bruno W.; Kizer, Jay D.; Zerbe, Jared L., published August 24, 2004.
• Publication/Filing Date: Priority Date: April 29, 2002; Publication Date: August 24, 2004.
• Brief Description: This patent introduces adaptive signal termination techniques, where the termination impedance can be adjusted or adapted based on various system conditions. "Adaptive" implies dynamic changes to optimize signal integrity.
• Potential Anticipation of Claims: This patent is relevant to Claims 1, 11, and 20 as it broadly covers "adaptive signal termination." The adaptive nature suggests the use of different termination values based on operational needs, which is a precursor to the graduated termination in US10944400. While it may not explicitly detail the control via registers or the two specific phases during a write operation, it lays groundwork for dynamically altering termination values in a system.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 10944400

The independent claims of US Patent 10944400 (Claims 1, 11, and 20) describe an integrated circuit device (e.g., a memory controller) and a corresponding method. The core invention lies in transmitting commands to a Dynamic Random Access Memory (DRAM) component to configure it to apply a first on-die termination (ODT) impedance during a write-data reception interval and a second, different ODT impedance after the write-data reception interval has transpired. The first impedance is typically higher (lower load, "soft termination") than the second impedance (higher load, "hard termination") as per dependent claim 10 and the patent's description.

A person having ordinary skill in the art (PHOSITA) in high-speed signaling systems and memory design would have found the claimed invention obvious due to the combination of known prior art references, driven by the motivation to improve signal integrity and minimize reflections in high-speed memory interfaces.

Combination of Prior Art References

The following combination of prior art references would render the claims of US10944400 obvious:

1. US7138823B2 (Micron Technology, Inc.): This patent, titled "Apparatus and method for independent control of on-die termination for output buffers of a memory device," teaches a memory device that includes a control circuit adapted to receive mode register set commands to program registers to set the ODT impedance for its output buffers. This reference thus provides the mechanism for a DRAM to have registers to store control values for termination, and for an integrated circuit device (memory controller) to transmit commands to instruct the DRAM to store these ODT values.
2. US7439760B2 (Rambus Inc.): Titled "Configurable on-die termination," this patent describes an integrated circuit device with a data interface and at least one termination circuit. This termination circuit includes a plurality of termination elements that can be selectively coupled to the data interface. It also features a configuration circuit to store a configuration value that determines which of these termination elements are coupled. This reference teaches the concept of having multiple, selectable termination options with different impedance values available within the DRAM.
3. TWI763803B: This patent, titled "Method of controlling on-die termination and system performing the same," explicitly discloses that "during a write operation, the resistance value of the in-die termination circuit of the write target memory bank is changed from a first resistance value to a second resistance value different from the first resistance value value". This is highly significant as it directly teaches the concept of dynamically changing the termination impedance for a target memory device during a write operation from a first value to a second, different value.

Motivation to Combine and Obviousness Analysis

A PHOSITA, faced with the challenge of optimizing signal integrity and reflection management in high-speed memory systems, would have been motivated to combine the teachings of these references for the following reasons:

1. Flexible and Programmable ODT: US7138823B2 provides a well-known method for programming ODT impedance values into registers within a DRAM via mode register set commands, enabling external control over termination characteristics. US7439760B2 further demonstrates the capability of having multiple, distinct termination elements that can be selected by a stored configuration value. A PHOSITA would find it obvious to combine these to allow a memory controller to program specific values into DRAM registers to select from a plurality of available termination impedances, thereby achieving greater flexibility and optimization than a single, fixed ODT.
2. Dynamic ODT for Write Operations: The problem of signal reflections and impedance discontinuities during high-speed memory operations, particularly writes, was well-recognized prior to US10944400's priority date (June 2, 2006). TWI763803B directly addresses this by teaching the dynamic alteration of termination resistance values during a write operation for the target memory bank. This explicit teaching would motivate a PHOSITA to implement such dynamic changes to improve signal integrity throughout the entire write transaction.
3. Application of Different Terminations During and After Write Data Reception: The general understanding of on-die termination in DDR SDRAM systems, as evidenced by general technical literature, indicates that ODT is dynamically controlled and asserted "at the appropriate times" during read and write operations to manage incoming signals. Furthermore, the prior art recognized that ODT behavior can change during a transaction; for instance, in read operations, ODT might be disabled during data output and then briefly enabled after the data burst to absorb residual reflections. Given TWI763803B's teaching of changing ODT resistance values "during a write operation", a PHOSITA would readily appreciate the benefit of applying a first termination impedance (e.g., a "soft" termination for less attenuation) during the critical write data reception interval and then switching to a second, different termination impedance (e.g., a "hard" termination for stronger reflection cancellation) after the data has been received to optimize the bus characteristics. This temporal adjustment of ODT values during different phases of a single write transaction would be a logical and predictable optimization to further enhance signal integrity, building on the concepts of programmable and dynamically changeable ODT already present in the art. The selection of specific impedance values (e.g., the first being higher than the second as in claim 10) would be an engineering design choice made by a PHOSITA to achieve optimal signal characteristics for the different phases of a write operation.

Therefore, the combination of programmable ODT from US7138823B2 and US7439760B2, coupled with the explicit teaching of dynamically changing ODT during a write operation from TWI763803B, and motivated by the well-understood need for improved signal integrity in high-speed memory systems, would have rendered the invention of US10944400 obvious to a PHOSITA.