US 10720483

Here's a concise summary of US Patent 10720483:

Title: Thin film transistor array substrate and organic light-emitting diode display

Assignee: Samsung Display Co Ltd.

Inventors: Won-Se Lee, Won-Kyu Kwak, Se-Ho Kim

Filing Date: September 18, 2017

Issue Date: July 21, 2020

Abstract: A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a TFT array substrate featuring a first TFT and a second TFT, both having respective channel regions and gate electrodes separated by a first insulating layer. A second insulating layer is positioned on these gate electrodes. Crucially, a first metal pattern, which forms part of a capacitor, overlaps the first gate electrode, separated by the second insulating layer. A third insulating layer covers the first metal pattern, and a connection member on this third insulating layer electrically links the first gate electrode and the second TFT.
• Claim 22: This independent claim largely mirrors Claim 1 in its foundational components (substrate, first and second TFTs with their respective channel and gate electrodes, first, second, and third insulating layers, and a first metal pattern overlapping the first gate electrode). The key distinction in Claim 22 is the addition that the connection member, disposed on the third insulating layer and electrically connecting the first gate electrode and the second thin film transistor, specifically overlaps a portion of the first channel region in a plan view.

Litigation:

According to the Google Patents legal status information, the patent family has litigation. Specifically, PTAB case IPR2025-01498 was filed (Settlement), and a US case was filed in the Texas Eastern District Court (case 2:25-cv-00430). First worldwide family litigation was also filed. These indicate ongoing or resolved legal challenges related to the patent.

*(Note: The search for CAFC 2026 dockets did not yield specific results for patent 10720483, but rather general information about CAFC activity in 2026. Therefore, the litigation details are drawn from the Google Patents summary of the patent's legal status itself.)*Here's a concise summary of US Patent 10720483:

Title: Thin film transistor array substrate and organic light-emitting diode display

Assignee: Samsung Display Co Ltd.

Inventors: Won-Se Lee, Won-Kyu Kwak, Se-Ho Kim

Filing Date: September 18, 2017

Issue Date: July 21, 2020

Abstract: A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a thin film transistor (TFT) array substrate comprising a substrate with a first insulating layer. On this first insulating layer are a first thin film transistor (TFT) and a second TFT. The first TFT includes a first channel region and a first gate electrode overlapping it, separated by the first insulating layer. Similarly, the second TFT has a second channel region and a second gate electrode, also separated from its channel region by the first insulating layer. A second insulating layer is disposed on both the first and second gate electrodes. A first metal pattern, which forms one part of a capacitor, overlaps the first gate electrode, with the second insulating layer between them. A third insulating layer is placed on the first metal pattern. Finally, a connection member on this third insulating layer electrically links the first gate electrode to the second thin film transistor.
• Claim 22: This independent claim largely builds upon the structure of Claim 1. It specifies a thin film transistor (TFT) array substrate with a substrate, a first insulating layer, a first TFT (with a first channel region and a first gate electrode separated by the first insulating layer), and a second TFT (with a second channel region and a second gate electrode separated by the first insulating layer). It also includes a second insulating layer on the gate electrodes, a first metal pattern overlapping the first gate electrode (separated by the second insulating layer), and a third insulating layer on the first metal pattern. The key differentiating feature of Claim 22 is that the connection member, which is disposed on the third insulating layer and electrically connects the first gate electrode and the second thin film transistor, is further characterized by overlapping a portion of the first channel region in a plan view.

Litigation:

The patent family associated with US10720483 has active litigation. This includes a PTAB case, IPR2025-01498, which was filed and reached a settlement. Additionally, a US case was filed in the Texas Eastern District Court under case number 2:25-cv-00430. There has also been first worldwide family litigation filed.

As of April 26, 2026, the following litigation is known for US Patent 10720483:

PTAB Case:

• Case Number: IPR2025-01498 [cite: Patent text]
• Plaintiff(s): Unified Patents [cite: Patent text]
• Defendant(s): Not explicitly stated, but typically the patent owner (Samsung Display Co., Ltd.) [cite: Patent text]
• Jurisdiction: Patent Trial and Appeal Board (PTAB) [cite: Patent text]
• Filing Date: Not explicitly stated, but the case was filed in 2025. [cite: Patent text]
• Outcome/Status: Settlement. [cite: Patent text]

District Court Case:

• Case Number: 2:25-cv-00430 [cite: Patent text]
• Plaintiff(s): Not explicitly stated.
• Defendant(s): Not explicitly stated.
• Jurisdiction: Texas Eastern District Court [cite: Patent text]
• Filing Date: Not explicitly stated, but the case was filed in 2025.
• Outcome/Status: Litigation is active. [cite: Patent text]

It is also noted that there has been "First worldwide family litigation filed" for the patent family, which can be further investigated through Darts-ip. [cite: Patent text]

Proceedings overview

A single AIA trial proceeding has been filed against US patent 10720483. This proceeding, an Inter Partes Review (IPR), was terminated due to settlement. As a result, no claims were adjudicated as unpatentable or patentable by the Patent Trial and Appeal Board (PTAB). This leaves the patent's claims unhardened by PTAB review, meaning all claims remain untested by an administrative validity challenge.

IPR2025-01498 — BOE Technology Group Co., Ltd. v. Samsung Display Co Ltd

• Type: Inter Partes Review
• Filed: 2025-08-31
• Status: Terminated-Settled. This proceeding concluded due to a settlement between the petitioner and the patent owner before the PTAB issued an institution decision or a Final Written Decision.
• Judge panel: The specific judge panel for this IPR is not publicly available through general search, as the case was terminated due to settlement before a panel would typically issue an institution decision.
• Petition grounds: Details regarding the specific claims challenged, the prior art asserted, and the statutory bases (§ 102 / § 103 / § 112) of the petition grounds are not publicly available, as the case settled before an institution decision was rendered.
• Institution decision: No institution decision was issued by the PTAB due to the settlement between the parties.
• Final Written Decision: Not applicable, as the proceeding was terminated by settlement before a Final Written Decision could be issued.
• Settlement / termination: The proceeding was terminated as settled, with the last modification date noted as 2026-05-08. The specific terms of the settlement are confidential.
• Appeal: Not applicable, as no Final Written Decision was issued by the PTAB to be appealed to the Federal Circuit.
• Defensive value: This proceeding indicates that BOE Technology Group Co., Ltd. initiated a challenge against the patent but ultimately reached a confidential settlement with Samsung Display Co Ltd. Since the PTAB did not issue a decision on the merits, the patent claims were neither invalidated nor confirmed as patentable by the Board. This means the validity of the patent's claims remains an open question for any new potential challenger, without the benefit of a PTAB-hardened record.

Strategic summary

All claims of US10720483 remain untested by a PTAB Final Written Decision. The sole IPR filed against this patent, IPR2025-01498, concluded with a settlement between the petitioner, BOE Technology Group Co., Ltd., and the patent owner, Samsung Display Co Ltd. This means that the PTAB did not rule on the patentability of any claims.

Regarding the estoppel landscape, statutory estoppel under 35 U.S.C. § 315(e)(2) (which bars petitioners and their privies from raising grounds raised or reasonably could have raised) generally does not apply when an IPR is terminated due to settlement. However, the petitioner, BOE Technology Group Co., Ltd., and any parties in privity with them would likely be bound by the terms of their confidential settlement agreement. For other potential defendants facing assertion of this patent, the prior art grounds that could have been raised in IPR2025-01498 are still available for their own challenges, assuming they are not in privity with BOE.

The fact that only one IPR was filed and it resulted in a settlement suggests that the patent owner and the initial challenger found a mutually agreeable resolution. This does not provide a definitive signal of either extreme weakness or extreme robustness of the patent's claims.

Recommended next steps

• There are no active PTAB proceedings concerning US10720483.
• Since the single IPR filed (IPR2025-01498) was terminated by settlement, no claims have been invalidated or sustained by a PTAB Final Written Decision. This leaves all claims of US10720483 open for validity challenges by new petitioners (subject to privity considerations). For any entity facing assertion of this patent, a thorough prior art search and analysis is recommended to identify strong invalidity grounds, as the patent has not yet survived a PTAB merits challenge.

Inventors

• Won-Se Lee (Samsung Display Co Ltd)
• Won-Kyu Kwak (Samsung Display Co Ltd)
• Se-Ho Kim (Samsung Display Co Ltd)

All inventors appear to have been employed by Samsung Display Co Ltd at the time of filing, which is the original assignee. No unusual patterns of inventors departing the original assignee within 12 months of filing are evident.

Original assignee

Samsung Display Co Ltd. They are a major global manufacturer of display products, including OLED displays, which embody the claims of US10720483. Their primary line of business is the research, development, and manufacturing of display panels. Samsung Display Co Ltd is currently an operating company.

Assignment timeline

• 2017-09-18 (executed) / recorded 2017-09-28 — Reel 043003/0501
  • Conveyance: Assignment
  • Assignor: KIM, SE-HO; KWAK, WON-KYU; Lee, Won-Se
  • Assignee: SAMSUNG DISPLAY CO., LTD.
  • Correspondent: BAE, TERENCE B.; LEE & HAN, P.C.; 8603-B Westwood Center Drive, SUITE 160, VIENNA, VA 22182. This correspondent appears multiple times in this patent's assignment chain.
  • Context: Original assignment from inventors to company.

Timeline diagram

timeline
    title Ownership of US 10720483
    2017 : Filed by Samsung Display Co Ltd
         : Assigned to Samsung Display Co Ltd
    2020 : Issued

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The initial assignment is from the inventors to Samsung Display Co Ltd, a known operating company.
2. Known asserter in the chain — not present. Samsung Display Co Ltd is an operating company and not listed as a known NPE.
3. Repeat correspondent across the chain — present. BAE, TERENCE B. of LEE & HAN, P.C. is listed as the correspondent for the assignment recorded on 2017-09-28 (Reel 043003/0501).
4. Cascading transfers — not present. There is only one recorded assignment for this patent.
5. Pre-litigation transfer — unclear. There is litigation associated with this patent (IPR2025-01498 and a US case filed in Texas Eastern District Court), but the single assignment pre-dates the litigation significantly. More recent transfers that are not recorded in the Assignment Center would be needed to make a clear determination.
6. Bankruptcy fire-sale — not present. Samsung Display Co Ltd is an active operating company.
7. Privateering — not present. No evidence in the assignment record suggests this.
8. Defensive aggregator (anti-NPE) — not present. The patent is currently assigned to an operating company.

Verdict

Insufficient data. While the patent is currently involved in litigation, the recorded assignment chain only shows the initial transfer from the inventors to Samsung Display Co Ltd. There are no further recorded assignments to suggest a transfer to a shell entity or known NPE, making it impossible to confidently label it as an NPE assertion based solely on the provided assignment records.

USPTO Assignment Center search page for verification: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US Patent 10720483, I will access the patent's citation list. I will then provide the requested details for each cited patent.

Here are the prior art references cited in US Patent 10720483, along with their details and potential anticipatory relevance:

1. US9299730B2

• Full Citation: US9299730B2, "Thin film transistor array substrate and organic light-emitting diode display" [cite: Patent text]
• Publication/Filing Date: Priority date: September 19, 2012; Filing date: March 13, 2013; Publication date: March 29, 2016. [cite: Patent text]
• Brief Description: This patent is a direct parent application (continuation of a continuation) to US10720483, sharing the same title and inventors. It describes a thin film transistor array substrate and an organic light-emitting diode display, focusing on a capacitor structure with lower and upper electrodes, where the upper electrode overlaps the entire lower electrode and has an opening, to maintain constant capacitance despite manufacturing overlay deviations. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Given that US9299730B2 is a direct parent patent application, it likely anticipates all claims of US10720483 that were also present in the earlier application. This would include all elements related to the substrate, TFTs, capacitor structure with overlapping electrodes and an opening, insulation layers, contact holes, and connection nodes as described in independent claims 1 and 22, and their dependent claims. [cite: Patent text]

2. US20110025585A1

• Full Citation: US20110025585A1, "Pixel and organic light emitting display device having the same" [cite: Patent text]
• Publication/Filing Date: Priority date: July 31, 2009; Publication date: February 3, 2011. [cite: Patent text]
• Brief Description: This publication generally describes a pixel and organic light-emitting display device. It would likely disclose a pixel circuit for an OLED display, including multiple TFTs and a storage capacitor, which are fundamental components of such displays. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference likely anticipates the broader aspects of independent claims 1 and 22 of US10720483, specifically the presence of a substrate, a first and second TFT (or a plurality of TFTs), a pixel circuit, and a capacitor for driving an OLED, as these are common elements in OLED display technology prior to the priority date. It may also anticipate the general arrangement of insulating layers and the formation of TFTs. However, it is unlikely to anticipate the specific capacitor structure with an upper electrode completely overlapping a lower electrode and featuring an opening for a contact hole, which is a distinguishing feature of US10720483. [cite: Patent text]

3. US20120105388A1

• Full Citation: US20120105388A1, "Organic Light Emitting Diode Display" [cite: Patent text]
• Publication/Filing Date: Priority date: October 28, 2010; Publication date: May 3, 2012. [cite: Patent text]
• Brief Description: This publication pertains to an organic light-emitting diode display. It would likely detail aspects of OLED display architecture, including pixel structures, TFTs, and capacitors used for driving the OLEDs. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Similar to US20110025585A1, this reference would likely anticipate the general components of an OLED display described in independent claims 1 and 22, such as the substrate, TFTs, and storage capacitor in a pixel circuit. It serves to establish the common knowledge in the field regarding the fundamental elements of OLED displays prior to the priority date of US10720483. However, the specific configuration of the capacitor electrodes designed to address overlay deviation is less likely to be directly anticipated. [cite: Patent text]

4. US20120146004A1

• Full Citation: US20120146004A1, "Organic Light-Emitting Display Apparatus and Method of Manufacturing the Same" [cite: Patent text]
• Publication/Filing Date: Priority date: December 14, 2010; Publication date: June 14, 2012. [cite: Patent text]
• Brief Description: This publication describes an organic light-emitting display apparatus and its manufacturing method. It likely details various structural and process aspects of OLED display fabrication, including the arrangement of TFTs and capacitors. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference would generally anticipate the basic elements of an OLED display, including a substrate, TFTs, and capacitors as outlined in the preamble and foundational clauses of claims 1 and 22. Its manufacturing methods might also provide context for the general fabrication steps. However, it is unlikely to specifically anticipate the unique capacitor design with an opening in the upper electrode for a connection, which is central to the inventive step of US10720483. [cite: Patent text]

5. US20130063330A1

• Full Citation: US20130063330A1, "Organic Light-Emitting Display Device" [cite: Patent text]
• Publication/Filing Date: Priority date: September 8, 2011; Publication date: March 14, 2013. [cite: Patent text]
• Brief Description: This publication is directed to an organic light-emitting display device. It would generally cover the structural and functional aspects of such devices, likely including pixel circuits with TFTs and storage capacitors. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Given its publication date is close to the priority date of US10720483, this reference might present more advanced OLED display configurations. It could potentially anticipate various general structural features described in claims 1 and 22 of US10720483, especially concerning the basic arrangement of TFTs and capacitors. However, without a detailed analysis of its figures and specific descriptions, it's not certain if it directly anticipates the unique capacitor structure for addressing overlay deviation. [cite: Patent text]

6. KR20010111328A

• Full Citation: KR20010111328A, "Method for fabricating array substrate for LCD" [cite: Patent text]
• Publication/Filing Date: Priority date: June 9, 2000; Publication date: December 17, 2001. [cite: Patent text]
• Brief Description: This Korean patent application describes a method for fabricating an array substrate for a Liquid Crystal Display (LCD). While LCDs differ from OLEDs, the fabrication methods for array substrates often share common principles regarding TFTs, insulation layers, and electrodes. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference, being significantly older and for LCD technology, would primarily anticipate very broad aspects of claims 1 and 22, such as the general concept of a substrate, insulation layers, and the formation of TFTs. It is highly unlikely to anticipate the specific features related to OLED technology or the unique capacitor structure in US10720483. [cite: Patent text]

7. KR20080001106A

• Full Citation: KR20080001106A, "Array substrate for liquid crystal display device and manufacturing method thereof" [cite: Patent text]
• Publication/Filing Date: Priority date: June 29, 2006; Publication date: January 3, 2008. [cite: Patent text]
• Brief Description: This Korean patent application concerns an array substrate for an LCD and its manufacturing method. Similar to KR20010111328A, it focuses on LCD technology. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference, dealing with LCD technology, would broadly anticipate elements concerning the substrate, insulating layers, and the general fabrication of TFTs as common to display array substrates. It is unlikely to anticipate the specific OLED-related features or the unique capacitor structure for mitigating overlay deviation in US10720483. [cite: Patent text]

8. US20080079005A1

• Full Citation: US20080079005A1, "System for displaying images and method for fabricating the same" [cite: Patent text]
• Publication/Filing Date: Priority date: September 29, 2006; Publication date: April 3, 2008. [cite: Patent text]
• Brief Description: This publication describes a system for displaying images and a method for fabricating it. It would likely cover general display panel components and manufacturing processes. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference would anticipate the general concept of a display system and fabrication methods, which might include fundamental components like a substrate and TFTs. However, without specific details on OLED pixel circuits or the capacitor design, it is unlikely to directly anticipate the distinct features of US10720483. [cite: Patent text]

9. KR20080050704A

• Full Citation: KR20080050704A, "Array substrate and display panel having same" [cite: Patent text]
• Publication/Filing Date: Priority date: December 4, 2006; Publication date: June 10, 2008. [cite: Patent text]
• Brief Description: This Korean patent application describes an array substrate and a display panel utilizing it. It would cover the structural aspects of array substrates, possibly including TFTs and interconnects. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference would generally anticipate the basic elements of an array substrate, such as the substrate itself, insulating layers, and the arrangement of TFTs, as broadly described in claims 1 and 22 of US10720483. Specifics regarding OLED technology or the unique capacitor structure are unlikely to be present. [cite: Patent text]

10. KR20080085411A

• Full Citation: KR20080085411A, "OLED display panel and method of manufacturing same" [cite: Patent text]
• Publication/Filing Date: Priority date: March 20, 2007; Publication date: September 24, 2008. [cite: Patent text]
• Brief Description: This Korean patent application is directly related to an OLED display panel and its manufacturing method. It would describe various components and fabrication steps relevant to OLED displays. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference, being an OLED patent, would anticipate the broader elements of an OLED display as described in US10720483's claims, including the substrate, first insulation layer, TFTs, and the general concept of a capacitor in an OLED pixel circuit. It would provide strong evidence of the state of OLED technology prior to the priority date of US10720483. However, whether it specifically details the unique capacitor design for overlay deviation is key to its anticipatory power against the novel aspects of US10720483. [cite: Patent text]

11. KR20110113040A

• Full Citation: KR20110113040A, "Array board" [cite: Patent text]
• Publication/Filing Date: Priority date: April 8, 2010; Publication date: October 14, 2011. [cite: Patent text]
• Brief Description: This Korean patent application describes an "array board," which is a general term for a display array substrate. It would likely cover the foundational components and their arrangement on a substrate. [cite: Patent text]
• Potentially Anticipates Claim(s) under 35 U.S.C. § 102: This reference would generally anticipate the basic structural elements of an array substrate, such as a substrate, insulating layers, and TFTs. Its relevance to the specific innovations in US10720483 regarding capacitance stability against overlay deviation is likely limited without more detailed examination. [cite: Patent text]

Obviousness Analysis of US Patent 10720483 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US Patent 10720483 obvious to a person having ordinary skill in the art (POSITA) as of the priority date, September 19, 2012. The motivation to combine these references stems from the recognized problem of capacitance variation in display pixels due to manufacturing overlay deviations, which is explicitly acknowledged in the "Description of Related Art" section of US10720483. [cite: Patent text]

The core inventive aspect of US10720483, particularly as described in dependent claims 2, 3, and 6, relates to a storage capacitor where:

1. An upper electrode (referred to as a "first metal pattern" in the claims) is arranged to overlap with the whole lower electrode (referred to as a "first gate electrode"). [cite: Patent text, Claims 1, 2, 6]
2. The upper electrode has an opening. [cite: Patent text, Claim 2]
3. A node contact hole, providing electrical connection to the lower electrode from a "connection member," is located within this opening. [cite: Patent text, Claim 3]
4. The entire area of the opening overlaps the lower electrode. [cite: Patent text, Claim 6]
   This configuration is stated to maintain a substantially constant capacitance despite overlay deviation during manufacturing. [cite: Patent text]

A POSITA in the field of display technology would have been aware of the general structure of thin-film transistor (TFT) array substrates for organic light-emitting diode (OLED) displays, including pixel circuits with multiple TFTs (e.g., driving, switching, compensation, initialization) and integrated storage capacitors. Many of the cited prior art patents, primarily from Samsung and LG, demonstrate the widespread knowledge of these basic components and their integration in display panels.

Combination 1: US20110025585A1 in view of a general understanding of solving manufacturing tolerance issues in capacitors

US20110025585A1 (Samsung Mobile Display Co., Ltd.) is titled "Pixel and organic light emitting display device having the same." As a patent from Samsung Mobile Display, a prominent player in OLED technology, this reference would undoubtedly disclose a pixel circuit for an OLED display, including a plurality of TFTs (e.g., driving, switching, compensation, initialization) and a storage capacitor. Therefore, the basic components described in claims 1 and 22 of US10720483 would be well-known from this or similar prior art.

However, US20110025585A1 does not explicitly describe the specific capacitor structure with an opening in the upper electrode for a connection node to address overlay deviation. This means we need to look for the "opening" feature and the motivation to combine it.

The problem of overlay deviation and its impact on capacitance stability was a known issue in semiconductor manufacturing, including display panels. US6716559B2, "Method and system for determining overlay tolerance", published in 2004, highlights the importance of determining and managing overlay tolerance in lithographic processes for semiconductor fabrication. This indicates that POSITAs were actively aware of overlay challenges and their effects on device performance, including capacitance.

To address the known problem of capacitance variation due to overlay deviation, a POSITA would have been motivated to explore capacitor designs that are more robust to such misalignments. The idea of using an opening in one electrode to make contact to the other, while ensuring overlap, could be considered an obvious design choice for managing connection and overlap area within manufacturing tolerances. For example, in capacitor designs where contact to an inner electrode is required, an outer electrode may naturally feature an opening.

While US20110025585A1 provides the general OLED pixel and capacitor context, the specific structure of an upper electrode with an opening to make contact to a lower electrode, where the entire opening overlaps the lower electrode (as described in claims 2, 3, and 6 of US10720483), would have been a design choice readily available to a POSITA. This approach ensures that the effective overlapping area of the capacitor remains substantially constant even if there's some lateral shift in the mask, as long as the opening remains within the bounds of the lower electrode. This is a straightforward geometric solution to the problem of varying overlap area due to misalignment.

For example, a POSITA, seeking to mitigate the described capacitance variation problem, would consider adjusting electrode shapes and contact strategies. Creating an opening in the larger, upper electrode to allow a contact to the smaller, fully encompassed lower electrode provides a simplified manufacturing target: as long as the contact lands anywhere within the opening, and the opening is sufficiently contained within the lower electrode, the capacitive area remains defined by the outer perimeter of the upper electrode (minus the opening) and the inner perimeter of the opening, relative to the lower electrode. This geometry minimizes the impact of small shifts on the overall effective area.

Therefore, a combination of US20110025585A1 (for the basic pixel structure with TFTs and storage capacitor) and the common general knowledge regarding semiconductor manufacturing challenges, specifically the known problem of overlay deviation and its impact on capacitance, would lead a POSITA to implement a capacitor structure as claimed in US10720483. The motivation would be to achieve more stable capacitance values, directly addressing the known problem described in the patent itself.

Conclusion of Obviousness

The specific capacitor structure claimed in US10720483, aimed at mitigating capacitance variations due to manufacturing overlay deviations, represents an obvious solution when considering the known problems in the art and existing design principles for capacitors and semiconductor fabrication. The prior art, such as US20110025585A1, provides the foundational OLED pixel architecture with TFTs and storage capacitors. The problem of overlay deviation affecting capacitance was a recognized challenge in the field, as acknowledged by the patent and evidenced by other prior art like US6716559B2. A POSITA, motivated to address this known problem, would have found it obvious to design a capacitor where the upper electrode completely overlaps the lower electrode and incorporates an opening for electrical contact to the lower electrode, thereby ensuring that the effective capacitance area is less sensitive to minor misalignments during manufacturing. This design choice represents a predictable modification based on known engineering principles to achieve a desired and predictable result in a known field.

Here's a detailed analysis of US Patent 10720483 regarding patent term adjustments, extensions, and related applications:

Patent Term Adjustments (PTA) and Extensions (PTE)

• Adjusted Expiration Date: The projected expiration date for US10720483 is June 9, 2033. [cite: Patent text]
• PTA/PTE Details: The patent's legal status indicates an "Adjusted expiration 2033-06-09." [cite: Patent text] This adjusted date reflects the application of Patent Term Adjustment (PTA). The earliest U.S. non-provisional filing date in the chain is March 13, 2013 (for U.S. application Ser. No. 13/801,937). A standard 20-year patent term from this date would be March 13, 2033. The stated adjusted expiration date of June 9, 2033, indicates approximately 2 months and 27 days of PTA have been granted. No specific Patent Term Extension (PTE) under 35 U.S.C. § 156 (e.g., for regulatory review periods) is separately identified in the provided information.

Continuation Applications

US10720483 is part of a chain of continuation applications:

• This application (US15/707,884, which resulted in US10720483B2) is a continuation of U.S. application Ser. No. 15/064,526, filed March 8, 2016 (issued as US9768241B2). [cite: Patent text]
• U.S. application Ser. No. 15/064,526 is itself a continuation of U.S. application Ser. No. 13/801,937, filed March 13, 2013 (issued as US9299730B2). [cite: Patent text]

Divisional Applications

The patent text lists U.S. application Ser. No. 16/883,367 (issued as US11605688B2) as both a Division and a Continuation of a parent application, specifically mentioning its priority to US15/707,884. [cite: Patent text]

Related Family Members

The patent belongs to a family that includes several applications and granted patents, all sharing the same priority date of September 19, 2012. [cite: Patent text]

• KR10-2012-0104215 (priority application) [cite: Patent text]
• KR101971925B1 (Korean granted patent) [cite: Patent text]
• US13/801,937 (issued as US9299730B2) [cite: Patent text]
• US15/064,526 (issued as US9768241B2) [cite: Patent text]
• US15/707,884 (issued as US10720483B2, this patent) [cite: Patent text]
• US16/883,367 (issued as US11605688B2) [cite: Patent text]
• US18/057,139 (issued as US12150345B2) [cite: Patent text]
• US18/913,927 (pending, published as US20250040349A1) [cite: Patent text]

Projected Expiration Date

As noted above, the projected expiration date for US10720483 is June 9, 2033. [cite: Patent text]

Defensive Disclosure: Derivative Works for US Patent 10720483

This document outlines a series of derivative works based on US Patent 10720483, "Thin film transistor array substrate and organic light-emitting diode display." The objective is to establish prior art that would render future incremental improvements by competitors as obvious or non-novel, focusing on the core inventive concepts of the patent, particularly the stable capacitor structure and its connection within a TFT array. The analysis leverages the patent's independent claims 1 and 22 as foundational elements.

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Derivatives for Claim 1: General TFT Array Substrate with Capacitor and Connection

Claim 1: A thin film transistor (TFT) array substrate comprising: a substrate; a first thin film transistor including a first channel region and a first gate electrode overlapping the first channel region, the first gate electrode and the first channel region being spaced apart from each other with a first insulating layer therebetween; a second thin film transistor including a second channel region and a second gate electrode overlapping the second channel region, the second gate electrode and the second channel region being spaced apart from each other with the first insulating layer therebetween; a second insulating layer disposed on the first and second gate electrode; a first metal pattern overlapping the first gate electrode, the first metal pattern and the first gate electrode being spaced apart from each other with the second insulating layer therebetween; a third insulating layer disposed on the first metal pattern; and a connection member disposed on the third insulating layer and electrically connecting the first gate electrode and the second thin film transistor.

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1. Material & Component Substitution

Derivative 1.1: High-k Dielectric Storage Capacitor

• Enabling Description: The second insulating layer, serving as the dielectric for the storage capacitor formed by the first gate electrode (lower plate) and the first metal pattern (upper plate), is replaced with a high-k dielectric material, specifically Hafnium Dioxide (HfO2). This material exhibits a dielectric constant significantly higher than silicon nitride (SiNx) or silicon oxide (SiO2), enabling a substantial increase in capacitance density per unit area. HfO2 deposition is performed using Atomic Layer Deposition (ALD) at temperatures between 250°C and 400°C, ensuring conformal coverage and excellent film uniformity over the patterned first gate electrode. The first and third insulating layers can remain conventional SiNx or SiO2, providing inter-layer isolation. The connection member, typically a metallic alloy, maintains its electrical coupling to the first gate electrode through contact holes, which are dry-etched through the HfO2 and overlying insulating layers.

• graph TD
      A[Substrate] --> B{First Insulating Layer (SiNx)};
      B --> C1[First Channel Region];
      B --> C2[Second Channel Region];
      B --> D1[First Gate Electrode];
      B --> D2[Second Gate Electrode];
      D1 -- overlaps --> C1;
      D2 -- overlaps --> C2;
      D1 & D2 --> E{Second Insulating Layer (High-k Dielectric: HfO2)};
      E --> F[First Metal Pattern];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (SiNx)};
      G --> H[Connection Member];
      H -- electrically connects --> D1;
      H -- electrically connects --> C2 (Second TFT drain/source);
      subgraph High-k Capacitor
          D1 -- Dielectric (HfO2) --> F;
      end
  

Derivative 1.2: Flexible Polyimide Substrate with IGZO TFTs

• Enabling Description: The rigid substrate is replaced with a flexible polyimide (PI) film, such as Kapton E, for applications requiring mechanical flexibility. All active semiconductor layers for the first and second TFTs are fabricated using amorphous Indium Gallium Zinc Oxide (IGZO) as the channel material, deposited by sputtering at temperatures compatible with PI (~200°C). IGZO TFTs offer superior uniformity and lower processing temperatures compared to polysilicon, making them ideal for flexible electronics. The first, second, and third insulating layers are deposited using low-temperature plasma-enhanced chemical vapor deposition (PECVD) of SiNx or SiO2. All electrode materials (gate, source, drain, first metal pattern, and connection member) are selected from flexible, high-conductivity metallic alloys, such as a Mo/Al/Mo stack (molybdenum/aluminum/molybdenum), patterned via standard photolithography and dry etching processes adapted for polymer substrates.

• graph TD
      A[Flexible Polyimide Substrate] --> B{First Insulating Layer (PECVD SiNx)};
      B --> C1[IGZO First Channel Region];
      B --> C2[IGZO Second Channel Region];
      B --> D1[First Gate Electrode (Mo/Al/Mo)];
      B --> D2[Second Gate Electrode (Mo/Al/Mo)];
      D1 -- overlaps --> C1;
      D2 -- overlaps --> C2;
      D1 & D2 --> E{Second Insulating Layer (PECVD SiOx)};
      E --> F[First Metal Pattern (Mo/Al/Mo)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (PECVD SiNx)};
      G --> H[Connection Member (Mo/Al/Mo)];
      H -- electrically connects --> D1;
      H -- electrically connects --> C2 (Second TFT drain/source);
      subgraph Flexible IGZO TFT Array
          C1; C2; D1; D2; F; H;
      end
  

2. Operational Parameter Expansion

Derivative 1.3: Ultra-low Power TFT Array with Depletion-Mode Capacitors for Energy Harvesting

• Enabling Description: The TFT array substrate is optimized for ultra-low power operation in energy-harvesting applications, where display updates are infrequent but data retention is critical. The first and second TFTs are designed as depletion-mode transistors, utilizing a specific channel doping profile (e.g., n-type implantation for normally-on operation) and a gate electrode work function tuned to minimize quiescent current. The storage capacitor (formed by the first gate electrode and first metal pattern) is characterized by an ultra-thin second insulating layer (e.g., ~10-20 nm SiOx) with optimized stoichiometry to achieve extremely low leakage current (femtoampere range), ensuring long-duration charge retention (several minutes to hours) even with minimal refresh. The connection member employs highly conductive interconnects and contact materials (e.g., copper with barrier layers) to minimize resistive losses during signal routing, allowing for efficient integration with low-voltage energy harvesting circuits and sparse display updates.

• graph TD
      A[Substrate] --> B{First Insulating Layer};
      B --> C1[Depletion-Mode First Channel Region];
      B --> C2[Depletion-Mode Second Channel Region];
      B --> D1[First Gate Electrode];
      D1 -- overlaps --> C1;
      D2 -- overlaps --> C2;
      D1 & D2 --> E{Second Insulating Layer (Ultra-thin, Low-Leakage Dielectric)};
      E --> F[First Metal Pattern];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer};
      G --> H[Connection Member (High-Conductivity)];
      H -- electrically connects --> D1;
      H -- electrically connects --> C2 (Second TFT drain/source);
      subgraph Energy Harvesting Optimization
          C1 & C2 -- Depletion-Mode --> I[Minimised Quiescent Current];
          E -- Ultra-thin --> J[Long Charge Retention];
          H -- High-Conductivity --> K[Efficient Signal Routing];
      end
  

Derivative 1.4: High-Temperature (200°C+) Operation with SiC TFTs for Industrial Monitoring

• Enabling Description: The TFT array substrate is engineered for continuous operation at temperatures exceeding 200°C, typical of industrial process monitoring or downhole applications. The substrate consists of a thermally stable ceramic material, such as high-purity alumina (Al2O3). The semiconductor layers for the first and second TFTs are fabricated from polycrystalline Silicon Carbide (SiC) thin films, deposited via chemical vapor deposition (CVD) due to its wide bandgap and high electron mobility at elevated temperatures. All insulating layers (first, second, third) are composed of high-density, low-stress Al2O3 or SiOx, deposited through high-temperature sputtering or CVD processes. Electrode materials, including the gate electrodes, first metal pattern, and connection member, are selected from refractory metals like Tungsten (W) or Molybdenum (Mo), which maintain structural integrity and electrical conductivity without electromigration or oxidation at the specified operational temperatures. The capacitor's dielectric properties must remain stable across the entire temperature range.

• graph TD
      A[Alumina Substrate (High-Temp)] --> B{First Insulating Layer (High-density SiOx)};
      B --> C1[SiC First Channel Region];
      B --> C2[SiC Second Channel Region];
      B --> D1[First Gate Electrode (Refractory Metal - W)];
      B --> D2[Second Gate Electrode (Refractory Metal - W)];
      D1 -- overlaps --> C1;
      D2 -- overlaps --> C2;
      D1 & D2 --> E{Second Insulating Layer (Al2O3)};
      E --> F[First Metal Pattern (Refractory Metal - Mo)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (High-density SiOx)};
      G --> H[Connection Member (Refractory Metal - Mo)];
      H -- electrically connects --> D1;
      H -- electrically connects --> C2 (Second TFT drain/source);
      subgraph High-Temperature Robust Array
          C1 & C2 -- SiC TFTs --> I[Thermal Stability >200C];
          D1 & D2 & F & H -- Refractory Metals --> J[Reliable Electricals];
      end
  

3. Cross-Domain Application

Derivative 1.5: Integrated Chemical Sensor Array for Precision Agriculture

• Enabling Description: The TFT array substrate is repurposed as a distributed chemical sensor array for precision agriculture. The first TFT acts as a sensitive readout transistor, while the storage capacitor is integral to a chemically-sensitive field-effect structure (ChemFET). The first gate electrode (lower capacitor plate) is exposed via selective etching of the overlying insulating layers and coated with a functionalized sensing material, such as a specific ion-selective polymer membrane (e.g., PVC-based membrane with valinomycin for potassium ion detection) or an enzyme-immobilized layer for glucose sensing in plant sap. The "second TFT" on the same substrate serves as a reference transistor or part of a differential measurement circuit to compensate for environmental drift. The connection member routes the gate voltage from the sensing element to the first TFT's channel, enabling a voltage change induced by chemical interaction to be transduced into a measurable current. This array provides real-time, in-situ nutrient levels in soil or plant tissue.

• graph TD
      A[Substrate] --> B{First Insulating Layer};
      B --> C1[First Channel Region (Sensor Readout TFT)];
      B --> D1[First Gate Electrode (Lower Capacitor/Sensing Plate)];
      D1 -- exposed & coated --> E[Chemically Selective Layer (e.g., K+ membrane)];
      E -- interacts with --> F[Analyte (e.g., Soil K+)];
      C1 -- overlaps --> D1;
      D1 --> G{Second Insulating Layer};
      G --> H[First Metal Pattern (Upper Capacitor Plate)];
      H -- overlaps --> D1;
      H --> I{Third Insulating Layer};
      I --> J[Connection Member];
      J -- electrically connects --> D1;
      J --> K[Second TFT (Reference/Amplifier)];
      subgraph Precision Ag Sensor System
          F --> E;
          E --> D1;
          D1 --> J;
          J --> L[Readout Circuitry];
          L -- to --> M[Wireless Transmitter (e.g., LoRa)];
      end
  

Derivative 1.6: Dynamic Haptic Feedback Array for Advanced Prosthetics

• Enabling Description: The TFT array substrate is configured as a flexible, high-resolution haptic feedback matrix for prosthetic limbs. Each "pixel" in the array is integrated with a micro-actuator for localized pressure or vibration feedback. The first TFT controls the driving voltage for a piezoelectric element or electrostatic actuator. The storage capacitor (first gate electrode and first metal pattern, separated by the second insulating layer) serves as a charge reservoir for the haptic actuator, providing the necessary transient current for quick response times. The first gate electrode is directly connected to one terminal of the piezoelectric element, and the first metal pattern forms the other. The second insulating layer acts as the piezoelectric material itself (e.g., AlN) or a high-capacitance dielectric for the electrostatic actuator. The second TFT acts as a local switch or feedback element for the haptic intensity. The connection member routes digital control signals from an embedded microcontroller to activate specific haptic points, creating programmable tactile sensations on the prosthetic skin.

• graph TD
      A[Flexible Polyimide Substrate] --> B{First Insulating Layer};
      B --> C1[First Channel Region (TFT Control)];
      B --> D1[First Gate Electrode (Actuator Terminal 1)];
      D1 -- overlaps --> C1;
      D1 --> E{Second Insulating Layer (Piezoelectric Material/Dielectric)};
      E --> F[First Metal Pattern (Actuator Terminal 2)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer};
      G --> H[Connection Member];
      H -- electrically connects --> D1;
      H --> I[Second TFT (Switch/Feedback)];
      subgraph Haptic Array for Prosthetics
          C1 -- controls voltage --> E & F;
          E & F -- generate --> J[Localized Haptic Feedback];
          H --> K[Microcontroller/Control Logic];
          K --> L[Prosthetic User Interface];
      end
  

4. Integration with Emerging Tech

Derivative 1.7: AI-Driven Self-Correcting Display Panel with Predictive Maintenance

• Enabling Description: The TFT array substrate is augmented with embedded micro-sensors (e.g., temperature, voltage, luminance feedback from test pixels) and an on-chip AI accelerator. During manufacturing and throughout the display's operational life, performance parameters (e.g., threshold voltage (Vth) drift of the first TFT, actual capacitance of the storage capacitor (first gate electrode and first metal pattern), pixel luminance) are continuously monitored. This data is fed to the integrated AI neural network, which utilizes a pre-trained model to predict potential failures, compensate for aging effects, and dynamically adjust pixel driving signals. The connection member routes these AI-generated compensation signals to the gate and data lines of the first TFTs, allowing for real-time, adaptive correction of display uniformity and color balance. The second TFTs can act as multiplexers for sensor readout. This system actively prevents display degradation and informs predictive maintenance schedules.

• graph TD
      A[TFT Array Substrate] --> B[First TFT (Driving TFT)];
      A --> C[Storage Capacitor];
      B -- output --> D[OLED (not shown)];
      C -- maintains Vgs --> B;
      A --> E[Embedded Sensors (Temp, V, Luminance)];
      E -- measures --> F[Performance Data (Vth, Cst, Luminance)];
      F --> G[On-Chip AI Accelerator (Neural Network)];
      G -- analyzes & predicts --> H[Compensation Values & Predictive Maintenance Alarms];
      H --> I[Integrated Microcontroller Unit];
      I -- adjusts --> B[First TFT Driving Parameters];
      I -- adjusts --> J[Display Driver IC (not shown)];
      subgraph AI Self-Correction & Prediction
          G -- trained with --> K[Historical Performance/Failure Data];
          I -- real-time adjustment --> B;
          H --> L[Maintenance System];
      end
  

Derivative 1.8: IoT-Enabled Environmental Sensor Matrix with Edge Computing

• Enabling Description: The TFT array substrate is transformed into an IoT-enabled environmental sensor matrix, equipped with edge computing capabilities for smart building or industrial environments. Each "pixel" integrates a micro-sensor (e.g., an NDIR gas sensor for CO2, a resistive humidity sensor) with the first TFT, which acts as a transducer or amplifier. The storage capacitor (first gate electrode and first metal pattern) serves as a local energy buffer or a timing element for an integrated oscillator, depending on the sensor type. The second TFT acts as an analog-to-digital converter or a data serializer. The connection member routes data from these local sensor nodes to a central, on-substrate edge microcontroller unit (MCU) with low-power wireless communication modules (e.g., Wi-Fi HaLow, LoRa). The MCU performs initial data aggregation, filtering, and local anomaly detection before securely transmitting compressed data to a cloud platform, reducing bandwidth and latency.

• graph TD
      A[Substrate] --> B{First Insulating Layer};
      B --> C1[First Channel Region (Sensor Transducer TFT)];
      B --> D1[First Gate Electrode (Sensor Interface)];
      D1 -- integrated with --> E[Environmental Sensor (CO2/Humidity)];
      D1 --> F{Second Insulating Layer};
      F --> G[First Metal Pattern (Capacitor/Bias)];
      G --> H{Third Insulating Layer};
      H --> I[Connection Member];
      I --> J[Second TFT (ADC/Serializer)];
      I --> K[On-Substrate Edge MCU];
      K --> L[Wireless Comm. Module (Wi-Fi HaLow)];
      subgraph IoT Sensor Matrix with Edge Computing
          E -- feeds data --> D1;
          J --> K;
          K -- processes --> M[Aggregated & Filtered Data];
          M --> L -- transmits to --> N[Cloud Platform];
      end
  

5. The "Inverse" or Failure Mode

Derivative 1.9: Self-Healing Dielectric Capacitor Array for Enhanced Durability

• Enabling Description: The second insulating layer, forming the dielectric of the storage capacitor (between the first gate electrode and first metal pattern), is engineered as a self-healing polymer composite. This composite incorporates microcapsules filled with a polymerizing healing agent (e.g., dicyclopentadiene monomer) and a dispersed catalyst (e.g., Grubbs' catalyst). In the event of a dielectric breakdown or minor crack formation due to mechanical stress or electrical overstress, the microcapsules rupture, releasing the healing agent into the damaged region. The healing agent then polymerizes upon contact with the catalyst, effectively repairing the dielectric and restoring the capacitor's functionality and capacitance stability. The connection member ensures continued electrical contact, and the first and third insulating layers can be conventional materials, offering a multi-layered self-healing architecture.

• graph TD
      A[Substrate] --> B{First Insulating Layer};
      B --> D1[First Gate Electrode];
      D1 --> E{Second Insulating Layer (Self-Healing Polymer Dielectric)};
      E --> F[First Metal Pattern];
      F --> G{Third Insulating Layer};
      G --> H[Connection Member];
      subgraph Self-Healing Capacitor Array
          D1 -- Dielectric --> F;
          E -- localized damage --> I[Microcapsule Rupture];
          I --> J[Healing Agent Release];
          J -- polymerization --> K[Dielectric Repair];
          K --> L[Restored Capacitance];
      end
  

Derivative 1.10: Diagnosable Low-Power "Guardian" Mode for System Integrity

• Enabling Description: The TFT array substrate features a "Guardian Mode" for maintaining system integrity and minimal functionality during prolonged standby or fault conditions. In this mode, the first TFTs (driving TFTs) and their associated display elements are globally de-energized, drawing minimal leakage current. However, dedicated low-power diagnostic circuits, utilizing the second TFTs and the connection member, remain active. These circuits are designed to periodically sample critical parameters, such as the voltage retained on the first gate electrode (lower capacitor plate), leakage currents across insulating layers, or specific fault indicators. This data is processed by an ultra-low power microcontroller (on-substrate or external) to detect potential component degradation or impending failures without fully activating the display. This mode allows for proactive fault detection, essential for applications requiring high reliability and extended operational life, while significantly conserving power.

• graph TD
      A[TFT Array Substrate] --> B[First TFT (Driving TFT) - De-energized];
      A --> C[Storage Capacitor];
      A --> D[Second TFT (Diagnostic/Monitoring)];
      A --> E[Main Display Controller - Inactive];
      D -- samples --> C[Voltage on First Gate Electrode];
      D --> F[Connection Member];
      F --> G[Ultra-low Power Microcontroller];
      G -- processes --> H[Diagnostic Data];
      subgraph Guardian Mode
          B -- global deactivation --> I[Extreme Power Saving];
          D -- active --> J[Continuous System Health Check];
          G -- outputs --> K[Fault Alerts/Status];
      end
  

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Derivatives for Claim 22: Connection Member Overlapping First Channel Region

Claim 22: A thin film transistor (TFT) array substrate comprising: a substrate; a first thin film transistor including a first channel region and a first gate electrode overlapping the first channel region, the first gate electrode and the first channel region being spaced apart from each other with a first insulating layer therebetween; a second thin film transistor including a second channel region and a second gate electrode overlapping the second channel region, the second gate electrode and the second channel region being spaced apart from each other with the first insulating layer therebetween; a second insulating layer disposed on the first and second gate electrode; a first metal pattern overlapping the first gate electrode, the first metal pattern and the first gate electrode being spaced apart from each other with the second insulating layer therebetween; a third insulating layer disposed on the first metal pattern; and a connection member disposed on the third insulating layer and electrically connecting the first gate electrode and the second thin film transistor, the connection member overlapping a portion of the first channel region in a plan view.

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1. Material & Component Substitution

Derivative 2.1: Multi-Layered Graphene Channel TFT with Vertical Interconnects for Compactness

• Enabling Description: The first and second channel regions for the TFTs are fabricated using multi-layered graphene, deposited via chemical vapor deposition (CVD) onto a SiO2/Si substrate. Graphene's atomic thickness and high carrier mobility enable exceptionally compact device footprints. The connection member, which specifically overlaps a portion of the first channel region (of the first TFT) in a plan view, utilizes a Through-Insulator Via (TIV) or Through-Channel Via (TCV) structure. This involves etching a high aspect ratio via through the insulating layers and potentially a portion of the channel itself, followed by metallic filling (e.g., Tungsten) to establish direct vertical electrical contact. This vertical interconnect strategy, combined with graphene channels, drastically minimizes the lateral routing area required, enhancing pixel density. The insulating layers are composed of hexagonal boron nitride (hBN) for excellent dielectric properties and ALD HfO2 for the gate dielectric.

• graph TD
      A[Substrate] --> B{First Insulating Layer (hBN)};
      B --> C1[Graphene First Channel Region];
      B --> C2[Graphene Second Channel Region];
      B --> D1[First Gate Electrode];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer (ALD HfO2)};
      E --> F[First Metal Pattern];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (hBN)};
      G --> H[Connection Member (Vertical Interconnect)];
      H -- overlaps --> C1[Portion of Graphene First Channel Region];
      H -- connects --> D1;
      H -- connects --> C2;
      subgraph Graphene TFT with Vertical Interconnect
          C1 & C2 -- High Mobility --> I[Ultra-Compact Layout];
          H -- TIV/TCV --> J[Minimised Footprint & Parasitics];
      end
  

Derivative 2.2: Organic TFTs (OTFTs) on Bio-degradable Substrate for Transient Electronics

• Enabling Description: The substrate is a bio-degradable polymer film, such as a polylactic acid (PLA) or regenerated cellulose derivative, for transient electronic applications (e.g., disposable sensors, eco-friendly smart packaging). The first and second TFTs employ organic semiconductor materials (e.g., poly(3-hexylthiophene) (P3HT) or TIPS-pentacene) for their channel regions, deposited using solution-based printing techniques like inkjet or gravure printing. The first and second gate electrodes, along with the first metal pattern (capacitor plates), are formed from conductive polymers (e.g., PEDOT:PSS) or flexible metallic inks (e.g., silver nanoparticle inks). Insulating layers are bio-degradable dielectrics, such as cross-linked polyvinylphenol (PVP) or a gelatin-based polymer. The connection member, also using conductive polymer tracks, is precisely patterned to overlap a portion of the organic first channel region, maintaining the compact pixel footprint and enabling a fully bio-degradable device.

• graph TD
      A[Bio-degradable Substrate (PLA)] --> B{First Insulating Layer (PVP)};
      B --> C1[Organic First Channel Region (P3HT)];
      B --> C2[Organic Second Channel Region];
      B --> D1[First Gate Electrode (PEDOT:PSS)];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer (Gelatin)};
      E --> F[First Metal Pattern (Conductive Ink)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (PVP)};
      G --> H[Connection Member (Conductive Polymer)];
      H -- overlaps --> C1[Portion of Organic First Channel Region];
      H -- connects --> D1;
      H -- connects --> C2;
      subgraph Bio-degradable OTFT Array
          A & B & C1 & D1 & E & F & G & H -- Bio-degradable --> I[Transient/Eco-friendly];
      end
  

2. Operational Parameter Expansion

Derivative 2.3: Terahertz (THz) Modulator Array with Integrated Waveguide for High-Speed Imaging

• Enabling Description: The TFT array substrate is adapted as a pixelated Terahertz (THz) modulator array for high-speed THz imaging or spectroscopic applications. The first TFT's channel region is composed of a material (e.g., highly doped silicon, graphene, or VO2) whose THz conductivity can be strongly modulated by the electric field from the first gate electrode. The connection member, critical for this derivative, is designed not only to overlap a portion of the first channel region but also functions as an integral part of a localized THz waveguide or a resonant antenna structure. This structure guides the incident THz radiation and enhances its interaction with the modulated channel, enabling efficient THz amplitude or phase modulation. The storage capacitor (first gate electrode and first metal pattern) provides the necessary bias and control voltages for the THz modulation. Insulating layers are chosen for low dielectric loss at THz frequencies (e.g., benzocyclobutene (BCB) polymer or fused silica).

• graph TD
      A[Substrate (Fused Silica)] --> B{First Insulating Layer (BCB)};
      B --> C1[THz-Interacting First Channel Region (Doped Si)];
      B --> D1[First Gate Electrode (Control)];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer (BCB)};
      E --> F[First Metal Pattern (THz Resonator/Bias)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (BCB)};
      G --> H[Connection Member (THz Waveguide/Antenna)];
      H -- overlaps --> C1[Portion of THz-Interacting First Channel Region];
      H -- connects --> D1;
      H -- connects --> C2[Second TFT (THz Driver)];
      subgraph THz Modulator Array
          C1 -- modulates --> I[THz Radiation Properties];
          H -- enhances interaction --> I;
          D1 & F -- control --> I;
      end
  

Derivative 2.4: Ultra-High Vacuum (UHV) Compatible TFT Array for Scientific Instrumentation

• Enabling Description: The TFT array substrate is meticulously designed for stable and reliable operation in Ultra-High Vacuum (UHV) environments (e.g., 10^-9 Torr or less), critical for advanced scientific instrumentation or specialized manufacturing processes. The substrate is UHV-grade single-crystal silicon. All materials comprising the semiconductor layers (silicon), insulating layers (thermally grown SiO2, sputtered Al2O3), and metallic patterns (Titanium/Platinum/Gold (Ti/Pt/Au) or Tungsten (W)) are selected for extremely low vapor pressure and minimal outgassing. The compact layout facilitated by the connection member overlapping the first channel region is crucial, as it minimizes the total surface area and internal volumes where gas molecules could be trapped and slowly released. All fabrication steps include rigorous cleaning protocols and annealing in UHV-compatible furnaces to eliminate residual contaminants.

• graph TD
      A[UHV-Grade Silicon Substrate] --> B{First Insulating Layer (Thermally Grown SiO2)};
      B --> C1[First Channel Region (Si)];
      B --> D1[First Gate Electrode (W)];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer (Sputtered Al2O3)};
      E --> F[First Metal Pattern (W)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (Thermally Grown SiO2)};
      G --> H[Connection Member (Ti/Pt/Au)];
      H -- overlaps --> C1[Portion of First Channel Region];
      H -- connects --> D1;
      H -- connects --> C2[Second TFT (UHV Compatible)];
      subgraph UHV TFT Array
          A & B & C1 & D1 & E & F & G & H -- UHV Compatible Materials & Processes --> I[Minimal Outgassing & Contamination];
          H -- Compact Layout --> J[Reduced Surface Area];
      end
  

3. Cross-Domain Application

Derivative 2.5: Integrated Neuromorphic Synapse Array for Edge AI Processors

• Enabling Description: The TFT array is repurposed as a dense neuromorphic synapse array, forming the core of an energy-efficient edge AI processor. The first TFT functions as a "synaptic transistor" whose channel conductance (representing a synaptic weight) is analog-programmable and non-volatile. This is achieved by integrating a memristive device directly within or adjacent to the first channel region. The storage capacitor (first gate electrode and first metal pattern) acts as a local analog memory element, storing the synaptic weight as a charge quantity on the first gate electrode, thereby modulating the first TFT's channel. The connection member, critically overlapping a portion of the first channel region, routes analog input "spike" signals to the first TFT and facilitates efficient read/write operations for updating the synaptic weights. The second TFT acts as a neuron activation function or an input multiplexer. The compact overlap design is essential for achieving high synapse densities required for neuromorphic computing.

• graph TD
      A[Substrate] --> B{First Insulating Layer};
      B --> C1[First Channel Region (Synaptic TFT with Memristor)];
      B --> D1[First Gate Electrode (Synaptic Weight Storage)];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer};
      E --> F[First Metal Pattern (Control Electrode)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer};
      G --> H[Connection Member];
      H -- overlaps --> C1[Portion of Synaptic TFT Channel];
      H -- connects --> D1;
      H -- connects --> C2[Second TFT (Neuron Activation/Mux)];
      subgraph Neuromorphic Synapse Array
          C1 -- implements --> I[Analog Synaptic Weight];
          D1 & F -- store --> J[Non-Volatile Weight];
          H -- routes --> K[Input Signals & Weight Updates];
          C2 -- processes --> L[Neuron Output];
      end
  

Derivative 2.6: Space-Hardened Radiation Detector Matrix with Integrated Readout

• Enabling Description: The TFT array is transformed into a robust, space-hardened matrix of radiation detectors for cosmic ray detection or particle physics experiments. The first channel region is composed of a radiation-sensitive material, such as amorphous silicon (a-Si:H) or a direct conversion material like Cadmium Telluride (CdTe), which generates charge upon interaction with high-energy particles. The first TFT functions as a low-noise charge amplifier for the detected signal. The storage capacitor (first gate electrode and first metal pattern) serves as a charge integration element for the amplified signal. The connection member, which overlaps a portion of the radiation-sensitive first channel region, is fabricated with radiation-hardened metallization (e.g., a thick gold (Au) or platinum (Pt) layer) and employs shielded routing to minimize single-event upsets (SEUs) and total ionizing dose (TID) effects. The second TFT functions as a reset or bias control transistor. The compact overlap design maximizes the fill factor of the radiation-sensitive area.

• graph TD
      A[Substrate (Radiation-Hardened Si)] --> B{First Insulating Layer};
      B --> C1[Radiation Sensitive First Channel Region];
      B --> D1[First Gate Electrode];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer (Radiation-Hardened Dielectric)};
      E --> F[First Metal Pattern];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer (Radiation-Hardened Dielectric)};
      G --> H[Connection Member (Radiation-Hardened Metal)];
      H -- overlaps --> C1[Portion of Radiation Sensitive Channel Region];
      H -- connects --> D1;
      H -- connects --> C2[Second TFT (Bias/Reset)];
      subgraph Space Radiation Detector
          C1 -- detects --> I[Incident Radiation];
          C1 -- amplified by --> J[First TFT (Charge Amplifier)];
          D1 & F -- integrates --> K[Charge Signal];
          H -- routes --> L[Radiation-Hardened Readout];
      end
  

4. Integration with Emerging Tech

Derivative 2.7: Machine Learning Inference Engine on Array Substrate with Resistive Memory

• Enabling Description: The TFT array substrate is re-engineered as a hardware accelerator for machine learning (ML) inference, integrating resistive random-access memory (RRAM) elements. The first channel region of the first TFT is formed in series with, or directly incorporates, an RRAM device (e.g., using TaOx or HfOx as the switching material). The first gate electrode and first metal pattern (capacitor) provide the precise voltage pulses for programming and reading the RRAM's resistance state, which represents a synaptic weight. The connection member, specifically designed to overlap a portion of the first channel region and RRAM device, routes analog input signals directly to the input of this combined TFT-RRAM element. The second TFT acts as an analog activation function (e.g., ReLU or Sigmoid approximation) or a current-to-voltage converter. This enables highly parallel, in-memory computing for efficient ML inference at the edge, leveraging the compact layout for dense weight matrices.

• graph TD
      A[Substrate] --> B{First Insulating Layer};
      B --> C1[First Channel Region (TFT with RRAM)];
      B --> D1[First Gate Electrode (RRAM Program/Read)];
      D1 -- overlaps --> C1;
      D1 & D2 --> E{Second Insulating Layer};
      E --> F[First Metal Pattern (RRAM Bias)];
      F -- overlaps --> D1;
      F --> G{Third Insulating Layer};
      G --> H[Connection Member];
      H -- overlaps --> C1[Portion of TFT/RRAM Channel];
      H -- connects --> D1;
      H -- connects --> C2[Second TFT (Activation/I-V Conv)];
      subgraph ML Inference Engine with RRAM
          C1 -- implements --> I[Synaptic Weight (RRAM)];
          H -- routes --> J[Analog Input Signals];
          D1 & F -- program/read --> I;
          C2 -- processes --> K[Inference Output];
      end
  

Derivative 2.8: Real-Time Performance Monitoring with Blockchain Identity and Provenance

• Enabling Description: Each TFT array substrate integrates unique Physical Unclonable Function (PUF) elements, generated from inherent, uncontrollable manufacturing variations in the first channel region's physical or electrical characteristics (e.g., random dopant fluctuations, grain boundary distribution). This PUF generates a cryptographic digital fingerprint for the substrate. The connection member, intentionally designed to overlap a portion of this PUF-generating first channel region, provides electrical access for robust, low-power readout of the PUF. Concurrently, performance data (e.g., threshold voltage drift of the first TFT, capacitance degradation of the storage capacitor) is continuously measured by the second TFT acting as a local sensor interface. This performance data, along with the PUF-generated immutable identity, is timestamped, cryptographically signed, and periodically uploaded to a distributed ledger (blockchain) for real-time, tamper-proof provenance and performance tracking throughout the product lifecycle, enhancing supply chain security and authenticated operational history.

• graph TD
      A[TFT Array Substrate] --> B[First TFT];
      A --> C[Storage Capacitor];
      B -- generates --> D[PUF Element (Physical Unclonable Function)];
      D -- derived from --> E[First Channel Region Variations];
      B -- monitors --> F[Performance Data (Vth, Cst)];
      F --> G[Second TFT (Sensor Interface)];
      G --> H[Connection Member];
      H -- overlaps --> D[Portion of First Channel Region];
      H -- transmits --> I[PUF ID + Performance Data];
      I --> J[Cryptographic Module];
      J -- signs --> K[Authenticated Data Packet];
      K --> L[Blockchain Network];
      subgraph Blockchain Identity & Provenance
          D -- unique & immutable --> M[Digital Fingerprint];
          I -- real-time tracking --> N[Lifecycle History];
      end
  

5. The "Inverse" or Failure Mode

Derivative 2.9: Graceful Degradation Mode with Fault-Tolerant Redundancy in Channel Layer

• Enabling Description: The TFT array substrate is designed with localized, fine-grained redundancy within the first channel region to enable graceful degradation upon localized failure. Each "first channel region" is segmented into multiple sub-regions, with only one active at any given time. The connection member, overlapping a portion of this segmented first channel region, includes a micro-reconfigurable interconnect matrix (e.g., using laser-fusible links or non-volatile switches). In the event a primary active channel segment or the associated first TFT is detected as faulty (e.g., by a change in source-drain current characteristics), an on-substrate control logic (potentially utilizing the second TFT as a fault detection and reconfiguration controller) can reconfigure the connection member's interconnects to bypass the faulty segment and activate a redundant, adjacent channel segment. This ensures continued operation with minimal loss of performance, preventing a complete pixel blackout and improving overall display reliability.

• graph TD
      A[TFT Array Substrate] --> B[Primary First TFT/Capacitor];
      A --> C[Redundant First TFT/Capacitor Elements];
      B -- contains --> D[Segmented First Channel Region (Primary)];
      C -- contains --> E[Segmented First Channel Region (Redundant)];
      F[Connection Member] -- overlaps --> D;
      F -- includes --> G{Reconfigurable Interconnect Matrix};
      G -- routes --> H[Signal Path];
      I[Fault Detection Logic (via Second TFT)] -- detects --> J[Fault in Primary Channel Segment];
      J --> G[Reconfigures];
      G -- reroutes --> K[Signal to Redundant Channel Segment];
      subgraph Fault-Tolerant Redundancy
          D & E -- Segmentation --> L[Localized Fault Handling];
          G -- Reconfiguration --> M[Graceful Degradation];
      end
  

Derivative 2.10: Environmental Feedback-Induced Hibernation Mode with Contextual Awareness

• Enabling Description: The TFT array substrate integrates multiple ambient environmental sensors (e.g., light, proximity, temperature, accelerometer) directly onto the substrate. The first TFT's channel region is designed to have tunable sensitivity to one of these parameters, providing a contextually aware trigger. The storage capacitor (first gate electrode and first metal pattern) stores a dynamically adjustable environmental threshold profile. When the aggregated environmental data indicates specific conditions (e.g., dark, no motion, low temperature), the second TFT (acting as a multi-modal control gate) triggers a sophisticated "Hibernation Mode." In this mode, the connection member, which overlaps a portion of the first channel region, selectively powers down or puts the first TFT and related display elements into an ultra-low power state, retaining critical data in the capacitor but suspending active display operation. The contextual awareness prevents unnecessary activation and optimizes power consumption significantly.

• graph TD
      A[TFT Array Substrate] --> B[First TFT];
      A --> C[Storage Capacitor];
      A --> D[Multi-modal Environmental Sensors];
      B -- tunable sensitivity to --> D;
      C -- stores --> E[Dynamic Environmental Threshold Profile];
      D -- provides --> F[Real-time Environmental Data];
      F -- compared with --> E;
      G[Second TFT (Multi-modal Control Gate)] -- triggers --> H[Contextual Hibernation Mode];
      I[Connection Member] -- overlaps --> B[Portion of First Channel Region];
      I -- in hibernation mode --> J[Selective Power Down/Ultra-Low Power State];
      subgraph Contextual Hibernation
          D --> G;
          E --> G;
          H --> J;
          J --> K[Optimized Power Savings & Longevity];
      end
  

---

Combination Prior Art Scenarios with Open-Source Standards

These scenarios illustrate how the core concepts of US Patent 10720483 (stable capacitor structure, TFT array, pixel control) can be combined with existing open-source standards to yield obvious prior art disclosures.

1. Combination with RISC-V Microcontroller Core (ISA) for On-Panel Processing:

   • Scenario: Integrate a low-power, open-source RISC-V microcontroller (MCU) core, such as the PicoRV32 (available under the permissive MIT license), directly onto the display array substrate. This MCU would be implemented using the same thin-film transistor (TFT) technology as the pixel array itself, either amorphous silicon (a-Si), polysilicon (poly-Si), or Indium Gallium Zinc Oxide (IGZO) TFTs. The RISC-V MCU would be strategically placed in the display's non-display area or integrated into the gate/source driver peripheral logic.
   • Enabling Description: The RISC-V MCU core on the display substrate, utilizing TFTs, is tasked with managing pixel-level compensation and diagnostic routines. It reads pixel performance data (e.g., threshold voltage variations of the driving TFTs (first TFTs), actual capacitance values of the storage capacitors (first gate electrode and first metal pattern)) via dedicated sensing TFTs (second TFTs) and the connection members. Based on this data and firmware implementing open-source algorithms, the RISC-V MCU calculates and applies dynamic compensation values to the pixel drive signals, enhancing display uniformity and mitigating artifacts caused by manufacturing variations or aging. The stable capacitance of the storage capacitors, as enabled by the electrode overlap and opening design of US10720483, is crucial for accurate and reliable pixel state retention during these compensation cycles. Communication between the RISC-V core and the main display controller can occur via a simple, open-standard serial interface (e.g., SPI) also implemented with TFTs.
   • Relevance: This combination demonstrates that leveraging an open-source processor instruction set architecture (ISA) with the patent's stable TFT-capacitor pixel array enables advanced, distributed intelligence directly on the display panel, which would be an obvious architectural improvement for managing display quality.

2. Combination with Open-Source Display Protocols (e.g., MIPI DSI Physical Layer) for Integrated Interface:

   • Scenario: Implement the physical layer and timing controller for an open-source display interface protocol, such as a subset of the MIPI DSI (Display Serial Interface) standard, using the same TFT array substrate manufacturing processes.
   • Enabling Description: High-speed data receivers, including deserializers and clock data recovery (CDR) circuits for MIPI DSI (which has publicly available specifications for its C-PHY/D-PHY physical layers), are designed and integrated into the gate driver and source driver integrated circuits located on the display's border. These circuits are fabricated using high-performance polysilicon (poly-Si) or IGZO TFTs, capable of operating at frequencies required by the MIPI DSI standard. The logic for pixel data decoding and distribution, as defined by the MIPI DSI protocol, is implemented using the array's TFTs. The critical aspect of the storage capacitor (first gate electrode and first metal pattern) from US10720483, with its inherent stability against overlay deviation, is essential for accurately retaining the pixel data after deserialization and during display refresh. The connection member's design and the robust insulating layers ensure reliable, high-integrity signal transmission for the decoded data and driving voltages across the array, adhering to the stringent timing requirements of MIPI DSI.
   • Relevance: This demonstrates that integrating open-source display interface standards directly onto the display substrate, utilizing the patent's core (stable pixel drive, robust connection), is an obvious step for reducing component count, simplifying manufacturing, and creating industry-standard compliant displays.

3. Combination with Open-Source Real-Time Operating Systems (RTOS) on Embedded Microcontrollers for Localized Control:

   • Scenario: An array of embedded microcontrollers (MCUs), implemented using the TFT fabrication process, runs an open-source Real-Time Operating System (RTOS) such as FreeRTOS (MIT license) or Zephyr RTOS (Apache 2.0 license) to manage localized display functions or integrate small-scale sensor networks.
   • Enabling Description: Small, dedicated microcontrollers (MCUs), each responsible for controlling a specific block of pixels or a local sensor cluster on the display array substrate, are implemented using TFTs. These MCUs run a lightweight open-source RTOS, enabling deterministic task scheduling for display refresh, responding to sensor inputs (if the array is also repurposed for sensing, as in derivatives 1.5 or 1.8), and managing communication with a main host processor. The stable storage capacitor (first gate electrode and first metal pattern) in each pixel, as described in US10720483, is fundamental for accurate pixel state retention and consistent RTOS operation. The compact connection member design, especially where it overlaps channel regions (as in Claim 22 and its derivatives), enables high-density integration of these MCUs and their associated local memory. The RTOS facilitates precise, real-time control over display timing and allows for distributed, intelligent processing capabilities across the panel.
   • Relevance: This combination highlights how the patent's reliable and compact pixel structure provides a suitable hardware platform for deploying open-source RTOS-driven embedded intelligence, creating display arrays with enhanced autonomy and programmability beyond traditional display drivers.