I'll search for the specific patent number 10489314 in the USPTO database and CAFC dockets.

Summary: U.S. Patent No. 10,489,314 ("US10489314B2")

I searched for the specific patent number 10489314 (and its B2 publication) and located authoritative records from Google Patents, the USPTO (PTACTS continuity records), Unified Patents, Patexia, and Federal Circuit/PTAB docket reporting. Results were specific to this patent number, not a similar one.

Bibliographic data (verified across Google Patents, USPTO, and court exhibits)

• Title: Memory module with data buffering
• Patent number / kind code: US 10,489,314 B2
• Assignee (owner): Netlist, Inc., Irvine, CA (US)
• Inventors: Jefferey C. Solomon, Irvine, CA (US); Jayesh R. Bhakta, Cerritos, CA (US)
• Application number: 15/857,519
• Filing date: December 28, 2017
• Issue (grant) date: November 26, 2019
• Priority date: March 5, 2004 (earliest provisional, 60/550,668); the '314 patent is a continuation in a long chain running back through 9,858,215 → 9,037,774 → 8,516,188 → 8,081,536 → 7,916,574 → 7,881,150 → 7,636,274 → 7,532,537 → 7,289,386 → 7,286,436
• Claims / drawings: 33 claims, 23 drawing sheets (per PTAB exhibit)
• Primary examiner: Gurtej Bansal
• Legal status: Google Patents lists the patent as "Expired – Lifetime" (earliest priority date March 5, 2004). Note: Patexia lists an expiration date of March 5, 2024, while Google Patents shows "anticipated expiration" of March 7, 2025 — there is some discrepancy in the reported expiration date, and I do not have an authoritative USPTO term-adjustment/terminal-disclaimer record to resolve it with high confidence.

Abstract (verbatim)

A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

Plain-language overview of the independent claims

The patent has three independent claims — claims 1, 15, and 28 (per Patexia's claim data; the full claim set is otherwise locked on that source). All three are directed to a memory module (e.g., a DIMM) with a printed circuit board, edge connections to a system slot, memory devices organized into N-bit-wide ranks, and buffering/control logic between the ranks and the memory bus.

• Claim 1 — Memory module with data-buffered rank switching at a specified data rate:
  A memory module that communicates with a memory controller over an N-bit-wide data bus at a specified data rate in response to memory commands. It has a PCB with edge connections, memory ICs arranged in multiple N-bit-wide ranks (a first rank for a first burst of data and strobes, a second rank for a second burst), circuitry between the ranks and the bus, and logic that responds to a first command with first control signals and then a second command with second control signals so data/strobe bursts pass through the circuitry at the specified data rate. Key limitation: the data transfers through the circuitry are registered transfers governed by an overall CAS latency of the module, and the circuitry adds a predetermined delay per transfer so the module's overall CAS latency is greater than the actual operational CAS latency of the memory ICs themselves.

• Claim 15 — Memory module with registered chip-select decoding and buffered data paths:
  A memory module where logic receives a first set of input address/control signals (including multiple input chip-select signals) and outputs registered chip-select signals corresponding to them — one active and the others non-active. The memory devices are arranged in N-bit-wide ranks that receive the registered chip-select signals, and the rank receiving the active signal handles the data/strobe burst for the command. Circuitry sits between the memory-bus data/strobe lines and the memory-device data/strobe pins. The data transfers are registered, performed in accordance with the module's overall CAS latency, which again is greater than each memory device's actual operational CAS latency.

• Claim 28 — Memory module with registered chip-select decoding and logic-pipeline buffering:
  Similar to claim 15 (logic receives input chip-select signals and outputs registered chip-select signals, with one active; ranks receive respective registered chip selects; circuitry between bus data/strobe lines and device pins), but specifically requires the circuitry to include logic pipelines that enable the data transfers between the selected rank and the memory bus in accordance with the module's overall CAS latency. As in claims 1 and 15, the transfers are registered and the circuitry adds a predetermined time delay per transfer so the overall CAS latency exceeds the actual operational CAS latency of the memory devices.

In plain terms, the invention is a memory module whose on-module logic/buffer registers and decodes the memory controller's commands and chip-selects, switches between ranks one-at-a-time, and adds a controlled extra clock of latency so that buffering the data path (for load isolation and higher capacity/density) is transparent to the system's timing model.

CAFC 2026 docket status (current as of today's date)

• Decision: On February 20, 2026, the Federal Circuit (Judges Dyk, Prost, and Reyna; opinion authored by Judge Reyna) affirmed the PTAB's October 2023 final written decisions upholding the validity of the '314 patent claims in Micron Technology, Inc. v. Netlist, Inc., Case Nos. 24-1312 and 24-1313 (Fed. Cir. 2026). Netlist publicly announced the affirmance on February 23, 2026; Micron has 90 days from the CAFC judgment to petition the U.S. Supreme Court.
• Underlying IPRs: IPR2022-00744 and IPR2022-00745 (both filed March 30, 2022, by Micron; institution November 1, 2022; final written decisions October 30, 2023). Per contemporaneous reporting (IPWatchdog, Netlist press release), the PTAB found Micron failed to show obviousness over the Halbert reference (US 2002/0112118 A1) — including on claim 1's "specified data rate" limitation and on the motivation to combine Halbert's Figure 2 and Figure 4 — and the CAFC rejected all of Micron's appeal arguments.
• Caveat: One aggregator (Patexia) lists IPR2022-00744 with a field reading "Claims Invalidated: 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14." This appears to be a data-labeling error, as it directly contradicts the PTAB's decisions, the CAFC's affirmance, and the parties' own statements. I would treat the "validity upheld" reporting as the reliable ground truth here.
• Related litigation: The '314 patent is asserted against Micron in the Western District of Texas (currently stayed), and the patent's family has seen prior district-court cases (e.g., W.D. Tex. 6:21-cv-00431; Idaho 1:24-cv-00001) and related CAFC appeals (24-1312, 24-1313).

Uncertainty notes

• I did not access the USPTO Patent Center full-text claim set directly; independent-claim text is from Patexia's copy of the granted patent, which matches the abstract and prosecution record found elsewhere. The identity of the three independent claims (1, 15, 28) is consistent with the IPR record (claim 1 in IPR2022-00744; claims 15 and 28 in IPR2022-00745, per the Fukami IP law summary of the CAFC decision).
• The exact expiration/status date is reported inconsistently (March 2024 vs. March 2025; Google marks the patent "Expired – Lifetime"). I could not verify the terminal-disclaimer/term-adjustment detail authoritatively.

I'll research litigation involving US Patent 10,489,314 ("Memory module with data buffering"). Let me search multiple sources.

I have strong leads. Let me verify the specific district court cases and their connection to the '314 patent.

Based on my research (searches of the Unified Patents litigation portal, PACER/Justia/CourtListener dockets, CAFC opinions, and Netlist's SEC filings), here is what is known about litigation involving US Patent No. 10,489,314 B2 ("Memory module with data buffering," Netlist, Inc.):

1. Netlist, Inc. v. Micron Technology, Inc., et al. — W.D. Tex. (infringement action where the '314 patent is asserted)

• Plaintiff: Netlist, Inc.
• Defendants: Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC
• Jurisdiction / Case Nos.: U.S. District Court for the Western District of Texas, Waco Division, 6:21-cv-00431 (and companion 6:21-cv-00430), filed April 28, 2021; transferred to the Austin Division on February 14, 2022, and renumbered 1:22-cv-00134 / 1:22-cv-00136 (the '314 patent is asserted in the 1:22-cv-00136 line).
• Patents asserted: Four patents — 10,489,314 (the "'314 Patent"), 9,824,035, 10,268,608, and 8,301,833 — against Micron's LRDIMM and NVDIMM enterprise memory modules (per Netlist's SEC filings and the parties' Joint Claim Construction Statement).
• Status: Stayed by Judge Lee Yeakel on May 11, 2022 pending resolution of Micron's IPRs on all four asserted patents. The stay was repeatedly continued; Judge Robert Pitman denied Netlist's motion to lift the stay and transfer venue on June 17, 2024 (noting the '314 IPRs were on appeal and the '314 patent expires in 2025). As of Netlist's February 23, 2026 press release, the WDTX case against Micron asserting the '314 and '608 patents remains stayed.

2. IPR2022-00744 — Micron v. Netlist (PTAB)

• Petitioner: Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology Texas LLC
• Patent Owner: Netlist, Inc.
• Filing date: Petition filed March 30, 2022; institution granted November 1, 2022
• Challenge: Claims 1, 2, 6, 8, and 12–14 alleged obvious over the "Halbert" reference (U.S. Patent App. Pub. 2002/0112119), alone and with JEDEC standards.
• Outcome: Final Written Decision October 30, 2023 — no challenged claims shown unpatentable (validity upheld in favor of Netlist).

3. IPR2022-00745 — Micron v. Netlist (PTAB)

• Petitioner / Patent Owner: Same as above (concurrently filed petition)
• Filing date: March 30, 2022; institution granted November 1, 2022
• Challenge: Claims 15–20 and 22–33, based on Halbert in view of JEDEC 21-C.
• Outcome: Final Written Decision October 30, 2023 — no challenged claims shown unpatentable (validity upheld in favor of Netlist).

4. Micron Technology, Inc., et al. v. Netlist, Inc. — CAFC Nos. 24-1312 & 24-1313 (consolidated appeals)

• Appellants: Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology Texas LLC
• Appellee: Netlist, Inc.
• Jurisdiction / Case Nos.: U.S. Court of Appeals for the Federal Circuit, 24-1312 (lead) and 24-1313
• Filing date: Micron filed its notice of appeal of the '314 IPR decisions on December 29, 2023; the appeals were docketed at the CAFC (briefing during 2024; argued before Judges Dyk, Prost, and Reyna).
• Outcome: Decided February 20, 2026 (non-precedential) — the CAFC affirmed both PTAB final written decisions, rejecting Micron's challenges to the "specified data rate" construction, the motivation-to-combine analysis, and the chip-select-signal issue. Netlist announced the affirmance on February 23, 2026; Micron had 90 days from the judgment to seek Supreme Court review (status of any cert. petition not confirmed in my searches).

5. Micron v. Netlist — D. Idaho / Idaho State Court (related family litigation; caveat below)

• Case No. 1:24-cv-00001 (U.S. District Court for the District of Idaho) — listed on the Google Patents/Unified Patents litigation record for the '314 patent family. It began as Micron's Idaho state-court bad-faith patent-assertion suit (Idaho Code § 48-1703) filed December 11, 2023 (Ada County Case No. CV01-23-19920), removed to federal court January 2, 2024, and assigned to Judge David C. Nye on January 18, 2024.
• Important caveat: Based on Netlist's SEC filings, Micron's Idaho complaint specifically concerns Netlist's assertion of the '833 patent (a different patent asserted in the same WDTX litigation that also includes the '314 patent) — not the '314 patent itself. I could not independently confirm any direct '314-patent allegation in the Idaho case, so treat this entry as "related litigation" rather than a direct '314 suit.
• Status: Remanded to Idaho state court on August 16, 2024; Netlist's appeal of the remand (CAFC No. 24-2281) remained pending; the Idaho State Court set a trial date of December 7, 2026 and appointed a discovery master in January 2026.

Summary table

Key caveats: (1) The Idaho case is flagged as related, not a direct '314-patent suit. (2) I found no litigation asserting the '314 patent against Samsung or any party other than Micron — the Samsung cases in the EDTX (2:22-cv-00293) involved different Netlist patents ('608, etc.). (3) The '314 patent's Google Patents record shows "Expired – Lifetime" status with anticipated expiration around March 7, 2025, which was also noted by Netlist in the WDTX stay-litigation briefing. (4) If a petition for certiorari was filed after the February 20, 2026 CAFC affirmance, it would not have been reflected in the sources I retrieved; I could not confirm one way or the other.

Proceedings overview

Two completed Inter Partes Reviews — both fully decided in favor of patent owner Netlist, Inc., with zero claims canceled. Per the structured USPTO ODP block in the prompt, the ODP API reports no AIA trial proceedings for US 10,489,314 "as of the most recent ingest" — but that is contradicted by the live public record, and per the operating rules I am treating the live record as authoritative: IPR2022-00744 and IPR2022-00745 (both Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology Texas, LLC v. Netlist, Inc.) were filed 2022-03-30, instituted 2022-11-01, and resolved by Final Written Decisions on 2023-10-30 holding all 29 challenged claims patentable. The Federal Circuit affirmed both FWDs on 2026-02-20 (Nos. 2024-1312/2024-1313, nonprecedential). Bottom line for a defendant: this patent is hardened, not wounded — no claim of the '314 patent has ever been invalidated in an AIA trial, and the primary obviousness theory (Halbert) has now been rejected twice by the PTAB and once by the Federal Circuit.

IPR2022-00744 — Micron Technology, Inc. et al. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2022-03-30
• Status: Final Written Decision — Appealed → affirmed. (Unified Patents portal: "Final Written Decision," termination date 2023-10-30.) No claims invalidated.
• Judge panel: Institution panel of Jon M. Jurgovan, Daniel J. Galligan, and Nabeel U. Khan (APJ Khan authoring the institution decision, Paper 15, entered 2022-11-01). APJ Khan also authored the Final Written Decision (per Patexia).
• Petition grounds (all pre-AIA § 103(a), per the institution decision):
  • Claims 1, 2, 6, 8, 12–14: obvious over Halbert (US 2002/0112119 A1, filed 2002-03-13, published 2002-08-15) alone;
  • Claims 3, 9, 10: obvious over Halbert + JESD21-C (JEDEC Standard 21-C, PC2100/PC1600 DDR SDRAM Registered DIMM Design Specification, Jan. 2002);
  • Claim 5: obvious over Halbert + JESD79-2A (DDR2 SDRAM Specification, Jan. 2004).
  • Challenged claims: 1–3, 5, 6, 8–10, 12–14 (independent claim 1 plus its challenged dependents), supported by the declaration of Dr. Vojin G. Oklobdzija.
• Institution decision: Granted 2022-11-01 on all grounds as to all challenged claims. The panel declined Netlist's request for discretionary denial under 35 U.S.C. § 314(a) based on the two concurrently filed petitions, agreeing with Micron that the large number of asserted claims (29) could justify two petitions and noting no claim overlap between them.
• Final Written Decision (2023-10-30): No claims unpatentable. The dispositive issue was claim 1's "specified data rate." The Board construed the preamble as limiting and held that "the specified data rate" in the claim body is the same rate at which data is communicated between the memory module and the memory controller. Applying that construction, the Board found Halbert's ranks communicate one piece of data per clock cycle (1:1) while Halbert's module communicates two pieces per clock cycle to the system bus (2:1) — i.e., Halbert's ranks run at half the module's data rate. Disposition: "we determine that Petitioner has not proven, by a preponderance of the evidence, that claims 1-3, 5, 6, 8-10, and 12-14 of the '314 patent are unpatentable"; "ORDERED that claims 1-3, 5, 6, 8-10, and 12-14 of the '314 patent have not been shown to be unpatentable." The Board added that the dependent claims "depend directly or indirectly from claim 1, do not remedy the deficiencies discussed above and, therefore, also fail to show unpatentability."
• Settlement / termination: None — fully adjudicated; no settlement.
• Appeal: Micron appealed 2023-12-29; docketed as CAFC No. 2024-1312 (consolidated lead with 2024-1313). Issues: (1) whether the Board misconstrued "specified data rate"; (2) whether Halbert nonetheless rendered the limitation obvious under a broader construction. Disposition: affirmed on 2026-02-20 by Judges Dyk, Prost, and Reyna (opinion by Judge Reyna). The CAFC rejected Micron's "rate is just a ratio" argument, holding the claim "requires a data rate between components, not a ratio of rates across different pairs of devices," and that Micron's proffered ratios "cannot be squared with claim 1's plain language." (Opinion: https://cases.justia.com/federal/appellate-courts/cafc/24-1312/24-1312-2026-02-20.pdf; CourtListener: https://www.courtlistener.com/opinion/[10796819](/patent/10796819)/micron-technology-inc-v-netlist-inc/)
• Defensive value: For anyone facing assertion of the '314 patent, the only theory that has been tested to finality — Halbert-based obviousness against claim 1 and its dependents — is a proven loser. If you are Micron or in privity with Micron, that ground is estopped under § 315(e)(2). If you are a new defendant, you are not estopped but will be litigating against a claim-construction ruling and a CAFC affirmance squarely against you.

IPR2022-00745 — Micron Technology, Inc. et al. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2022-03-30
• Status: Final Written Decision — Appealed → affirmed. (Unified Patents portal: "Final Written Decision," termination date 2023-10-30.) No claims invalidated.
• Judge panel: Per Patexia, APJs Nabeel U. Khan, Patrick M. Boucher, and Jon M. Jurgovan, with APJ Khan authoring the Final Written Decision. (A PTAB-docket aggregator also lists other APJs — Galligan, Braden, Szpondowski, McShane — reflecting panel composition changes over the life of the case; the FWD panel per Patexia is Khan/Boucher/Jurgovan.)
• Petition grounds: All challenged claims — 15–20 and 22–33 (independent claims 15 and 28 plus challenged dependents; claim 21 was never challenged) — under pre-AIA § 103(a) over Halbert + JESD21-C (the same two references used in -744's secondary ground). Micron's theory combined Halbert's Figure 2 embodiment (active/non-active chip-select signals) with Halbert's Figure 4 memory module (registered data buffers).
• Institution decision: Granted 2022-11-01 (same day as -744) on the single ground as to all challenged claims. The Board again declined § 314(a) discretionary denial of the parallel-petition structure.
• Final Written Decision (2023-10-30): No claims unpatentable. The Board found no adequate motivation to combine: Halbert's Figure 4 relies on concurrently operated ranks to double throughput, and grafting Figure 2's active/non-active (non-concurrent) chip-select scheme onto Figure 4 "would eliminate concurrent operation and reduce performance"; Micron never explained why a skilled artisan would make a performance-sacrificing combination "accounting for the performance impact of not operating [the] ranks . . . concurrently." The Board separately found limitation 15.6 unsatisfied: even accepting Micron's theory, Halbert's Figure 4 sends the chip-select/control signals to the multiplexer, not to the ranks, and "[i]f the active and non-active signals are only used at the [multiplexer] and are not sent to the [ranks], then the combination does not show [ranks] that are 'configured to receive' registered chip select signals, as required by claim 15." Disposition: "we determine that Petitioner has not proven, by a preponderance of the evidence, that claims 15-20 and 22-33 of the '314 patent [are unpatentable]"; "ORDERED that claims 15-20 and 22-33 of the '314 patent have not been shown to be unpatentable." Dependent claims 16–20, 22–27, and 29–33 "stand with" their respective independent claims.
• Settlement / termination: None — fully adjudicated; no settlement.
• Appeal: Micron appealed 2023-12-29; docketed as CAFC No. 2024-1313 (consolidated with 2024-1312). Issues: (1) motivation-to-combine legal error (limitation in isolation vs. claim as a whole); (2) error in requiring explanation for combining non-concurrent chip selects with Halbert's concurrent mode; (3) construction of where "non-active" registered chip-select signals must be sent. Disposition: affirmed 2026-02-20. The CAFC held Micron's "in isolation" argument "rests on a mischaracterization of the Board's decision" (the Board properly evaluated "the subject matter as a whole" under KSR), found no legal error in considering the fundamental differences between Halbert's Figure 2 and Figure 4, and declined to resolve the construction dispute because Micron's alternative theory failed regardless — Halbert undisputedly sent the active chip-select signals to the multiplexer rather than the ranks.
• Defensive value: This proceeding closes off the combination variant of the Halbert theory against claims 15, 28, and their dependents — the claims that require registered chip-select decoding and buffered data paths. The CAFC's affirmance makes the Halbert + JESD21-C combination a dead letter as a practical matter for any defendant.

Strategic summary

Claim status — CANCELED vs. SUSTAINED vs. UNTESTED. Zero claims of the '314 patent have been canceled in any AIA proceeding. All 29 claims that were challenged were SUSTAINED: claims 1–3, 5, 6, 8–10, and 12–14 in IPR2022-00744, and claims 15–20 and 22–33 in IPR2022-00745. The four claims never tested in any IPR are claims 4, 7, 11, and 21 (all dependent). The only invalidity theory that has been adjudicated is § 103(a) obviousness built on Halbert (alone, or with JESD21-C / JESD79-2A), and it failed at institution-stage merits, at final decision, and on appeal. No § 102, no § 112, and no non-Halbert § 103 ground has ever been presented to the Board on this patent.

Estoppel landscape. Under 35 U.S.C. § 315(e)(2), Micron and its affiliates (and their privies) are barred from asserting in the W.D. Tex. litigation or the ITC any ground they raised or reasonably could have raised in the two IPRs — that sweeps in Halbert-based obviousness in all the permutations presented. For a defendant not in privity with Micron, estoppel does not apply, and § 102 anticipation by other references, non-Halbert § 103 combinations, and § 112 issues remain formally available. In practice, though, any defendant's Halbert theory must now be argued against a favorable-to-Netlist claim construction ("specified data rate" = same rate module↔controller and logic↔ranks) that the CAFC endorsed. Claims 4, 7, 11, and 21 were never challenged — a new petitioner could target them, but they depend from sustained claims, so the practical upside is limited.

Pattern signals. This is a coordinated, same-petitioner, two-petition campaign: Micron filed both IPRs the same day (2022-03-30), split the claim set cleanly (no overlap), and used Halbert as the primary reference in both — the Board expressly noted the parallel-petition structure and declined to exercise § 314(a) discretion against it. Netlist defended aggressively and has now won three CAFC validity affirmances within 12 months ('314, plus '608 and '523 against Micron/Samsung). The '314 patent is asserted against Micron in W.D. Tex. Case No. 1:22-cv-00136 (currently stayed, with the stay now ripe for lifting given the affirmance), and related family litigation appears in W.D. Tex. 6:21-cv-00431 and Idaho 1:24-cv-00001. Unified Patents appears only as the data aggregator surfacing the PTAB records — it is not a petitioner here, so there is no defensive-aggregator chain on this patent.

Recommended next steps

• If you are a defendant (or prospective defendant) facing assertion of the '314 patent: Do not build your invalidity case on Halbert. The FWDs (IPR2022-00744 and IPR2022-00745, both entered 2023-10-30) and the CAFC's affirmance (Micron Technology, Inc. v. Netlist, Inc., Nos. 2024-1312, 2024-1313, decided 2026-02-20) foreclose it as a practical matter, and if you are Micron or a privy it is estopped outright. If you are not estopped, the only untested ground space is (a) the four never-challenged dependent claims (4, 7, 11, 21), and (b) non-Halbert art under §§ 102/103 — but be prepared for the fact that the Board and CAFC have now endorsed a construction of "specified data rate" (same rate on both sides of the buffer) that will be difficult to argue around.
• If you are in the W.D. Tex. case (Netlist v. Micron, 1:22-cv-00136): The stay was premised on the pending CAFC appeal. With the affirmance now final (mandate presumably issued; Micron has 90 days from the 2026-02-20 judgment to petition for certiorari), expect Netlist to move to lift the stay and resume the infringement case on a patent whose validity just survived two IPRs and a Federal Circuit appeal. Plan for claim construction and infringement discovery, not invalidity-by-Halbert.
• Docket accuracy caveat: The USPTO ODP block in this prompt states no AIA proceedings are on file — that is stale or incomplete. The canonical record (Unified Patents PTAB portal: https://portal.unifiedpatents.com/ptab/caselist?patent.patent_number=[10489314](/patent/10489314); PTAB Papers 15/16 institution decisions; the 2023-10-30 FWDs; CAFC dockets 24-1312/24-1313) confirms the two proceedings above. If you are tracking the file yourself, verify the FWDs at USPTO PTAB E2E/PTACTS (the -744 institution decision is publicly hosted, e.g., Paper 15 at https://bannerwitcoff.com/wp-content/uploads/2022/11/IPR2022-00744.pdf) before citing them in any submission. No further IPRs, PGRs, or CBMs on this patent were found in any source searched.

I could not pull the USPTO Assignment Center's reel/frame database directly through the tools available to me in this session, and the web sources I could reach (Google Patents legal-events, Unified Patents portal, IPR/CAFC records, district-court filings) do not publish reel/frame numbers. I will state plainly below which facts are verified from those public records and which I could not verify, and I will not fabricate any recorded assignments.

Inventors

• Jefferey C. Solomon — Irvine, CA (US). Co-founder-level engineer at Netlist, Inc.; named inventor throughout Netlist's memory-module patent family dating to 2004–2006 (e.g., the '537, '386, '436, '274, '150, '574, '536, '188, '774, '215 patents and the '314 patent). Long-tenured Netlist employee; no evidence of departure within 12 months of the 2017 filing of the '314 application.
• Jayesh R. Bhakta — Cerritos, CA (US). Netlist executive (long-time VP of R&D / chief technical architect); named inventor across the same family. Still affiliated with Netlist through the 2020s (named on later Netlist filings, e.g., US 2021/0279194 A1 and Netlist patents through 2021+).

Unusual pattern check: not present. Both inventors remained with Netlist for years after the underlying 2004–2006 priority filings and the 2017 continuation filing; there is no inventor exodus preceding a portfolio sale.

Original assignee

Netlist, Inc. (Irvine, CA) is the entity named on the issued patent (front page assignee, "Netlist, Inc., Irvine, CA (US)") and remains the current assignee per Google Patents ("Current Assignee: Netlist Inc.") and the Unified Patents portal ("Assignees: Netlist Inc").

• Primary line of business: Designer and manufacturer of high-performance memory modules — DRAM DIMMs and, more recently, NVDIMM/hybrid memory products (HyperCloud®, Vault®, NVMe/Flash-DRAM hybrid lines). Public company, NASDAQ: NLST.
• Products embodying the claims: Yes. The '314 patent claims load-isolating, data-buffered rank switching with an added CAS-latency clock cycle — the core of Netlist's rank-buffered/load-reduced memory module products. Netlist has affirmatively represented in litigation that it practices the family (and the PTAB/CAFC record treats Netlist as the operating-company patent owner).
• Current status: Operating and actively litigating. Netlist, Inc. (not a shell, not dissolved, no bankruptcy) is asserting the '314 patent against Micron (W.D. Tex. 1:22-cv-00136; IPR2022-00744/00745; CAFC 24-1312/24-1313) and Samsung (E.D. Tex. 2:22-cv-00293, which lists the '314 patent among the asserted patents).

Assignment timeline

The USPTO Assignment Center records for this patent could not be retrieved with reel/frame identifiers in this session, so I cannot produce a verified chronological list of recorded assignments. What the available public records do establish:

• The '314 patent issued November 26, 2019 to Netlist, Inc. (application 15/857,519, filed December 28, 2017) as a continuation in Netlist's own chain back to the 2004/2005 priority applications (11/075,395 → 11/173,175 → 11/335,875 → … → 15/857,519). The entire chain names Netlist, Inc. as applicant/assignee.
• No post-issuance transfer away from Netlist is visible in any source I accessed: Google Patents legal events, Unified Patents, PTAB/CAFC records, and district-court filings all show Netlist, Inc. as owner and plaintiff from issuance through 2026 (the CAFC affirmance). There is no recorded transfer to an LLC, lender, or aggregator that surfaced in any search.
• Inventor-to-company assignments from Solomon and Bhakta to Netlist would have been recorded for the original family applications in the mid-2000s, but I could not verify their reel/frame numbers and will not guess at them.

Finding: As far as the accessible record shows, Netlist, Inc. has owned this patent continuously — original and current assignee. If the Assignment Center shows only the original inventor assignments and possibly financing/security filings, that would be consistent with what is visible; I could not confirm any specific reel/frame entries, and I flag this as a data gap rather than a finding of "no records."

Timeline diagram

timeline
    title Ownership of US 10489314
    2004 : Priority filed by Netlist inventors
    2005 : Netlist family applications filed
    2019 : Patent issued to Netlist Inc
    2022 : Netlist sues Micron and Samsung
    2023 : PTAB upholds validity
    2026 : CAFC affirms PTAB

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No transfer to any "IP / Patents / Licensing / Holdings / Ventures" LLC appears anywhere in the accessible record. Netlist, Inc. (a public operating company) is both original and current assignee.
2. Known asserter in the chain — not present as an NPE. Netlist, Inc. is a high-frequency plaintiff, but it is a public, product-selling operating company, not an entity on the classic NPE rosters (Acacia, Marathon, IV, Conversant, etc.). The IPR petitioner classification confirms the ecosystem's view: Netlist is listed as the patent owner/operating company in IPR2022-00744/00745 (Unified Patents PTAB case list shows petitioner = Micron operating-company entities, owner = Netlist).
3. Repeat correspondent across the chain — unclear / unverifiable. No reel/frame correspondent data was retrievable in this session, so I cannot test for a repeat recording attorney. No assertion is made either way.
4. Cascading transfers — not present. No chained LLC-to-LLC transfers within any 24-month window appear in the record.
5. Pre-litigation transfer — not present. The patent issued to Netlist in November 2019 and Netlist itself filed the first suits naming it (e.g., W.D. Tex. 1:22-cv-00136 filed January 2022; the Samsung E.D. Tex. suit in 2022). No assignment was recorded in the six months before those filings; Netlist was the owner from grant.
6. Bankruptcy fire-sale — not present. Netlist has not filed Chapter 7 or 11; there is no Kodak/Nortel-style auction record for this patent.
7. Privateering — not present. No operating company transferred the patent to a third-party NPE to sue on its behalf; Netlist sues in its own name.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN; Netlist still owns and asserts the patent.

Verdict

Operating-company assertion.

Netlist, Inc. — a public, product-selling memory-module maker — is the original and current assignee of US 10,489,314 (per the patent front page, Google Patents' current-assignee field, and the PTAB/CAFC litigation record), and it is asserting the patent against actual competitors (Micron and Samsung) in its own name. There is no recorded transfer to any shell entity, NPE, or aggregator in any source I could access, and no bankruptcy or privateering signal. The only caveat is that I could not verify the USPTO Assignment Center reel/frame-level records directly, so the absence of transfers is established from secondary authoritative sources (litigation, PTAB, Unified Patents) rather than from a primary reel/frame printout.

Verification links:

• USPTO Patent Assignment Center: https://assignmentcenter.uspto.gov/ (search Patent No. 10489314 for the authoritative reel/frame record)
• Google Patents legal events: https://patents.google.com/patent/US10489314/en
• Unified Patents patent page: https://portal.unifiedpatents.com/patents/patent/10489314
• Unified Patents PTAB case list for the patent: https://portal.unifiedpatents.com/ptab/caselist?patent.patent_number=10489314

I have reached the search-step limit, so I'll synthesize the answer from the retrieved sources. Here is my analysis, with explicit confidence flags where the record is incomplete.

1. Sources consulted & completeness caveat

The most complete retrieval of the references cited on the face of US 10,489,314 B2 came from PTAB Exhibit EX1055 in IPR2023-00454 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) v. Netlist, Inc.), which reproduces the patent's "References Cited — U.S. Patent Documents" page. The search result returned a truncated excerpt of that page (the list is ~100+ U.S. patents; the excerpt cut off at US 6,223,650 B1). I could not retrieve the complete face-of-patent list (including any foreign-patent and non-patent literature sections) within the available search steps, and Google Patents' citation tab was not fully accessible in the fetched material.

What this means for the § 102 analysis: I can identify and analyze the most relevant prior art with high confidence (the Halbert reference litigated in the IPRs, plus several well-known references on the retrieved list), but I cannot claim to have examined every citation on the face of the patent. Where I cannot confirm a reference's identity, I say so rather than guessing.

2. Primary prior art: Halbert (the IPR-tested reference)

Full citation: Halbert, John B. and Bonella, Randy M. (Intel Corporation), "Memory module having buffer for isolating stacked memory devices," US Patent Application Publication US 2002/0112118 A1, published August 15, 2002; application No. 10/263,995 filed October 2, 2002; issued as US 6,747,887 B2 on June 8, 2004. (The application is a continuation of US 6,487,102 B2, issued November 26, 2002, same title.)

Brief description: A memory module uses a buffer to isolate a stack (or pair) of memory devices from the memory bus, thereby increasing memory density while reducing capacitive loading. The buffer is coupled between first and second memory devices and the bus, and multiple buffered stacks are preferably coupled in a point-to-point arrangement. Halbert's Figures 2 and 4 depict the two alternative topologies that were at issue in the IPRs.

§ 102 anticipation analysis — claims potentially implicated:

• Claims 1, 15, and 28 (all three independent claims) are the ones Halbert most closely reads on, because it discloses the core combination of a module-level buffer between multiple memory devices and the data bus.
• However, anticipation is not established. Halbert alone does not disclose: (i) data transfers through the circuitry that are registered transfers governed by a module-level overall CAS latency greater than the actual operational CAS latency of the memory ICs (a limitation common to claims 1, 15, and 28); (ii) the module operating at a "specified data rate" as claimed in claim 1; or (iii) registered chip-select decoding with one active and the others non-active, as claimed in claims 15 and 28. These were precisely the limitations the PTAB found unmet in IPR2022-00744 and IPR2022-00745 (final written decisions October 30, 2023), where Micron's obviousness ground was based on Halbert. The PTAB rejected the challenge on the "specified data rate" limitation and on the motivation to combine Halbert's Figure 2 and Figure 4 embodiments, and the Federal Circuit affirmed on February 20, 2026 (Micron Technology, Inc. v. Netlist, Inc., Nos. 24-1312, 24-1313). Since obviousness failed on these features, the stricter single-reference anticipation standard under § 102 necessarily fails as well.
• Bottom line: Halbert is the single most relevant prior art of record, but it does not anticipate claims 1, 15, or 28 under § 102 as construed and decided by the PTAB/CAFC.

3. Other notable references retrieved from the face of the patent

From the EX1055 excerpt, the cited U.S. Patent Documents include (dates as printed on the patent):

References I can analyze with reasonable confidence:

• US 5,953,215 A (Karabatsos, September 14, 1999) — "Computer memory system" directed to a memory module (DIMM) with multiple memory devices and reduced loading on the memory bus. § 102 analysis: Potentially reads on the structural portion of claim 1 (multiple memory ICs, data path between ranks and the bus) and on the buffered/isolated rank-switching concept, but it predates the DDR registered-CAS-latency paradigm and does not disclose the claimed "registered" transfers with overall CAS latency greater than the memory ICs' operational CAS latency. It therefore does not anticipate claim 1, 15, or 28 in full.

• US 5,532,954 A (Bechtolsheim et al., July 9, 1996) and US 5,581,498 A (Ludwig et al., December 3, 1996) — both cited on the face of the '314 patent and also cited in Halbert's own reference list; they concern memory module/device arrangements with multiple banks or devices. § 102 analysis: Neither discloses the module-level data buffer with registered, CAS-latency-governed transfers of claims 1/15/28, so neither anticipates those claims alone. Their relevance is primarily as combination references (obviousness, § 103), not § 102 anticipations.

• The 1983–1990 references (Miyasaka 4,393,460; Mantellina 4,570,226; Lewandowski 4,631,705; Kassai 4,707,795; Ng 4,739,465; Chiba 4,868,823; Kosugi 4,953,149; Shubat 4,967,384; Tanaka 4,969,068; Morgan 4,980,855; Zulian 5,060,193) — all predate the DDR synchronous-burst era. § 102 analysis: These are early memory-module/bank-selection references; none plausibly discloses the claimed combination of N-bit-wide ranks, module-level buffering, registered chip-select decoding, and CAS-latency-governed registered transfers. At most they are background art on rank/bank selection (relevant to the "chip-select" decoding concept in claims 15 and 28, but not to the buffering/latency limitations).

4. § 102 claim-mapping summary (independent claims 1, 15, 28)

5. Important caveats

1. Incomplete citation list: The face-of-patent list was only partially retrieved (truncated at US 6,223,650 B1). There are almost certainly additional cited references (later U.S. patents, foreign patents, and NPL such as JEDEC standards — the specification itself incorporates JEDEC JESD79D) that I could not retrieve within the search limit. A complete § 102 sweep would require the full "References Cited" page from the USPTO or Google Patents.
2. No fabricated titles: For the many references where the retrieved text gave only number/date/inventor, I did not supply titles from memory; treat those rows as "identity confirmed as cited; content not independently verified."
3. Family members are not prior art: References in the '314 patent's own continuation chain (e.g., US 7,286,436, US 7,289,386, US 7,532,537, US 7,881,150, US 7,916,574, US 8,081,536, US 8,516,188, US 9,037,774, US 9,858,215 and publication US 2009/0201711 A1) share the March 5, 2004 priority date and are not § 102 prior art against the '314 patent.
4. Statutory note: Because the '314 patent's claims are entitled to a pre-AIA priority date (earliest: March 5, 2004), § 102 anticipation is properly analyzed under pre-AIA § 102(a)/(b); all references discussed above (published 1983–2004) qualify as prior art under that framework, and Halbert's August 15, 2002 publication date is comfortably before the priority date.

§ 103 Obviousness Analysis — U.S. Patent No. 10,489,314 B2 ("Memory Module with Data Buffering")

Preliminary note on sources

The user message references a "Prior Art section of this page," but no separately labeled Prior Art section was included in the materials provided. I have therefore reconstructed the prior-art landscape from (i) the IPR records for this exact patent (IPR2022-00744, IPR2022-00745), (ii) the Federal Circuit's February 20, 2026 affirmance (Micron Tech., Inc. v. Netlist, Inc., Nos. 24-1312, 24-1313, slip op.), (iii) the examiner's "References Cited" on the face of the '314 patent, and (iv) the related Halbert family. Where a conclusion below is the PTAB/CAFC's rather than my independent view, I say so.

1. The claimed invention and the dispositive limitations

The '314 patent has three independent claims — 1, 15, and 28 (IPR2022-00744 challenged claims 1, 2, 6, 8, 12–14; IPR2022-00745 challenged claims 15–20, 22–33). All three share the same architecture:

• a PCB with edge connections to a system module slot;
• logic that receives input address/control signals (including input chip-select signals) and outputs registered address/control signals — in claims 15 and 28, a plurality of registered chip-select signals with one active value and the rest non-active, received by N-bit-wide ranks of memory devices;
• circuitry coupled between the bus data/strobe lines and the device data/strobe pins (a data buffer);
• the logic issues control signals to the circuitry so that data/strobe bursts for the selected rank transfer through the circuitry;
• critically, the transfers are registered data transfers, and the circuitry adds a predetermined delay per transfer so that the module's overall CAS latency exceeds the actual operational CAS latency of the DRAM devices themselves;
• claim 1 additionally requires communication "at a specified data rate," which the PTAB construed (and the CAFC affirmed) as requiring the module↔controller data rate to equal the logic↔rank data rate — i.e., the buffered module must not run the bus faster than the ranks (CAFC slip op. at 10–13).

The two features that did the most work in the IPRs are (a) claim 1's equal module/rank data rate and (b) claims 15/28's registered active/non-active chip selects delivered to the ranks in a module whose ranks are selected one-at-a-time while the data path is buffered.

2. Prior-art inventory (all pre-dating the March 5, 2004 earliest priority date unless noted)

The examiner's "References Cited" on the face of the '314 patent is a long list of DRAM/module art (e.g., Dell, Bechtolsheim, Olarig, Karabatsos, Gillingham, Curtis, Dodd), but the operative invalidity battle in the IPRs was fought over Halbert + JEDEC.

3. Combination 1 — Halbert alone (claims 1, 2, 6, 8, 12–14)

Petitioner's mapping (IPR2022-00744): Halbert's Fig. 4 module 100 is the claimed "memory module"; controller 20 and bus 22 are the "memory controller" and "N-bit wide memory bus"; data interface 120 is the claimed "circuitry" between bus and device data/strobe pins; module controller 110 is the "logic"; ranks 140/142 are the ranks; the Fig. 5 timing shows read bursts from both ranks flowing through buffer 122 onto DQ/DQS.

Where it fails — the "specified data rate" limitation. Halbert's Fig. 5 timing (as the PTAB found, and the CAFC affirmed) shows each rank 140/142 outputting one m-bit word per clock cycle, while the module drives two m-bit words per clock cycle onto the system bus (T7n–T8n: one word per rank; T8–T9: both words serialized onto DQ). That is a deliberate 2:1 ratio — the entire point of Halbert's Fig. 4 architecture is "the memory bus transfer rate [doubles] for the same memory bus width and memory device speed." Claim 1, by contrast, requires the module↔controller rate and the logic↔rank rate to be the same ("specified data rate," with later recitations referring back to it). Halbert therefore teaches the opposite relationship — it teaches a module that runs the bus at twice the rank rate, which is precisely what claim 1 excludes. Micron's fallback (that "data rate" means any ratio, e.g., data-per-strobe-cycle) was rejected because it "cannot be squared with claim 1's plain language" (CAFC slip op. at 10–13).

Motivation analysis (why a POSITA would or would not get there): A POSITA (per the adopted level: advanced EE/CE degree + ~2 years, or BS + ~3 years, knowledgeable about DRAM/SDRAM standards and memory controllers) would readily understand Halbert's Fig. 4 bus-vs-rank rate relationship. The problem for obviousness is not capability but teaching away: converting Halbert's Fig. 4 module to run the bus at the same rate as the ranks would discard the architecture's stated benefit (2× bus throughput with slower devices). There is no independent motivation in Halbert to make that change, and the Board found Micron offered none. For the dependent claims that do not carry the data-rate limitation, Halbert alone is a much closer fit, but because each independent claim in the IPR2022-00744 ground incorporated the data-rate language, the ground failed as a whole.

4. Combination 2 — Halbert + JESD21-C (+ JESD79-2A) (claims 15–20, 22–33)

Petitioner's mapping (IPR2022-00745): Use Halbert Fig. 2's registered DIMM disclosure for the registered chip-select limitation — register 25 receives input bank selects B0_SEL#/B1_SEL# and outputs RB0_SEL#/RB1_SEL#, shown active-low/non-active-high in Fig. 3, to the chip-select pins of the two banks. Use Halbert Fig. 4's module 100 for the buffered data path (module controller 110 + data interface 120). Use JESD21-C Card N to show that a standard DDR DIMM has multiple input chip selects (S0/S1) and multiple registered chip selects (RS0/RS1) delivered to the ranks, and to show a "second plurality" of chip selects. Use JESD79-2A for CAS-latency programming. Halbert itself calls module 100 "just another design of a registered DIMM," which supplies a textual hook for importing registered-chip-select behavior into Fig. 4.

Where it fails — motivation to combine and the "ranks configured to receive" limitation. The Board found (and the CAFC affirmed) two independent defects:

1. No motivation to combine Fig. 2's non-concurrent chip-select operation with Fig. 4's concurrent module. Fig. 4 operates both ranks concurrently — both ranks exchange data with their registers during a single access, then the MUX serializes two words onto the bus. Halbert's Fig. 2 registered chip selects select one bank at a time (non-concurrent operation). Importing active/non-active registered chip selects into Fig. 4 to enable one rank at a time would convert the module from concurrent to non-concurrent operation and destroy the throughput advantage Fig. 4 exists to provide. Micron never explained "why a skilled artisan would have made such a combination, accounting for the performance impact of not operating [the] ranks . . . concurrently." That is a classic missing-motivation finding, not a legal error (CAFC slip op. at 14–18).
2. The combination does not meet "ranks . . . configured to receive" the registered chip selects. Micron's proposed implementation sent the active/non-active chip-select information to Fig. 4's MUX/DeMUX 124 (to steer which register's data is output), not to the ranks. As the Board explained, "[i]f the active and non-active signals are only used at the [multiplexer] and are not sent to the [ranks], then the combination does not show [ranks] that are 'configured to receive' registered chip select signals." The CAFC found this failure independently dispositive even without resolving the construction dispute (slip op. at 18–19).

The "overall CAS latency > device CAS latency" limitation (claims 15/28). This is the feature a better-crafted combination could most plausibly reach. The '314 patent's own specification states that the SPD reports a CAS latency one cycle higher than the DRAM's operational CL, and that "[t]his extra cycle of time . . . provides sufficient time budget to add a buffer." Registered-DIMM practice under JEDEC 21-C already accounts for register delay in timing/SPD reporting. A POSITA who combined Halbert Fig. 2's registered C/A path (one extra clock) with Fig. 4's registered data path (registers 126/128 and buffer 122 latching data) would understand that the module's effective/overall CAS latency must exceed the raw DRAM CL by the buffer's pipeline delay — otherwise the memory controller would sample data too early. So if the chip-select and rate limitations were overcome, the "greater CAS latency" element would be the easiest to prove as a routine, predictable timing adjustment (a "finite number of identified, predictable solutions" under KSR). The Board never reached it because the combination failed earlier in the claim chain.

5. Alternative combinations not pursued in the '314 IPRs

(a) Halbert '119 + US 6,747,887 (Halbert/Bonella buffer-isolation patent). The '887 patent supplies an explicit motivation for buffering that the '314 patent itself emphasizes: a buffer between the memory devices and the bus to reduce capacitive loading and enable higher density. Combining '887's load-isolation teaching with '119's buffered-module architecture and JEDEC 21-C's registered chip selects would fill the "why buffer at all" motivation gap more cleanly than Halbert alone. It does not cure the two defects above — '887 says nothing about registered active/non-active chip selects to ranks, and it does not alter Halbert Fig. 4's 2:1 data-rate teaching.

(b) Perego (US 6,502,161 / US 6,832,284) + JESD79-2. In a different Netlist-family IPR, the PTAB found "Perego + JESD79-2" rendered claims 1–29 of a related buffered-module patent obvious, relying on Perego's "JEDEC-compliant interface with its disclosure of a 64-bit module width" and data-path switching between ranks. Perego's point-to-point buffered memory subsystem is strong on the "buffer between ranks and bus" and "first/second data path" elements. But the '314's claims 15/28 add the registered active/non-active chip selects to the ranks and the CAS-latency differential — elements that were not central to the Perego ground in that other IPR — so Perego would need to be paired with JEDEC 21-C registered-DIMM teachings, and would still face the same "chip selects to the ranks, not the MUX" mapping problem the Board identified for Halbert.

(c) JEDEC 21-C registered-DIMM standard + JESD79-2A alone (no Halbert). A standard registered DIMM (register for C/A + PLL + SPD) supplies registered chip selects to the ranks, one active at a time, and the SPD-reported CL that exceeds the DRAM's operational CL by the register's one-cycle delay. What it lacks is the data buffer in the data/strobe path — in a conventional registered DIMM, DQ/DQS run directly from the controller to the DRAMs. The '314 claims require the data/strobe bursts to transfer through the circuitry, with the buffer adding delay. That is the genuine point of novelty separating the claims from ordinary registered-DIMM practice, and it is why Halbert's Fig. 4 (the buffered data path) is the indispensable primary reference.

6. Net assessment

• Claims 1, 2, 6, 8, 12–14: The strongest available combination is Halbert alone or Halbert + JESD79-2A, and it fails on claim 1's "specified data rate" limitation because Halbert affirmatively teaches a 2:1 module-to-rank rate ratio — the opposite of the claimed equal-rate relationship. Under the construction adopted by the PTAB and affirmed by the CAFC, Halbert teaches away from claim 1. A challenger would need a reference showing a buffered module whose bus and internal rank rates are equal; none was presented in the IPRs.
• Claims 15–20, 22–33: The strongest combination is Halbert (Fig. 2 registered chip selects + Fig. 4 buffered data path) + JESD21-C, and it fails for two independent reasons: (i) no motivation to graft non-concurrent rank selection onto Fig. 4's concurrent architecture because it destroys Fig. 4's throughput purpose; and (ii) the proposed chip-select routing goes to the multiplexer, not to the ranks as the claims require. The "overall CAS latency greater than device CAS latency" element is the most vulnerable limitation if those threshold problems were solved — registered-DIMM timing practice and the patent's own SPD/extra-cycle teaching make that a predictable design choice — but as the IPR record stands, the combination never gets there.
• Practical takeaway: The PTAB and CAFC have now twice rejected the Halbert-based combinations on motivation and claim-construction grounds. A future § 103 challenge would need (a) a buffered-module reference with equal bus/rank data rates (to attack claims 1/2/6/8/12–14), or (b) a reference combination that places registered active/non-active chip selects on the ranks of a non-concurrently-operated, data-buffered module without sacrificing the reference's stated performance goal (to attack claims 15–28). Perego, or a Halbert-variant focusing on the non-concurrent Fig. 2/Fig. 6-style embodiments, are the most plausible candidates, but none was developed in the record that produced the February 20, 2026 affirmance.

Key caveats: (1) The PTAB/CAFC rulings are the current ground truth for the combinations actually litigated; my analysis above identifies where a different combination or a different construction could change the outcome, not a ruling that any such combination succeeds. (2) The "Perego + JESD79-2" finding comes from a different Netlist-family IPR and should not be conflated with the '314 proceedings. (3) I could not verify the precise content of Halbert's Fig. 6/other embodiments beyond the record excerpts retrieved; if Halbert discloses a non-concurrent buffered mode with rank-level chip selects, that would materially strengthen a future challenge to claims 15/28.