US 10115439

US patent 10115439, titled "On-die termination of address and command signals," was issued on October 30, 2018, from an application filed on July 31, 2017. The inventors are Ian Shaeffer and Kyung Suk Oh. The original assignee was Rambus Inc., and it was later assigned to Signal LLP on October 15, 2025.

The abstract describes a system with multiple memory devices in a fly-by topology, each having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. Each memory device's ODT circuitry includes control registers for managing ODT of RQ bus signal lines. A first memory device stores a first ODT value in its control registers for termination, while a second memory device stores a different second ODT value for its termination.

A plain-language overview of each independent claim is as follows:

• Independent Claim 1: This claim describes a memory controller designed to manage a memory device. It includes circuits to drive command/address (CA) signals and a chip select signal onto a CA bus. The memory controller stores register values within the memory device, which represent the impedance values for on-die termination (ODT) to be applied to the inputs receiving CA signals. These register values specifically include ones that can selectively enable or disable the application of a chip select ODT impedance to the input receiving the chip select signal.

• Independent Claim 12: This claim also describes a memory controller for a memory device connected via a command and address (CA) bus. The memory device has ODT impedances that can be selectively connected to inputs receiving command and address information. The memory controller includes a command/address circuit to drive signals onto the CA bus and a first circuit to drive a clock signal onto the CA bus. The memory device contains register fields where the memory controller stores values to specify the ODT impedance values. Crucially, these register values include those that can selectively enable the application of a clock signal ODT impedance to the input that receives the clock signal.

• Independent Claim 20: This claim covers a memory controller that includes a circuit to drive command and address signals onto an external command and address bus, a first circuit to drive a chip select signal onto an external chip select signal line, and a second circuit to drive a clock signal onto an external clock signal line. The memory controller is configured to program register fields that store values. These register values specify one or more impedance values for on-die termination (ODT) impedances to be selectively applied to inputs receiving command and address signals. Additionally, these register values include specific values to selectively enable the application of a chip select signal ODT impedance to the input receiving the chip select signal, and also values to selectively enable the application of a clock signal ODT impedance to the input receiving the clock signal.

Regarding litigation, the patent family for US10115439B2 has litigation filed in the Texas Eastern District Court (case 2:26-cv-00093).

I could not find information regarding CAFC 2026 dockets for this specific patent number.US patent 10115439, titled "On-die termination of address and command signals," was issued on October 30, 2018, from an application filed on July 31, 2017. The inventors are Ian Shaeffer and Kyung Suk Oh. The original assignee was Rambus Inc., and it was later assigned to Signal LLP on October 15, 2025.

The abstract describes a system with multiple memory devices arranged in a fly-by topology. Each device has on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry in each memory device includes one or more control registers for managing the termination of signal lines on the RQ bus. A first memory device contains a first set of control registers storing a first ODT value to control its ODT circuitry, while a second memory device contains a second set of control registers storing a second ODT value, different from the first, for controlling its ODT circuitry.

A plain-language overview of each independent claim is as follows:

• Independent Claim 1: This claim describes a memory controller configured to manage a memory device. It comprises a command/address (CA) circuit for driving CA signals onto a CA bus and a driver for a chip select signal on the same bus. The memory controller stores register values within the memory device. These values represent one or more impedance values for on-die termination (ODT) to be applied to the memory device's inputs that receive the CA signals. Notably, these register values also include specific values to selectively enable the application of a chip select ODT impedance to the input receiving the chip select signal.

• Independent Claim 12: This claim pertains to a memory controller that manages a memory device connected via a command and address (CA) bus. The memory device features on-die termination (ODT) impedances that can be selectively connected to its inputs, which receive command and address information from the CA bus. The memory controller includes a command/address circuit to drive these signals onto the CA bus and a first circuit to drive a clock signal onto the CA bus. The memory device incorporates register fields where the memory controller stores values to define the ODT impedance values. Among these register values are those specifically designed to selectively enable the application of a clock signal ODT impedance to the input that receives the clock signal.

• Independent Claim 20: This claim outlines a memory controller with a circuit designed to drive command and address signals onto an external command and address bus, a first circuit to drive a chip select signal onto an external chip select signal line, and a second circuit to drive a clock signal onto an external clock signal line. The memory controller is configured to program register fields that store values. These register values are used to specify one or more impedance values for on-die termination (ODT) impedances, which are selectively applied to the inputs receiving command and address signals from the external bus. Furthermore, the register values include specific values to selectively enable the application of a chip select signal ODT impedance to the input receiving the chip select signal, and also values to selectively enable the application of a clock signal ODT impedance to the input receiving the clock signal.

Regarding litigation, the patent family for US10115439B2 has litigation filed in the Texas Eastern District Court (case 2:26-cv-00093).

I could not find authoritative information specifically detailing dockets for US patent 10115439 within the CAFC 2026 dockets. While there are general reports of CAFC decisions and ongoing patent litigation in 2026, none of the search results directly reference patent number 10115439 in the context of a CAFC docket.

I need to perform a more targeted search for litigation involving US patent 10115439. The initial search provided general information about patent litigation platforms and cases for other patent numbers, but no specific litigation details for US patent 10115439. The Google Patents page for US10115439B2 indicates "Family has litigation" and links to Unified Patents and Darts-ip, so these sources will be prioritized in the next search.

No litigation is currently known for US patent 10115439 based on the performed searches. The provided search results discuss general patent litigation procedures and specific cases involving other patent numbers, such as US 8,549,643, US 8,478,245, US 8,989,715, US 8,103,865, and US 10,621,228. There is no information about US patent 10115439 in these results. Additional specific searches are required to determine if there is any litigation related to US patent 10115439.

Proceedings overview

There are no AIA trial proceedings on file for US Patent 10,115,439. This gives a defendant a neutral defensive posture, as the patent has not been subjected to PTAB scrutiny.

Strategic summary

As there are no PTAB proceedings on file for US Patent 10,115,439, all claims (1-20) remain untested by AIA trial proceedings. This means there are no canceled or sustained claims from IPRs, PGRs, or CBMs.

The estoppel landscape is clear: since no proceedings have been filed, there are no prior art grounds barred by § 315(e)(2) for any potential petitioner. All prior art grounds remain available for a future challenge.

There are no patterns to observe regarding petitioners or patent owner's PTAB appeal aggressiveness, as no proceedings have taken place.

Recommended next steps

If you are a defendant currently facing assertion of US Patent 10,115,439, the absence of PTAB activity suggests that a post-grant challenge (e.g., an Inter Partes Review) could be a viable option to test the patent's validity. The lack of prior challenges means that the patent's claims have not been subjected to the rigorous scrutiny of an AIA trial, and thus no claims have been hardened against such challenges.

Inventors

• Ian Shaeffer (presumably Rambus Inc.)
• Kyung Suk Oh (presumably Rambus Inc.)

The inventors, Ian Shaeffer and Kyung Suk Oh, were likely employed by Rambus Inc. at the time of the underlying application's priority date (December 21, 2006) and the patent's filing date (July 31, 2017), given that Rambus Inc. was the original assignee. The Google Patents record indicates an assignment from the inventors to Rambus Inc. was recorded on July 3, 2018. No unusual patterns, such as inventors departing the original assignee within 12 months of filing, are immediately apparent from the provided information.

Original assignee

The original assignee named on the issued patent is Rambus Inc..

Rambus Inc. operates with a hybrid semiconductor business model, selling high-value chips (e.g., DDR5 memory interface chips for servers) and licensing intellectual property (IP) for integration into other companies' chips. They are known for providing advanced technology solutions and holding a robust portfolio of over 1000 issued patents. Rambus is an operating company that ships products embodying its claims through its chip sales and also monetizes its IP through licensing. Its current status is operating, and it is a public company traded on NASDAQ (RMBS).

Assignment timeline

• 2009-12-08 (executed) / recorded 2018-07-03 — Reel 046262/0738

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Oh, Kyung S.; Shaeffer, Ian P. (Inventors)
  • Assignee: Rambus Inc.
  • Correspondent: Not specified in the provided data.
  • Context: Initial assignment of patent rights from inventors to the operating company.

• 2025-09-29 (executed) / recorded 2025-10-15 — Reel 073085/0650

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Rambus Inc.
  • Assignee: Signal LLP
  • Correspondent: Not specified in the provided data.
  • Context: Transfer of patent rights from an operating company to a likely non-practicing entity.

Timeline diagram

timeline
    title Ownership of US 10115439
    2006 : Priority date
    2017 : Filed by Rambus Inc
    2018 : Inventors assign to Rambus
    2018 : Patent granted
    2025 : Assigned to Signal LLP
    2026 : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from Rambus Inc., an operating company, to Signal LLP. The "LLP" suffix often indicates a legal or investment entity rather than a product-producing company, and general searches for "Signal LLP" do not reveal a direct product-manufacturing business related to memory technology. Unified Patents, an anti-NPE organization, lists Signal LLP as a plaintiff in litigation involving this patent, reinforcing the likelihood that Signal LLP is a non-practicing entity. This transfer to a licensing-focused entity with no apparent products in commerce is a strong signal.

   • Citation: Reel 073085/0650, recorded 2025-10-15.

2. Known asserter in the chain — Present. The current assignee, Signal LLP, is identified by Unified Patents as actively engaged in patent litigation involving this patent, specifically noting a case filed in the Texas Eastern District Court. Unified Patents is an organization dedicated to deterring unsubstantiated or invalid patent assertions by Non-Practicing Entities (NPEs). Their identification of Signal LLP in litigation is a strong indicator that Signal LLP operates as a patent asserter.

   • Citation: "Current Assignee: Signal LLP" and "Family has litigation" with a link to a Texas Eastern District Court case filed by Unified Patents, as presented on the Google Patents page.

3. Repeat correspondent across the chain — Unclear. The provided patent text and Google Patents legal events do not explicitly state the name of the correspondent attorney or firm who filed the assignments for either recordation (Reel 046262/0738 and Reel 073085/0650). Therefore, it is not possible to assess whether the same correspondent recurs.

4. Cascading transfers — Not present. There are only two recorded assignments in the patent's history: from the inventors to Rambus and then from Rambus to Signal LLP. This does not constitute multiple consecutive assignments through chained LLCs in a short period.

5. Pre-litigation transfer — Present. The assignment from Rambus Inc. to Signal LLP was executed on September 29, 2025, and recorded on October 15, 2025 (Reel 073085/0650). A litigation case (2:26-cv-00093) involving this patent was filed in the Texas Eastern District Court in 2026. Given the current date (May 2026), this filing occurred within six months of the assignment, which is a strong signal for a pre-litigation transfer to enable assertion.

   • Citation: Reel 073085/0650, recorded 2025-10-15; Texas Eastern District Court case 2:26-cv-00093 filed in 2026.

6. Bankruptcy fire-sale — Not present. There is no information to suggest that Rambus Inc. filed for bankruptcy or that the patent was sold in bankruptcy proceedings.

7. Privateering — Present. Rambus Inc. is an operating company engaged in the semiconductor business. The patent was transferred from Rambus to Signal LLP, which appears to be a non-practicing entity engaged in assertion. This pattern is consistent with privateering, where an operating company transfers patents to an NPE that then asserts them against competitors, potentially benefiting the original operating company.

   • Citation: Reel 073085/0650, recorded 2025-10-15, showing transfer from Rambus Inc. to Signal LLP.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates with Signal LLP, which is identified as an asserter rather than a defensive aggregator like RPX or Unified Patents.

Verdict

NPE — high confidence. The patent was recently transferred from an operating company (Rambus Inc.) to Signal LLP (Reel 073085/0650, recorded 2025-10-15). This transfer occurred within six months of the first recorded infringement suit filed by Signal LLP in the Texas Eastern District Court (case 2:26-cv-00093, filed in 2026), strongly indicating a pre-litigation transfer to an assertion entity. Furthermore, Signal LLP is identified as a plaintiff in litigation by Unified Patents, an organization focused on countering NPE activity.

Verify on USPTO Assignment Center: https://assignmentcenter.uspto.gov/patent/index.html (Search by patent number 10115439).

Here is an analysis of the most relevant prior art for US Patent 10115439, identified from the examiner-cited patent references within the provided patent text.

Most Relevant Prior Art for US Patent 10115439

The most relevant prior art identified are those patent citations explicitly marked as "Cited by examiner" within the US10115439 patent document.

1. US20060107186A1

• Full Citation: US20060107186A1, International Business Machines Corporation, "System, method and storage medium for providing a high speed test interface to a memory subsystem".
• Publication/Filing Date:
  • Publication Date: 2006-05-18
  • Priority Date: 2004-10-29
• Brief Description: This patent describes a system and method primarily focused on providing a high-speed test interface for memory subsystems. It discloses memory devices with on-die termination (ODT) circuitry and a memory controller or test device that can provide a "termination control value" to set the termination. The disclosure refers to "dynamically adjustable on-die termination" and "programmable termination" within a memory system for testing purposes.
• Potential Anticipation (35 U.S.C. § 102):
  US20060107186A1, published on May 18, 2006, is prior art to US10115439 (priority date December 21, 2006) under 35 U.S.C. § 102(b). It generally anticipates the concept of dynamic and programmable on-die termination in memory devices, where a memory controller can influence ODT settings via a "termination control value". However, US10115439's independent claims (Claims 1, 12, 20) specify that the memory controller stores register values in the memory device to selectively enable application of ODT impedances for chip select signals and clock signals, in addition to general command/address signals. While US20060107186A1 discusses setting impedance values, it does not explicitly disclose the granular and selective enabling of ODT for these specific control signal types (chip select and clock) through register values stored in the memory device by the controller for operational rather than purely test scenarios. Therefore, while it anticipates the broad idea of dynamic ODT configuration by a controller via values, it likely does not fully anticipate the specific combination of elements and control mechanisms claimed in US10115439 for selectively enabling ODT on chip select and clock signals using register values stored in the memory device.

2. US6675272B2

• Full Citation: US6675272B2, Rambus Inc., "Method and apparatus for coordinating memory operations among diversely-located memory components".
• Publication/Filing Date:
  • Publication Date: 2004-01-06
  • Priority Date: 2001-04-24
• Brief Description: This patent describes a memory system and methods for coordinating operations among multiple memory components. It discusses a memory controller communicating various signals, including control and address signals, to memory components. The abstract explicitly mentions "an on-die termination circuit selectively connectable to one or more signal lines of a data bus" within the memory components.
• Potential Anticipation (35 U.S.C. § 102):
  US6675272B2, published on January 6, 2004, is prior art to US10115439 (priority date December 21, 2006) under 35 U.S.C. § 102(b). It broadly discloses memory systems and on-die termination. However, a key distinction from US10115439 is its explicit focus on "on-die termination circuit selectively connectable to one or more signal lines of a data bus". In contrast, US10115439 is specifically directed to on-die termination of address and command signals (RQ signals), which include chip select and clock signals. While US6675272B2 mentions control and address signals, it does not disclose the specific mechanism of a memory controller storing register values in the memory device to selectively enable ODT for distinct command and address signals such as chip select and clock, as detailed in the claims of US10115439. Therefore, it is unlikely to anticipate the specific subject matter of US10115439's claims.

To analyze the obviousness of US patent 10115439 under 35 U.S.C. § 103, we will examine combinations of prior art references that disclose the features claimed in US10115439. The patent generally claims a memory controller configured to program register values in a memory device to control on-die termination (ODT) impedances for address, command, chip select, and clock signals, particularly in a fly-by topology.

Key Features of US10115439's Claims:
The independent claims (Claims 1, 12, and 20) of US10115439 focus on a memory controller that:

• Drives command/address (CA) signals, chip select (CS) signals, and clock signals.
• Stores/programs register values in the memory device to control ODT impedances for these signals.
• The register values can selectively enable ODT for CS and clock signals.
• The register values can specify impedance values for the ODT.

Relevant Prior Art References and Their Disclosures:

Based on the provided patent text's "Citations" and "Family Cites Families" sections, the following references are highly relevant:

1. US7142461B2 (Micron Technology, Inc.): "Active termination control though on module register". This patent directly teaches the control of active termination using registers.
2. US6356106B1 (Micron Technology, Inc.): "Active termination in a multidrop memory system". This patent addresses the need for active termination in multidrop memory systems, which is explicitly identified as "fly-by" topology in US10115439.
3. US20050228912A1 (Walker Clinton F): "Memory address bus termination control". This reference focuses on the control of termination specifically for memory address bus signals.
4. US7123047B2 (Intel Corporation): "Dynamic on-die termination management". This patent suggests dynamic control (enable/disable) of ODT.
5. US5666078A (International Business Machines Corporation): "Programmable impedance output driver". This patent teaches the concept of programmable impedance.
6. WO1998004041A1 (Kaplinsky Cecil H): "Programmable dynamic line-termination circuit". This reference also teaches programmable and dynamic line termination.
7. KR100422451B1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): "method for controlling on-die termination and control circuit therefore". This broadly covers ODT control.
8. US10115439's own disclosure (Background/Description): The patent itself acknowledges the existence of certain concepts as known or obvious, such as the general termination of command, address, and control (RQ) signals, and the need for different impedance values for different signal classes. It also mentions that register control can override pin-based enable methods.

Obviousness Combinations and Rationale:

A person having ordinary skill in the art (POSITA) in semiconductor memory design, faced with known challenges in signal integrity and power consumption in high-speed memory systems, particularly those using fly-by (multidrop) topologies, would have been motivated to combine the teachings of the prior art references to arrive at the claimed invention.

Combination 1: US7142461B2 + US6356106B1 + US20050228912A1 + General Knowledge

• Claim 1 Analysis: This claim describes a memory controller storing register values in a memory device to control ODT impedances for CA signals and selectively enabling chip select ODT impedance via register values.

  • US6356106B1 discloses active termination in a multidrop (fly-by) memory system. A POSITA would be motivated to apply termination to address and command signals in such a topology to improve signal integrity, as reflections on these critical control lines are a known problem, as acknowledged in the background of US10115439.
  • US20050228912A1 specifically teaches controlling termination for memory address bus signals. It would be an obvious design choice for a POSITA to extend this control to chip select signals, which are closely related control signals for memory access and often routed similarly (as noted in US10115439, "chip select (CS) signals may also be routed with the same fly-by connection topology as the CA signals").
  • US7142461B2 teaches "active termination control though on module register". A POSITA, having identified the need for termination for CA and CS signals in a fly-by system, would be motivated to use this known and flexible method of register-based control to manage the ODT settings in the memory device. This provides the mechanism for the memory controller to "store register values, in the memory device" to control the ODT.
  • The "selective enablement" of chip select ODT impedance via register values would be an obvious design choice for power management and signal integrity optimization, as dynamic termination is a well-known concept (e.g., US5467455A "dynamic bus termination", US7123047B2 "Dynamic on-die termination management"). Enabling termination only when needed for specific signals (like a selected chip select) conserves power and can improve signal quality.
  • Motivation to Combine: The motivation for a POSITA would be to achieve robust and flexible signal integrity management for critical control signals (CA, CS) in high-speed, multidrop memory architectures while optimizing power consumption. Register-based control (US7142461B2) offers programmability and flexibility that would be highly desirable when implementing active termination (US6356106B1) for specific bus signals like address and chip select (US20050228912A1).

• Claim 2 Analysis (adds clock signal termination): This claim adds a circuit to drive a clock signal, and includes register values to selectively enable clock signal ODT impedance.

  • Building on the combination for Claim 1, it is well-established general knowledge in the art that clock signals, like CA and CS signals, are critical for timing and require proper termination to maintain signal integrity and prevent reflections, especially in high-speed memory systems. US10115439 itself notes that clock signals (CK/CKN) are "RQ signals" and are often terminated.
  • Motivation to Combine: A POSITA would naturally extend the already established register-based, selectively enabled ODT control (from Claim 1's combination) to clock signals. The goal would be to provide a comprehensive termination solution for all critical "RQ" (command, address, control, and clock) signals on the memory bus, using a consistent and flexible control mechanism.

• Claim 3 Analysis (adds specifying impedance value for clock ODT): This claim specifies that the register values can define the impedance value for the clock signal ODT.

  • US5666078A teaches a "Programmable impedance output driver", and WO1998004041A1 teaches a "Programmable dynamic line-termination circuit". These references establish the concept of programming termination impedance values.
  • Motivation to Combine: Given the inclusion of register-controlled ODT for clock signals (as per Claim 2), a POSITA would be motivated to make the value of that termination impedance programmable via registers. This allows for fine-tuning the termination impedance to optimize signal integrity based on system characteristics, environmental conditions, or different operating modes, a benefit explicitly recognized in US10115439 ("the impedance value of the termination may be determined by signal integrity studies, and may be different for different 'classes' of signals").

• Claim 5 Analysis (adds ODT enable signal): This claim adds a circuit to drive an ODT enable signal (e.g., first/second voltage) to enable/disable ODT for CA signals.

  • US7123047B2 teaches "Dynamic on-die termination management", implying an enable/disable mechanism for ODT. Many prior art references (e.g., US5467455A, US6894691B2, WO2004061690A2) disclose dynamic termination, which inherently involves enabling and disabling termination.
  • Motivation to Combine: While register values can control enabling/disabling, a dedicated ODT enable signal (e.g., a pin-based signal like the CAODT pin 16 in US10115439) provides a direct and fast mechanism for dynamic control. A POSITA would be motivated to integrate such a signal, alongside register control, to achieve efficient power management and real-time signal integrity adjustments. This aligns with the "power saving advantage" described in US10115439 for dynamically controlling termination.

• Claim 6 Analysis (adds override register values): This claim includes register values to override the ODT enable signal (from Claim 5).

  • US10115439's own description states, "Other embodiments may also utilize register control, either as an override, or as a replacement, for the enable pin configuration method. For example, in one embodiment register fields may be utilized to override the RQ ODT enable". This indicates that the concept of using register control as an override for a pin-based enable method was considered known or an obvious alternative.
  • Motivation to Combine: A POSITA, seeking to provide maximum flexibility and control, would find it obvious to implement register-based override capabilities for a pin-driven ODT enable signal. This allows for both dynamic, fast control via a pin and more persistent, configurable control via registers, giving system designers different levels of authority over the termination settings.

• Claim 10 Analysis (different register values for CA and CS ODT): This claim specifies that register values for CA signal ODT impedance are different from those for selectively enabling chip select ODT impedance.

  • US10115439's own description states, "the impedance value of the termination... may be different for different 'classes' of signals. For example, the chip select signal lines may have a different impedance value as compared to the address signal lines".
  • Motivation to Combine: Given the established understanding that different signal types may require different termination characteristics, it would be an obvious design choice for a POSITA to use separate (different) register fields or values to control the termination of distinct signal groups (like CA vs. CS). This allows for independent optimization of signal integrity and power consumption for each class of signal, maximizing system performance and efficiency.

Conclusion:
Claims 1, 2, 3, 5, 6, and 10 (and by extension, their dependent claims and similar independent claims like 12 and 20) of US10115439 would have been obvious to a person having ordinary skill in the art at the time of the invention. The motivation to combine the various prior art references would stem from well-known design goals in memory systems, such as improving signal integrity, reducing power consumption, and providing flexible and programmable control over critical signal parameters like termination impedance in complex bus topologies like fly-by architectures. The patent itself articulates many of these motivations, implicitly acknowledging them as desirable outcomes or known challenges in the art.