US 10115439

US patent 10115439, titled "On-die termination of address and command signals," was issued on October 30, 2018, from an application filed on July 31, 2017. The inventors are Ian Shaeffer and Kyung Suk Oh. The original assignee was Rambus Inc., and it was later assigned to Signal LLP on October 15, 2025.

The abstract describes a system with multiple memory devices in a fly-by topology, each having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. Each memory device's ODT circuitry includes control registers for managing ODT of RQ bus signal lines. A first memory device stores a first ODT value in its control registers for termination, while a second memory device stores a different second ODT value for its termination.

A plain-language overview of each independent claim is as follows:

• Independent Claim 1: This claim describes a memory controller designed to manage a memory device. It includes circuits to drive command/address (CA) signals and a chip select signal onto a CA bus. The memory controller stores register values within the memory device, which represent the impedance values for on-die termination (ODT) to be applied to the inputs receiving CA signals. These register values specifically include ones that can selectively enable or disable the application of a chip select ODT impedance to the input receiving the chip select signal.

• Independent Claim 12: This claim also describes a memory controller for a memory device connected via a command and address (CA) bus. The memory device has ODT impedances that can be selectively connected to inputs receiving command and address information. The memory controller includes a command/address circuit to drive signals onto the CA bus and a first circuit to drive a clock signal onto the CA bus. The memory device contains register fields where the memory controller stores values to specify the ODT impedance values. Crucially, these register values include those that can selectively enable the application of a clock signal ODT impedance to the input that receives the clock signal.

• Independent Claim 20: This claim covers a memory controller that includes a circuit to drive command and address signals onto an external command and address bus, a first circuit to drive a chip select signal onto an external chip select signal line, and a second circuit to drive a clock signal onto an external clock signal line. The memory controller is configured to program register fields that store values. These register values specify one or more impedance values for on-die termination (ODT) impedances to be selectively applied to inputs receiving command and address signals. Additionally, these register values include specific values to selectively enable the application of a chip select signal ODT impedance to the input receiving the chip select signal, and also values to selectively enable the application of a clock signal ODT impedance to the input receiving the clock signal.

Regarding litigation, the patent family for US10115439B2 has litigation filed in the Texas Eastern District Court (case 2:26-cv-00093).

I could not find information regarding CAFC 2026 dockets for this specific patent number.US patent 10115439, titled "On-die termination of address and command signals," was issued on October 30, 2018, from an application filed on July 31, 2017. The inventors are Ian Shaeffer and Kyung Suk Oh. The original assignee was Rambus Inc., and it was later assigned to Signal LLP on October 15, 2025.

The abstract describes a system with multiple memory devices arranged in a fly-by topology. Each device has on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry in each memory device includes one or more control registers for managing the termination of signal lines on the RQ bus. A first memory device contains a first set of control registers storing a first ODT value to control its ODT circuitry, while a second memory device contains a second set of control registers storing a second ODT value, different from the first, for controlling its ODT circuitry.

A plain-language overview of each independent claim is as follows:

• Independent Claim 1: This claim describes a memory controller configured to manage a memory device. It comprises a command/address (CA) circuit for driving CA signals onto a CA bus and a driver for a chip select signal on the same bus. The memory controller stores register values within the memory device. These values represent one or more impedance values for on-die termination (ODT) to be applied to the memory device's inputs that receive the CA signals. Notably, these register values also include specific values to selectively enable the application of a chip select ODT impedance to the input receiving the chip select signal.

• Independent Claim 12: This claim pertains to a memory controller that manages a memory device connected via a command and address (CA) bus. The memory device features on-die termination (ODT) impedances that can be selectively connected to its inputs, which receive command and address information from the CA bus. The memory controller includes a command/address circuit to drive these signals onto the CA bus and a first circuit to drive a clock signal onto the CA bus. The memory device incorporates register fields where the memory controller stores values to define the ODT impedance values. Among these register values are those specifically designed to selectively enable the application of a clock signal ODT impedance to the input that receives the clock signal.

• Independent Claim 20: This claim outlines a memory controller with a circuit designed to drive command and address signals onto an external command and address bus, a first circuit to drive a chip select signal onto an external chip select signal line, and a second circuit to drive a clock signal onto an external clock signal line. The memory controller is configured to program register fields that store values. These register values are used to specify one or more impedance values for on-die termination (ODT) impedances, which are selectively applied to the inputs receiving command and address signals from the external bus. Furthermore, the register values include specific values to selectively enable the application of a chip select signal ODT impedance to the input receiving the chip select signal, and also values to selectively enable the application of a clock signal ODT impedance to the input receiving the clock signal.

Regarding litigation, the patent family for US10115439B2 has litigation filed in the Texas Eastern District Court (case 2:26-cv-00093).

I could not find authoritative information specifically detailing dockets for US patent 10115439 within the CAFC 2026 dockets. While there are general reports of CAFC decisions and ongoing patent litigation in 2026, none of the search results directly reference patent number 10115439 in the context of a CAFC docket.