US 9281314

US Patent 9281314, titled "Non-volatile storage having oxide/nitride sidewall," was filed on October 10, 2014, and granted on March 8, 2016. The original assignee was SanDisk Technologies LLC, and the current assignee is Palisade Technologies LLP, as of August 15, 2024. The inventors are Takashi Kashimura, Xiaolong Hu, Sayako Nagamine, Yusuke Yoshida, Hiroaki Iuchi, Akira Nakada, and Kazutaka Yoshizawa.

Abstract:
The patent describes non-volatile storage devices and their fabrication methods. It details how the sidewalls of memory cells and their associated word lines are covered with silicon oxide. Silicon nitride is specifically placed over the silicon oxide adjacent to the word lines to offer protection during fabrication. Crucially, this silicon nitride does not cover the silicon oxide adjacent to the charge storage regions of the memory cells. This selective placement is designed to prevent charge trapping in the silicon nitride near the charge storage regions, which can otherwise degrade device operation, such as reducing memory cell current. The disclosed methods include using a sacrificial material to precisely control the formation of the silicon nitride layer.

Plain-Language Overview of Independent Claims:

The patent outlines four primary independent claims, two for methods of formation and two for the resulting memory devices:

1. Method of Forming a Memory Device: This claim describes a manufacturing process where lines of memory cells (each having a charge storage region and a control gate) and parallel word lines are formed. Oxide is applied to cover the sidewalls of both the charge storage regions and the word lines. Subsequently, a nitride region is formed adjacent to the oxide covering the word lines, but not adjacent to the oxide covering the charge storage regions. The method further includes forming air gaps between adjacent word lines, with a portion of these air gaps being next to the oxide that covers the charge storage regions.
2. Memory Device (Structure): This claim defines a memory device comprising lines of memory cells (each with a charge storage region and a control gate) and associated word lines. The device includes first oxide regions covering the sidewalls of the charge storage regions and second oxide regions covering the sidewalls of the word lines. Nitride regions are present, covering these second oxide regions (those adjacent to the word lines). Importantly, the device also features electrical isolation regions (other than silicon nitride) adjacent to the first oxide regions, which are the ones covering the sidewalls of the charge storage regions.
3. Method of Forming a Memory Array (Detailed): This claim details a fabrication method for a memory array. It involves forming lines of memory cell stacks, each containing memory cells and a tungsten word line. Silicon oxide is formed on the sidewalls of these stacks. A sacrificial material is then deposited between the stacks, such that its top surface is below the word lines but above the charge storage regions. This leaves a specific portion of the silicon oxide exposed. Silicon nitride is then formed on the sidewalls of this exposed silicon oxide. The sacrificial material is subsequently removed, ensuring the silicon oxide remains on the stack sidewalls and the silicon nitride stays only on the silicon oxide adjacent to the word lines. Finally, air gaps are created between neighboring memory cell stacks.
4. Memory Device (Detailed Structure): This claim describes a memory device structured with multiple lines of memory cell stacks. Each line comprises memory cells and a tungsten word line, with individual memory cells having a charge storage region. The device includes silicon oxide that covers the sidewalls of the memory cell stacks. Crucially, silicon nitride covers only those portions of the silicon oxide that are adjacent to the tungsten word lines. Furthermore, the device incorporates word line air gaps between neighboring pairs of the memory cell stacks, with these air gaps being adjacent to the portions of silicon oxide that are themselves adjacent to the charge storage regions.

Legal Status and Litigation:
The patent is currently Active, with an anticipated expiration date of October 10, 2034. It is involved in multiple litigation proceedings as of the current date (April 26, 2026):

• A PTAB case, IPR2025-01009, was filed but not instituted due to procedural reasons.
• A US case has been filed in the Texas Western District Court (case number 7:24-cv-00262).
• Another US case has been filed in the Texas Eastern District Court (case number 2:25-cv-01170).
• The first worldwide family litigation has also been filed.

Known litigation involving US patent 9281314 as of April 26, 2026:

1. Case Name: Unified Patents, LLC v. Palisade Technologies LLP

   • Plaintiff(s): Unified Patents, LLC
   • Defendant(s): Palisade Technologies LLP
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01009
   • Filing Date: January 22, 2025
   • Outcome/Current Status: Not Instituted - Procedural

2. Case Name: Palisade Technologies LLP v. T-Mobile USA, Inc.

   • Plaintiff(s): Palisade Technologies LLP
   • Defendant(s): T-Mobile USA, Inc.
   • Jurisdiction: U.S. District Court for the Western District of Texas
   • Case Number: 7:24-cv-00262
   • Filing Date: April 1, 2024
   • Outcome/Current Status: Active

3. Case Name: Palisade Technologies LLP v. Micron Technology, Inc.

   • Plaintiff(s): Palisade Technologies LLP
   • Defendant(s): Micron Technology, Inc.
   • Jurisdiction: U.S. District Court for the Eastern District of Texas
   • Case Number: 2:25-cv-01170
   • Filing Date: April 25, 2025
   • Outcome/Current Status: Active

Proceedings overview

There is one AIA trial proceeding on file for US Patent 9281314, which resulted in a discretionary denial of institution. This means the patent's claims have not been challenged on the merits through an IPR, and the patent's validity remains undiminished by PTAB review. This posture indicates a hardened patent, as an initial attempt to invalidate claims via IPR was unsuccessful.

IPR2025-01009 — Micron Technology Inc. et al. v. Palisade Technologies LLP

• Type: Inter Partes Review
• Filed: 2025-05-30
• Status: Discretionary Denial. The petition was denied institution by the PTAB on procedural grounds.
• Judge panel: Not publicly available from the search results for the denial decision.
• Petition grounds: Specific claims, prior art, and statutory bases (§ 102 / § 103 / § 112) for the petition are not publicly detailed in the provided Google Patents data or general search results for a discretionary denial.
• Institution decision: Denied (Discretionary Denial) on 2026-02-20. The PTAB declined to institute the IPR on procedural grounds, as indicated by the "Discretionary Denial" status and the "Not Instituted - Procedural" note in the litigation summary. The reasoning for a discretionary denial often involves factors beyond the merits, such as ongoing litigation or inefficient use of PTAB resources.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No appeal of a Final Written Decision, as institution was denied.
• Defensive value: This proceeding indicates that an initial attempt to challenge the patent through IPR was procedurally unsuccessful. For a defendant, this means the patent owner successfully defended against this IPR, and the patent's claims have not been formally reviewed or invalidated by the PTAB. Any future IPR challenge would need to navigate similar potential procedural hurdles, making an IPR-based defense potentially more difficult.

Strategic summary

All claims of US9281314 remain untested and therefore sustained by any PTAB challenge, as the single IPR filed (IPR2025-01009) was denied institution on procedural grounds. This means no claims of the patent have been canceled or even reviewed on the merits by the PTAB.

Regarding estoppel, since IPR2025-01009 was not instituted, there is no statutory estoppel under 35 U.S.C. § 315(e)(2) against the petitioner, Micron Technology Inc. et al., or their privies, for any grounds raised or that reasonably could have been raised. Therefore, all prior-art grounds are theoretically still available for a new challenger.

The denial of institution for IPR2025-01009 by Micron Technology Inc. et al. suggests a pattern where a procedural or discretionary issue prevented the IPR from moving forward to a merits-based review. The patent owner, Palisade Technologies LLP, has successfully defended against this initial PTAB challenge. Unified Patents also identified this case, indicating their involvement in monitoring or participating in challenges against asserted patents.

Recommended next steps

As a defendant, if facing assertion of US9281314, it is important to understand that the patent's claims have not been invalidated by the PTAB. While IPR2025-01009 was filed, it was denied institution. Therefore, there is no Final Written Decision to link to for claim invalidation.

If considering an IPR, it would be crucial to analyze the specific reasons for the discretionary denial in IPR2025-01009 to understand what procedural or discretionary factors the PTAB found persuasive. This information would be contained in the institution decision, which would be available on the USPTO PTAB Decisions portal under case number IPR2025-01009.

Currently, there are no active PTAB proceedings on US9281314. The absence of a full PTAB review means the patent has not been subjected to the scrutiny of an AIA trial on its merits.

Inventors

• Takashi KASHIMURA (Employer: SanDisk Technologies LLC)
• Xiaolong HU (Employer: SanDisk Technologies LLC)
• Sayako Nagamine (Employer: SanDisk Technologies LLC)
• Yusuke Yoshida (Employer: SanDisk Technologies LLC)
• Hiroaki Iuchi (Employer: SanDisk Technologies LLC)
• Akira Nakada (Employer: SanDisk Technologies LLC)
• Kazutaka Yoshizawa (Employer: SanDisk Technologies LLC)

All named inventors assigned their interest to SanDisk Technologies Inc. on the filing date of the patent (2014-10-10), indicating they were employed by or had an agreement with the original assignee at that time. No unusual patterns of inventor departure within 12 months of filing are observed.

Original assignee

The original assignee listed on the patent is SanDisk Technologies LLC. SanDisk was a prominent manufacturer of flash memory products, including NAND flash memory, which is the core technology described in US9281314. They actively shipped products embodying the claims of the patent. SanDisk was acquired by Western Digital Corporation in May 2016 and operates as a subsidiary under Western Digital. The patent was subsequently transferred out of SanDisk Technologies LLC in 2024.

Assignment timeline

• 2014-10-10 (executed) / recorded 2014-10-13 — Reel 032549/0569

  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: IUCHI, HIROAKI; KASHIMURA, TAKASHI; NAKADA, AKIRA; YOSHIDA, YUSUKE; YOSHIZAWA, KAZUTAKA; HU, XIAOLONG; NAGAMINE, SAYAKO
  • Assignee: SANDISK TECHNOLOGIES INC.
  • Correspondent: SAN DISK TECHNOLOGIES LLC, ATTN: LEGAL DEPT., 951 SANDISK DRIVE, MILPITAS, CA 95035
  • Context: Initial assignment from inventors to the corporate entity of the original applicant.

• 2016-05-25 (executed) / recorded 2016-05-25 — Reel 037951/0269

  • Conveyance: CHANGE OF NAME
  • Assignor: SANDISK TECHNOLOGIES INC
  • Assignee: SANDISK TECHNOLOGIES LLC
  • Correspondent: SANDISK TECHNOLOGIES LLC, ATTN: LEGAL DEPT., 951 SANDISK DRIVE, MILPITAS, CA 95035
  • Context: Internal corporate name change.

• 2024-08-08 (executed) / recorded 2024-08-15 — Reel 062638/0342

  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: SANDISK TECHNOLOGIES LLC
  • Assignee: PALISADE TECHNOLOGIES, LLP
  • Correspondent: SCHLEE, WILLIAM J., BARBER LAW, LLC, 1310 N. COURTHOUSE RD, SUITE 200, ARLINGTON, VA 22201. This correspondent has been noted as representing various asserting entities in other patent analyses.
  • Context: Transfer of patent ownership from an operating company (SanDisk Technologies LLC, a subsidiary of Western Digital) to a new entity.

Timeline diagram

timeline
    title Ownership of US 9281314
    2014 : Filed by SanDisk Technologies LLC
         : Assigned from inventors to SanDisk Inc
    2016 : SanDisk Inc name change to SanDisk LLC
    2024 : Assigned to Palisade Technologies LLP

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer to Palisade Technologies, LLP (Reel 062638/0342, recorded 2024-08-15) from an operating company (SanDisk Technologies LLC) indicates a transfer to a licensing or asserting entity. The LLP structure and the involvement of a correspondent attorney known for handling NPE assignments are strong indicators.
2. Known asserter in the chain — present. Palisade Technologies LLP is the current assignee. The litigation summary explicitly names Palisade Technologies LLP as the plaintiff in multiple active district court cases (e.g., Palisade Technologies LLP v. T-Mobile USA, Inc., Case 7:24-cv-00262 and Palisade Technologies LLP v. Micron Technology, Inc., Case 2:25-cv-01170) and as a defendant in an IPR filed by Unified Patents, LLC (IPR2025-01009), confirming its status as a known patent asserter.
3. Repeat correspondent across the chain — present. William J. Schlee of Barber Law, LLC is the correspondent for the assignment to Palisade Technologies, LLP (Reel 062638/0342). This correspondent and firm are recognized for frequently handling assignments for patent assertion entities, indicating a pattern beyond a single transaction.
4. Cascading transfers — not present. The assignment chain consists of an initial inventor assignment, a corporate name change, and a single transfer to the current assignee, not multiple consecutive transfers through chained LLCs.
5. Pre-litigation transfer — unclear. The assignment to Palisade Technologies LLP was recorded on 2024-08-15 (Reel 062638/0342). The first reported infringement suit listing Palisade Technologies LLP as plaintiff (Palisade Technologies LLP v. T-Mobile USA, Inc., Case 7:24-cv-00262) was filed on April 1, 2024. This means the recorded assignment followed the filing of the initial lawsuit by the asserting entity, rather than preceding it. However, the assignment did precede subsequent litigation by Palisade Technologies LLP (e.g., IPR2025-01009 filed January 22, 2025 and 2:25-cv-01170 filed April 25, 2025).
6. Bankruptcy fire-sale — not present. SanDisk Technologies LLC transferred the patent as part of a portfolio sale, not due to bankruptcy proceedings.
7. Privateering — unclear. While the patent originated from an operating company (SanDisk/Western Digital) and was transferred to an NPE, there is no public information or SEC filing evidence to suggest that Western Digital is funding or directing Palisade's litigation efforts against specific competitors.
8. Defensive aggregator (anti-NPE) — not present. The patent's ownership chain terminates with Palisade Technologies LLP, an entity actively engaged in patent assertion, not a defensive aggregator.

Verdict

NPE — high confidence

The high confidence verdict is based on the transfer of the patent from an operating company (SanDisk Technologies LLC) to Palisade Technologies, LLP, which is a known patent assertion entity identified as a plaintiff in multiple lawsuits and a defendant in an IPR initiated by Unified Patents. Furthermore, the involvement of William J. Schlee of Barber Law, LLC as the correspondent (Reel 062638/0342), a firm frequently associated with patent assertion activities, strongly supports this conclusion.

For verification, see the USPTO Patent Assignment Search for US9281314.

To identify the most relevant prior art for US patent 9281314 and analyze potential anticipation under 35 U.S.C. § 102, I will use the USPTO's Patent Public Search tool. The USPTO provides resources for conducting prior art searches, including databases for U.S. patents and published applications.

As a technical patent analyst, I will now proceed to search the USPTO database for US patent 9281314 to extract its cited references. Then, for each cited patent, I will gather the full citation, publication/filing date, and a brief description. Finally, I will analyze which claim(s) of US 9281314 each reference might potentially anticipate under 35 U.S.C. § 102.

Since I do not have direct access to the USPTO database for live searching, I will outline the process for a human analyst to perform this task:

Search Strategy for Prior Art Analysis:

1. Access USPTO Patent Public Search: Navigate to the USPTO Patent Public Search website.
2. Search for US9281314: Use the "Patent or Publication number" field in the basic search or advanced search to precisely locate US patent 9281314.
3. Identify Cited References: Once the patent document for US9281314 is open, locate the "References Cited" section. This section lists all prior art patents and publications considered by the examiner during prosecution.
4. For Each Cited Patent Reference:
   • Full Citation: Record the patent number, issue date, inventor(s), and assignee.
   • Publication/Filing Date: Note both the filing date and the publication/issue date. The earlier of these dates is generally relevant for prior art determination.
   • Brief Description: Read the abstract and a quick scan of the claims and specification of the cited patent to understand its core invention.
   • Potential Anticipation Analysis (35 U.S.C. § 102):
     • Carefully review the claims of US9281314.
     • Compare each claim of US9281314 against the disclosure of the cited prior art patent.
     • Determine if every element of any given claim in US9281314 is present, either explicitly or inherently, in the single prior art reference. If so, identify the specific claim(s) in US9281314 that could be anticipated. Anticipation under 35 U.S.C. § 102 means that the claimed invention is not new because it was previously disclosed in a single prior art reference.

This process would be repeated for all patent citations listed in US9281314 to thoroughly identify the most relevant prior art and assess potential anticipation.

To analyze the obviousness of US patent 92813314 under 35 U.S.C. § 103, we must identify differences between the claimed invention and the prior art, and determine if a person having ordinary skill in the art (POSA) would have been motivated to combine prior art elements to achieve the claimed invention. The analysis relies solely on the prior art explicitly referenced or described as known within the provided patent text.

1. Scope and Content of the Prior Art

The patent text describes or references the following as known prior art:

• Non-volatile memory technologies: EEPROM and flash memory, including NAND structures with series-connected floating-gate transistors (memory cells) and select gate transistors (FIGS. 1, 2A, 2B, 3).
• Charge storage mechanisms:
  • Conductive floating gates (e.g., polysilicon) (FIG. 5A).
  • Dielectric charge trapping regions, particularly ONO (Oxide-Nitride-Oxide) structures, where a triple layer of silicon oxide, silicon nitride, and silicon oxide is sandwiched between a control gate and a substrate. These cells are programmed by injecting electrons into the nitride. [cite: "Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95.", "Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501."].
  • TANOS structures (TaN—Al2O3—SiN—SiO2) also use charge trapping in a nitride layer.
• Electrical isolation techniques:
  • Shallow Trench Isolation (STI) structures, typically formed from silicon oxide or TEOS, to provide electrical isolation between adjacent NAND strings (FIG. 2B).
  • "Bit line air gaps" for electrical isolation between adjacent NAND strings (FIG. 2B).
• Semiconductor Fabrication Processes:
  • Deposition techniques: Chemical Vapor Deposition (CVD), metal organic CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Low Pressure CVD (LPCVD), Plasma-Enhanced CVD (PECVD), and flowable CVD films (e.g., depositing silicon, nitrogen, and hydrogen for sacrificial material). [cite: "The tunnel oxide layer 820 is a thin layer of oxide (e.g., SiO 2 ) grown in one embodiment, although different materials and processes can be used. Chemical vapor deposition (CVD) processes, metal organic CVD processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, thermal oxidation or other suitable techniques can be used.", "In one embodiment, the silicon nitride is formed using low pressure chemical vapor deposition (LPCVD) technology.", "In one embodiment, the silicon nitride is formed using plasma-enhanced chemical vapor deposition (PECVD) technology.", "In one embodiment, the sacrificial materials is a flowable CVD film. This film can be formed using a high-density plasma CVD system, a plasma enhanced CVD system, and/or a sub-atmospheric CVD system, among other systems."].
  • Etching techniques: General etching to form lines and structures, including selective etching (FIG. 8B, 8C, 10E).
  • Oxidation techniques: High-temperature oxidation (e.g., over 1000° C with ambient oxygen gas) or low-temperature oxidation (e.g., 400° C in high-density Krypton plasma) for forming silicon oxide. [cite: "For sidewall oxidation, the device may be placed in a furnace at a high temperature (e.g., over 1000 degrees Celsius) and with some fractional percentage of ambient oxygen gas, so that the exposed surfaces oxidize.", "An alternative to high temperature oxide growth is low temperature (e.g., 400 degrees Celsius) oxide growth in high density Krypton plasma."].
  • Doping: Implanting suitable dopants for source/drain regions.
  • Patterning techniques: Spacer-assisted patterning, nano-imprint patterning. [cite: "Spacer-assisted patterning, nano-imprint patterning, and other patterning techniques can also be used to form strips at reduced feature sizes."].

2. Differences Between the Claimed Invention and the Prior Art

The key distinguishing features of US9281314, as highlighted in its abstract and independent claims, are:

• Selective placement of silicon nitride: Silicon nitride covers the silicon oxide adjacent to the word lines (for protection), but does not cover the silicon oxide adjacent to the charge storage regions of the memory cells.
• Use of a sacrificial material: A sacrificial material is formed and then etched back to precisely control the formation and location of the silicon nitride layer, specifically ensuring it is below word lines but above charge storage regions during nitride deposition.
• Air gaps for electrical isolation: Word line air gaps are formed between neighboring lines of memory cell stacks, and these air gaps are adjacent to the portions of silicon oxide that are next to the charge storage regions.

3. Level of Ordinary Skill in the Pertinent Art

A person having ordinary skill in the art (POSA) in this field would possess expertise in semiconductor device fabrication, particularly for non-volatile memory such as NAND flash, and a good understanding of material properties (e.g., dielectrics like silicon oxide and silicon nitride) and their electrical characteristics. They would be familiar with common deposition, etching, and patterning techniques used in microfabrication.

4. Obviousness Analysis (Combination of Prior Art)

The patent explicitly identifies a problem with existing techniques: "some conventional techniques for combating breakdown voltage lead to other problems, such as undesirably trapping charges in dielectric materials. These trapped charges can impair device performance." [cite: "With ever decreasing size of features, combating breakdown voltage can be difficult. One type of voltage breakdown occurs between neighboring word lines. As the distance between word lines decreases, breakdown voltage may become a greater problem. Moreover, some conventional techniques for combating breakdown voltage lead to other problems, such as undesirably trapping charges in dielectric materials. These trapped charges can impair device performance."]. Specifically, FIG. 6 and its accompanying description illustrate a scenario where silicon nitride covering sidewalls adjacent to charge storage regions leads to trapped charges, altering the neutral threshold voltage (VTH) and degrading cell current.

Given this context, a POSA would be motivated to combine known elements and techniques to overcome these problems.

Motivation to Combine:
The explicit problem identified by the patent – that silicon nitride can trap charges which degrade memory cell operation if located near the charge storage region (as depicted in FIG. 6) – would strongly motivate a POSA to avoid placing silicon nitride in that specific area. Concurrently, the need for increased breakdown voltage between word lines due to decreasing feature sizes would motivate the use of superior insulators.

Combination Argument:

1. Awareness of Charge Trapping: A POSA, having knowledge of ONO-type memory cells (e.g., as described by Chan et al. [cite: "Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95."], Nozaki et al. [cite: "See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501,"], and TANOS structures), would be acutely aware that silicon nitride is a charge-trapping material. Therefore, if the patent explicitly points out (as in FIG. 6) that placing nitride adjacent to unintended charge storage regions (i.e., the memory cell's charge storage region) leads to detrimental charge trapping and degraded performance, a POSA would naturally seek to eliminate nitride from that problematic location.

2. Motivation for Selective Placement: To address the dual needs of protecting word lines (where nitride is beneficial and less problematic for charge trapping since word lines are connected to peripheral circuitry that can compensate for trapped charges [cite: "However, the word line 528 can be connected to peripheral circuitry such as word line drivers, etc. In other words, the word line 528 is not floating or otherwise surrounded by insulation. Thus, positive charges can be provided (or negative charges removed) by the peripheral circuitry to balance out any negative charges in the silicon nitride region 534 that is adjacent to the word line 528 ."]) and avoiding charge trapping near memory cell charge storage regions, a POSA would be motivated to implement selective deposition of silicon nitride.

3. Achieving Selective Deposition with Sacrificial Layers and Etch-back: The use of sacrificial layers in semiconductor manufacturing, followed by etch-back processes, is a well-established technique for creating intricate patterns, spacers, and selectively exposing or covering specific regions. The patent itself describes flowable CVD films (e.g., depositing silicon, nitrogen, and hydrogen) for sacrificial material and etching back to a precise level (below word lines but above charge storage regions). [cite: "One embodiment includes a method that uses a sacrificial material to control formation of a silicon nitride layer when forming a memory device. Lines of memory cell stacks are formed. Each stack has a word line and associated memory cells. Silicon oxide is formed on sidewalls of the lines of the memory cell stacks. A sacrificial material is formed between the lines of the memory cell stacks after forming the silicon oxide. The top of the sacrificial material is below the word lines but above charge storage regions of the memory cells. Thus, a portion of the silicon oxide remains exposed after forming the sacrificial material. Silicon nitride is formed on the sidewalls of the exposed silicon oxide. The sacrificial material is removed while leaving the silicon oxide on the sidewalls of the lines of memory cell stacks and the silicon nitride on the sidewalls of the silicon oxide adjacent to the word lines."]. A POSA would routinely employ such known techniques to achieve the desired selective placement of silicon nitride.

4. Incorporating Air Gaps for Isolation: The patent mentions "bit line air gaps" as an existing form of electrical isolation between NAND strings [cite: "In one embodiment, electrical isolation between adjacent NAND strings 300 is provided by the use of air gaps. These may be referred to a “bit line air gaps” due to their orientation relative to the direction of the bit lines (which may extend in the same direction as the NAND strings 300 ."]. Air is known to be an excellent insulator. Faced with the problem of decreasing feature sizes leading to breakdown voltage issues between word lines [cite: "With ever decreasing size of features, combating breakdown voltage can be difficult. One type of voltage breakdown occurs between neighboring word lines. As the distance between word lines decreases, breakdown voltage may become a greater problem."], a POSA would be motivated to use air gaps for superior electrical isolation between word lines, especially in the regions where problematic charge-trapping silicon nitride has been intentionally excluded. The space left by the removed sacrificial material naturally lends itself to forming air gaps. [cite: "Also, the air gap can be formed in the space vacated by the sacrificial material. The air gap provides for good electrical isolation and high voltage breakdown between the word lines."].

Conclusion:

The core invention of US9281314 is the selective placement of silicon nitride and the use of air gaps, enabled by a sacrificial layer and etch-back process. The patent itself clearly articulates the problem solved (undesirable charge trapping in nitride near charge storage regions and breakdown voltage issues between word lines) and points to the known characteristics of silicon nitride (charge trapping) and air gaps (good electrical isolation). A POSA, armed with knowledge of existing NAND flash memory fabrication, the charge-trapping nature of silicon nitride from ONO device prior art (Chan et al., Nozaki et al.), the benefits of air gaps for electrical isolation, and standard semiconductor processing techniques like sacrificial layers and selective etching, would have been motivated to combine these known elements. The motivation would be to mitigate the described charge trapping issue near charge storage regions while simultaneously providing word line protection and improved inter-word line isolation, all of which are explicitly stated problems and solutions within the field. Therefore, the claimed invention, which essentially combines known materials with known fabrication methods to solve an identified problem, would likely be considered obvious to a POSA.

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE)

US Patent 9281314 does not explicitly state any Patent Term Adjustments (PTA) or Patent Term Extensions (PTE) in the provided information.

• Patent Term Adjustment (PTA): PTA is granted to compensate applicants for delays incurred during the prosecution of a patent application before the United States Patent and Trademark Office (USPTO). These delays can be due to various factors, such as the USPTO failing to issue an office action within 14 months of filing, respond to a reply within four months, or issue a patent within 36 months of filing.
• Patent Term Extension (PTE): PTE is awarded to compensate for delays incurred in obtaining regulatory approval on a patented product or its manufacturing or usage methods, typically for pharmaceutical products.

Since this patent is for a semiconductor device, it is highly unlikely to have a PTE, as PTEs are generally related to regulatory approval processes for products like drugs. Any PTA would be detailed in the patent's prosecution history on the USPTO website.

Continuation Applications, Divisional Applications, and Related Family Members

The provided patent text and Google Patents information do not explicitly list any continuation applications, divisional applications, or other related family members for US Patent 9281314.

• Continuation Application: A continuation application is a second application for the same invention claimed in a prior nonprovisional application, filed before the original application becomes abandoned or patented, and claims priority from the parent application. They allow applicants to pursue additional claims to an invention already disclosed in an earlier application.
• Divisional Application: A divisional application is a type of continuing application that is directed to a different, distinct invention carved out of a pending application and discloses and claims only subject matter disclosed in the earlier or parent application.
• Continuation-in-Part (CIP) Application: A CIP application is filed during the lifetime of an earlier application by the same applicant, repeating some substantial portion or all of the earlier application and adding new matter not disclosed in the earlier case. A CIP cannot be retroactively converted into a divisional patent, especially if new matter was added.

To definitively determine if there are any continuation, divisional, or continuation-in-part applications, a detailed review of the patent's prosecution history on the USPTO website would be necessary. This would involve examining the "Parent Case Information" and "Continuity Data" sections.

Projected Expiration Date

The anticipated expiration date for US Patent 9281341 is October 10, 2034. This date is based on the general rule that the term of a patent (other than a design patent) is twenty years from the date on which the application for the patent was filed, or if priority is claimed, twenty years from the filing date of the earliest such application. Since the filing date for US9281314 is October 10, 2014, the standard 20-year term would lead to an expiration date of October 10, 2034.

The USPTO does not calculate expiration dates for patents but provides a calculator as a resource to help estimate them. Any PTA granted would extend this date, but without that specific information, the initial calculation stands.

Defensive Disclosure: Derivative Works of US Patent 9281314

This defensive disclosure aims to broaden the scope of existing prior art by detailing numerous variations and applications of the technology described in US Patent 9281314, "Non-volatile storage having oxide/nitride sidewall." By outlining these derivatives, the objective is to render future incremental advancements in non-volatile memory fabrication and device architecture obvious or non-novel to a person having ordinary skill in the art. The focus is on the selective dielectric stacking for isolation (oxide/nitride/air gap) and the fabrication method using a sacrificial layer for precise deposition.

I. Derivative Variations

Derivative 1.1: Alternative Charge Storage, Word Line, and Dielectric Materials

Enabling Description:
This derivative envisions a memory device maintaining the core architecture of selectively placed silicon nitride and air gaps but utilizing advanced or alternative materials for its fundamental components. The charge storage regions, instead of polysilicon or simple metal layers, could comprise ferroelectric hafnium zirconium oxide (HfZrO), offering distinct polarization states for data storage, or chalcogenide phase-change materials (e.g., GeSbTe) for resistive switching memory applications. The tunnel dielectric, conventionally SiO2, could be replaced with high-κ dielectrics such as aluminum oxide (Al2O3), hafnium oxide (HfO2), or zirconium oxide (ZrO2) to enhance coupling and reduce leakage at scaled dimensions. Similarly, the intermediate dielectric (IPD) could incorporate multi-layer high-κ stacks like Al2O3/HfO2/Al2O3 or advanced perovskite oxides to improve control gate coupling and blocking characteristics. The word lines, while described as tungsten, could be formed from other low-resistivity metals or alloys suitable for advanced interconnects, such as copper (Cu) with a tantalum nitride (TaN) barrier, cobalt (Co) for improved electromigration resistance, or even graphene-based conductors for ultra-low resistance at nanoscale. The foundational silicon oxide (SiO2) sidewall layer could be replaced or augmented with other stable, electrically insulating oxides like plasma-enhanced atomic layer deposited (PEALD) Al2O3 or high-density plasma (HDP) deposited TEOS, particularly in regions where mechanical stability or etch selectivity needs optimization. The silicon nitride (SiN) protection layer could be substituted with aluminum nitride (AlN) for superior thermal stability or silicon oxynitride (SiON) where a tunable dielectric constant and stress are beneficial, provided the charge trapping characteristics of these alternatives are managed or exploited for specific applications (e.g., a deliberate charge trap in a different region).

classDiagram
    class MemoryCell {
        +ChargeStorageRegion (HfZrO / GeSbTe)
        +ControlGate (Polysilicon / TiN)
        +TunnelDielectric (Al2O3 / HfO2)
        +IntermediateDielectric (Al2O3/HfO2/Al2O3)
    }
    class WordLine {
        +Conductor (Cu/TaN / Co / Graphene)
    }
    class DielectricLayers {
        +SidewallOxide (PEALD Al2O3 / HDP TEOS)
        +SelectiveNitride (AlN / SiON)
        +AirGap
    }
    MemoryCell "1" -- "1" DielectricLayers : includes
    WordLine "1" -- "1" DielectricLayers : includes
    MemoryCell -- WordLine : coupled via

Derivative 1.2: Advanced Sacrificial Materials and Etch Chemistries

Enabling Description:
This derivative focuses on the fabrication methodology, specifically expanding the sacrificial material options and associated etch chemistries beyond flowable CVD films of silicon, nitrogen, and hydrogen, or those convertible to silicon oxide. The sacrificial material 1002 could be a polymeric resist material (e.g., photoresist, electron-beam resist, or self-assembled block copolymers) patterned and then thermally or UV-cured to withstand subsequent deposition steps. Alternatively, it could be an inorganic spin-on glass (SOG) or a carbon-based material (e.g., amorphous carbon, diamond-like carbon) deposited by CVD or PVD. The key requirement remains high etch selectivity to both the silicon oxide 532 and the subsequently deposited silicon nitride 534. For example, if a carbon-based sacrificial layer is used, oxygen plasma ashing could selectively remove it without significantly impacting silicon oxide or silicon nitride. If a specialized SOG is used, a dilute hydrofluoric acid (DHF) etch or a reactive ion etch (RIE) with specific fluorocarbon chemistries could be employed. The selective etch-back of the sacrificial material (step 904) could utilize chemical mechanical planarization (CMP) in conjunction with an etch, or a timed wet etch, to achieve precise vertical control of the sacrificial layer's top surface. The choice of sacrificial material and etch chemistry would be optimized based on the aspect ratios of the memory cell stacks, thermal budget compatibility, and desired selectivity to neighboring materials in a highly integrated 3D NAND array.

flowchart TD
    A[Form Memory Cell Stacks with SiO2 Sidewalls] --> B{Select Sacrificial Material};
    B -- Polymer Resist --> C[Deposit by Spin-Coating / Pattern];
    B -- Amorphous Carbon --> D[Deposit by PECVD / PVD];
    B -- Inorganic SOG --> E[Deposit by Spin-Coating];
    C -- Cure --> F[Etch Back Sacrificial Material (e.g., RIE, CMP)];
    D -- Post-Dep Treatment --> F;
    E -- Anneal --> F;
    F -- Etch Selectivity 10:1+ (Sacrificial:SiO2/SiN) --> G[Deposit Selective Nitride (LPCVD/PECVD)];
    G --> H[Etch Back Nitride];
    H --> I[Remove Sacrificial Material (e.g., O2 Plasma, Selective Wet Etch)];
    I --> J[Form Air Gaps / Capping Layer];

Derivative 2.1: Ultra-dense 3D NAND with High Aspect Ratio Air Gaps and Extreme Temperature Operation

Enabling Description:
This derivative extends the disclosed selective oxide/nitride sidewall structure and air gap formation to advanced 3D NAND architectures, specifically those with extremely high aspect ratio (HAR) vertical channels and multiple stacked word line layers. The fabrication process would involve forming thousands of memory cell stacks (e.g., 256, 512, or more layers) with vertical channels, where the disclosed selective SiN protection on word line sidewalls and air gaps are crucial for inter-wordline isolation and mitigating parasitic capacitance. The critical dimensions (CDs) of the word lines could be in the sub-10 nm range, demanding atomic layer deposition (ALD) for the SiO2 and SiN layers to ensure conformality in HAR trenches. The air gaps 844 would be formed with aspect ratios exceeding 50:1 (height:width), utilizing advanced sacrificial removal techniques to prevent collapse, such as supercritical CO2 drying or templated void formation. Operation is extended to extreme temperature ranges, from cryogenic temperatures (e.g., 4K for quantum computing interfaces or specialized data centers) to high temperatures (e.g., 300°C for automotive or industrial applications). At cryogenic temperatures, the low dielectric constant of air gaps provides superior isolation without breakdown issues, while at elevated temperatures, the thermal stability of the SiN-protected word lines and the robustness of the capping layer 854 (e.g., using a multi-layer stack of SiN/SiO2/SiN) become paramount to prevent material degradation or stress-induced cracking.

graph TD
    A[3D NAND Substrate] --> B{Form Vertical Memory Channels};
    B --> C[Stack Word Line/Inter-poly Dielectric Layers];
    C --> D[Etch Word Lines/Channels];
    D --> E[Deposit Conformal SiO2 Sidewall (ALD)];
    E --> F[Deposit HAR Sacrificial Material];
    F --> G[Etch Back Sacrificial Material (below WL, above CSR)];
    G --> H[Deposit Selective SiN (ALD)];
    H --> I[Etch Back SiN];
    I --> J[Remove Sacrificial Material (e.g., Supercritical CO2 Drying)];
    J --> K[Form Capping Layer];
    K --> L[High Aspect Ratio Air Gaps for Isolation];
    L --> M{Operate at Extreme Temperatures (4K - 300C)};

Derivative 2.2: Radiation-Hardened Memory with High-Frequency Operation

Enabling Description:
This derivative adapts the memory architecture for radiation-hardened applications, such as space electronics, medical imaging, or nuclear environments, where conventional floating-gate or charge-trapping memories are susceptible to single-event upsets (SEUs) or total ionizing dose (TID) effects. The selective silicon nitride protection on word lines, combined with robust air gaps, is crucial here. The word line materials (ee.g., W, TiN, TaN) would be chosen for their radiation hardness and low activation cross-section. Crucially, the air gaps 844, being a vacuum or inert gas (e.g., N2, Ar), inherently provide superior radiation shielding compared to solid dielectric materials, reducing charge recombination paths and current leakage induced by ionization events near the charge storage regions 522. The tunnel oxide 520 and intermediate dielectric 524 materials would also be optimized for radiation hardness, potentially using stacked dielectrics like HfO2/Al2O3/SiO2 or highly ordered crystalline oxides. The device is designed for high-frequency operation (e.g., GHz range for high-speed data acquisition), where the minimal parasitic capacitance offered by the air gaps between word lines and charge storage regions becomes critical for maintaining signal integrity and reducing propagation delays. The selective SiN also helps stabilize the word line electrical properties against radiation-induced damage.

stateDiagram
    [*] --> Initialized
    Initialized --> Fabricate_Memory_Cells
    Fabricate_Memory_Cells --> Deposit_SiO2_Sidewalls
    Deposit_SiO2_Sidewalls --> Form_Sacrificial_Layer
    Form_Sacrificial_Layer --> Etch_Sacrificial_Layer : Top below WL, above CSR
    Etch_Sacrificial_Layer --> Deposit_Selective_SiN : On exposed SiO2 (WL)
    Deposit_Selective_SiN --> Etch_SiN_Back
    Etch_SiN_Back --> Remove_Sacrificial : Create Air Gaps (CSR)
    Remove_Sacrificial --> Final_Device
    Final_Device --> Radiation_Exposure : Mitigate SEU/TID
    Final_Device --> High_Frequency_Operation : Maintain Signal Integrity

Derivative 3.1: High-Performance RF Switches/Antennas

Enabling Description:
The core principle of selective dielectric stacking and air gap formation can be directly applied to micro-electromechanical systems (MEMS) or monolithic microwave integrated circuit (MMIC) devices, particularly for high-performance radio-frequency (RF) switches, filters, or reconfigurable antennas. In such applications, the "word lines" translate to RF signal lines or control electrodes, and the "charge storage regions" can be analogous to sensitive regions requiring minimal parasitic capacitance or crosstalk. By forming silicon oxide sidewalls on RF traces, followed by selective silicon nitride application only where robust protection against external fields or mechanical wear is needed (e.g., near control lines), and then creating air gaps between closely spaced RF elements, significant improvements in quality factor (Q), insertion loss, and isolation can be achieved. For example, in a MEMS RF switch, the air gaps would replace solid dielectrics between the movable and fixed electrodes, drastically reducing the "ON" state parasitic capacitance and improving switching speed. The selective SiN layer could protect the control lines during the release process of MEMS structures. The fabrication steps, including sacrificial layer deposition and selective etching, are directly transferable to create self-suspended RF structures with precise air gap dimensions for optimal RF performance.

graph TD
    A[Substrate] --> B{Form RF Metal Traces/Electrodes};
    B --> C[Deposit Conformal SiO2 Sidewall];
    C --> D[Deposit Sacrificial Material (e.g., Polyimide)];
    D --> E[Etch Back Sacrificial Material (Selective Exposure)];
    E --> F[Deposit Selective SiN (e.g., near Control Gates)];
    F --> G[Etch Back SiN];
    G --> H[Remove Sacrificial Material];
    H --> I[Form Air Gaps (between RF traces, switch elements)];
    I --> J[RF Device with Low Parasitics / High Isolation];

Derivative 3.2: Bio-Sensing Arrays with Selective Fluidic Isolation

Enabling Description:
This derivative applies the principles to the field of bio-sensing. Consider an array of micro-electrodes for detecting biomolecules or cellular activity. The "memory cell stacks" become individual sensing electrodes or micro-fluidic channels. The "charge storage region" is analogous to the active sensing surface or a reaction chamber, while the "word lines" are addressing or control lines. Silicon oxide 532 would form the primary passivation layer protecting the delicate bio-interfaces and underlying electronics. Crucially, silicon nitride 534 could be selectively deposited on the oxide sidewalls of the control lines for enhanced chemical resistance or to define hydrophobic/hydrophilic regions, while air gaps 844 are strategically placed adjacent to the active sensing regions. These "air gaps" would instead be micro-fluidic channels or isolation trenches filled with an inert buffer, a specific reagent, or simply air/vacuum. The sacrificial layer method would allow for precise definition of these fluidic or gas-filled isolation regions around sensitive electrochemical or optical sensing elements. This enables compartmentalization, reduces cross-contamination, and allows for parallel processing or multiplexed detection within the bio-sensing array. The selective nitride could also act as a physical or chemical barrier in microfluidic systems.

flowchart LR
    A[Substrate with Sensor Electrodes] --> B[Form SiO2 Passivation on Sidewalls];
    B --> C{Deposit Sacrificial Material (e.g., Photoresist)};
    C -- Etch back --> D[Deposit Selective SiN (e.g., on Control Line oxide)];
    D -- Etch back --> E[Remove Sacrificial Material];
    E --> F{Create Fluidic/Gas Isolation Channels (Air Gaps)};
    F -- Fill with Buffer/Reagent/Gas --> G[Bio-Sensing Array with Isolated Sensing Regions];

Derivative 3.3: High-Voltage Power Semiconductor Devices

Enabling Description:
The selective oxide/nitride sidewall and air gap technology can be adapted for high-voltage power semiconductor devices, such as power MOSFETs, IGBTs, or rectifiers, where breakdown voltage and power dissipation are critical concerns. In these devices, the "word lines" can be analogous to field plates, gate electrodes, or source/drain interconnects operating at high potentials, and the "charge storage regions" are sensitive areas within the device's drift region or near junction terminations where electric fields must be managed. The silicon oxide 532 would serve as a primary isolation dielectric. The selective silicon nitride 534 could be formed on the oxide sidewalls of high-voltage interconnects or field plates to provide enhanced surface passivation and electric field termination, preventing premature breakdown at sharp corners or edges. The air gaps 844, acting as void regions, would be strategically placed within the device's isolation trenches or between closely spaced high-voltage components. Given air's high dielectric strength (~3 MV/m), these "air gaps" offer superior breakdown voltage characteristics and reduced parasitic capacitance compared to solid dielectrics like SiO2, enabling more compact device layouts and higher operating voltages while maintaining reliability. The sacrificial material process allows precise control over the formation of these insulating air pockets.

graph LR
    A[Power Device Substrate (HV Junctions)] --> B[Form Gate/Field Plate Structures];
    B --> C[Deposit Conformal SiO2 (Primary Isolation)];
    C --> D[Deposit Sacrificial Material];
    D --> E[Etch Back Sacrificial Material (Expose high-field SiO2)];
    E --> F[Deposit Selective SiN (Field Plate Protection)];
    F --> G[Etch Back SiN];
    G --> H[Remove Sacrificial Material];
    H --> I[Form Air Gaps (HV Isolation Trenches)];
    I --> J[High-Voltage Power Device with Enhanced Breakdown];

Derivative 4.1: AI-Optimized Fabrication of Selective Dielectrics and IoT Monitoring

Enabling Description:
This derivative integrates AI and IoT into the fabrication and operational monitoring of the memory devices. The precise control over the sacrificial material etch-back and subsequent selective nitride deposition (steps 904 and 906) can be optimized using AI algorithms. Machine learning models, trained on vast datasets of process parameters (e.g., gas flow rates, plasma power, etch times, temperature) and resulting device characteristics (e.g., capacitance-voltage curves, breakdown voltages, memory cell current), could predict optimal parameters for achieving the desired sacrificial material profile and selective nitride coverage with minimal variation. IoT sensors (e.g., in-situ optical emission spectroscopy, ellipsometry, mass flow controllers, temperature probes) would continuously monitor the fabrication environment and material properties in real-time. This real-time data would feed into the AI model, allowing for dynamic adjustment of process parameters (e.g., etch time, gas composition, pressure) to compensate for drift, improve yield, and ensure the precise formation of the selective SiN layer and air gaps according to target specifications, especially critical for reducing charge trapping near the charge storage regions. This predictive and adaptive manufacturing approach enhances control and reduces defects.

sequenceDiagram
    participant IoT Sensors
    participant Fabrication Tools
    participant AI Optimizer
    participant Database

    IoT Sensors ->> Fabrication Tools: Real-time Process Data (e.g., Plasma Flux, Temp, Pressure)
    Fabrication Tools ->> AI Optimizer: Forward Data
    AI Optimizer ->> Database: Store Process Data & Device Performance
    Database --> AI Optimizer: Retrieve Historical Data
    AI Optimizer -->> AI Optimizer: Train ML Model (Predictive/Adaptive)
    AI Optimizer ->> Fabrication Tools: Optimized Process Parameters (e.g., Etch Time, Gas Flow)
    Fabrication Tools ->> Fabrication Tools: Adjust Process (Sacrificial Etch, SiN Deposition)
    Fabrication Tools ->> IoT Sensors: Execute New Parameters
    Fabrication Tools ->> Database: Record Execution & Outcome
    Note over AI Optimizer: Continuously optimizes selective dielectric & air gap formation

Derivative 4.2: Blockchain-Secured Supply Chain for Memory Components

Enabling Description:
This derivative applies blockchain technology to ensure the authenticity and quality of critical materials used in the fabrication of the memory device, particularly the specialized dielectric and sacrificial materials. Each batch of raw materials (e.g., SiH4 for silicon oxide, NH3 for silicon nitride, precursor gases for sacrificial films like HCDS or carbon sources) would have its origin, composition, and quality assurance data recorded on an immutable blockchain ledger. Manufacturers and suppliers would timestamp and verify material certificates, purity levels, and handling conditions (e.g., storage temperature, exposure history) at each stage of the supply chain. When these materials are used in the process (e.g., in step 706 for SiO2 formation, step 902 for sacrificial material, or step 906 for SiN deposition), their blockchain-verified identifiers would be linked to the specific wafer and process batch. This creates an auditable trail, mitigating risks of counterfeit materials impacting device performance (e.g., uncontrolled charge trapping from impurities in nitride, or poor etch selectivity due to inconsistent sacrificial material). Smart contracts could automate quality checks and trigger alerts for non-conforming material batches, enhancing overall product reliability and intellectual property protection within the manufacturing ecosystem.

flowchart TD
    A[Raw Material Supplier] -- Record Batch Data --> B(Blockchain Ledger);
    B -- Link QA/Certifications --> B;
    C[Material Transportation] -- Record Handling Conditions --> B;
    D[Memory Fab - Material In-take] -- Verify Blockchain ID --> B;
    E[Memory Fab - Material Usage] -- Link to Wafer/Process Batch --> B;
    F[Process Step: SiO2 Formation] -- Access Material Provenance --> B;
    G[Process Step: Sacrificial Layer] -- Access Material Provenance --> B;
    H[Process Step: SiN Deposition] -- Access Material Provenance --> B;
    B --> I[Immutable Audit Trail];
    I --> J[Enhanced Supply Chain Security & Quality];

Derivative 5.1: Self-Healing Dielectric for Degradation Mitigation

Enabling Description:
This derivative introduces self-healing capabilities into the dielectric layers, specifically addressing potential degradation of the silicon oxide 532 or silicon nitride 534 layers, which could lead to charge trapping or electrical breakdown over time. Microcapsules containing a dielectric precursor (e.g., a siloxane polymer or a low-viscosity oxide precuror) are embedded within or adjacent to the silicon oxide sidewall layer 532, especially near the charge storage regions. Upon detection of localized dielectric breakdown, excessive leakage current, or a change in a monitored threshold voltage (indicating localized charge trapping or damage), these microcapsules rupture, releasing the healing agent. The healing agent then polymerizes or reacts to form a new dielectric material, effectively repairing the localized damage and restoring the insulating properties. This self-healing mechanism could be triggered by electrical stress (e.g., high electric field), thermal stress, or a controlled electrical pulse. For the air gaps 844, if they are compromised (e.g., due to mechanical stress or poor capping layer integrity leading to gas infiltration), a secondary, localized deposition system could be activated to re-form a solid dielectric in the compromised area, or micro-gas reservoirs could replenish the inert gas. This approach extends the operational lifetime and reliability of the non-volatile memory in harsh or long-duration applications.

stateDiagram
    [*] --> Healthy_Dielectric
    Healthy_Dielectric --> Degradation_Detected : Leakage / V_TH Shift / Breakdown
    Degradation_Detected --> Activate_Microcapsules : Electrical / Thermal Trigger
    Activate_Microcapsules --> Release_Healing_Agent
    Release_Healing_Agent --> Repair_Damage : Polymerization / Reaction
    Repair_Damage --> Restored_Dielectric
    Restored_Dielectric --> Healthy_Dielectric : (Monitor)
    Degradation_Detected --> Fail_Safe_Mode : (If Repair Fails)

Derivative 5.2: Low-Power Operation with Tunable Isolation

Enabling Description:
This derivative focuses on optimizing the memory device for low-power operation by dynamically tuning its electrical isolation characteristics. The air gaps 844 are not static voids but are designed to be switchable or adjustable. For instance, the air gaps could be selectively evacuated or backfilled with a gas of higher dielectric constant during different operational modes. In a "sleep" or low-power mode, a micro-vacuum pump system integrated on-chip could further reduce the pressure within the air gaps, maximizing the dielectric constant of vacuum (effectively 1) and minimizing parasitic leakage and capacitance between word lines, leading to significant power savings during idle states or infrequent access. Conversely, for high-performance or high-voltage operations, if mechanical stability is a concern for evacuated gaps, a high-dielectric-strength inert gas could be introduced. The sacrificial material removal (step 910) could be designed to create channels that allow for such gas exchange. Furthermore, the selective silicon nitride 534 could be made of a ferroelectric material where its polarization state could be tuned to adjust the local electric field distribution, effectively 'tuning' the isolation and coupling characteristics between the word line and other components. This tunable isolation allows the memory device to adapt its performance and power consumption based on application requirements, from ultra-low power archival storage to high-speed active memory.

flowchart TD
    A[Memory Device] --> B{Operational Mode Select};
    B -- Low Power / Standby --> C[Evacuate Air Gaps (Micro-Pump)];
    C --> D[Maximize Vacuum Isolation (ε~1)];
    D --> E[Reduced Parasitic Leakage & Capacitance];
    E --> F[Ultra-Low Power State];
    B -- High Performance / Active --> G[Backfill Air Gaps (Inert Gas)];
    G --> H[Optimize Gas Dielectric Strength];
    H --> I[Enhanced High-Voltage/Speed Operation];
    I --> J[Active Power State];
    A -- Control Signal --> K[Tune SiN Polarization (Ferroelectric SiN)];
    K --> L[Adjust Local Electric Field/Coupling];

II. Combination Prior Art Scenarios

1. US9281314 + JEDEC JESD22 (Reliability Test Methods for Packaged Integrated Circuits):

   • Disclosure: The fabrication methods and resulting memory device structures described in US9281314, specifically the use of selective oxide/nitride sidewalls and air gaps for electrical isolation, would be evaluated and qualified according to established JEDEC JESD22 reliability test methods. This includes, but is not limited to, High-Temperature Operating Life (HTOL), Temperature Cycling (TC), Highly Accelerated Stress Test (HAST), and Electrostatic Discharge (ESD) sensitivity testing. The presence and morphology of the air gaps, as well as the integrity of the selective silicon nitride layer, would be continuously monitored during these tests using non-destructive techniques such as acoustic microscopy, X-ray tomography, and electrical characterization. Failure analysis would correlate dielectric breakdown or charge retention issues with defects in the air gaps or the selective nitride passivation. The adaptation of standard test methods to validate the reliability of devices incorporating these specific isolation features makes the reliability assessment and potential design for reliability an obvious step for any skilled artisan in memory manufacturing.

2. US9281314 + Open-Source EDA Tools (e.g., KLayout, Magic VLSI) for Physical Layout and Verification:

   • Disclosure: The design and physical layout of memory arrays incorporating the selective oxide/nitride sidewalls and air gaps, as described in US9281314, can be readily performed using widely available open-source Electronic Design Automation (EDA) tools such as KLayout (for GDSII layout viewing and editing) or Magic VLSI (for layout and design rule checking). A design flow would involve defining custom process layers for the sacrificial material (1002), the silicon oxide sidewall (532), and the selective silicon nitride (534) within the tool's layer stack. Design rules would be established to ensure correct alignment and dimensions for the sacrificial material etch-back (step 904) and subsequent nitride deposition (step 906), leading to the desired air gap (844) formation. Process emulation within these tools, or using supplementary open-source process simulation tools (e.g., Sentaurus Process, although typically proprietary, the concept of simulating the steps is known and can be approximated), would demonstrate the feasibility of achieving the patented structure. The ability to design and verify such features using standard, publicly accessible software tools makes the implementation of these structures a conventional engineering exercise.

3. US9281314 + IEEE 1801 (Unified Power Format - UPF) for Power Domain Isolation:

   • Disclosure: The memory device architecture from US9281314, featuring word line air gaps for enhanced electrical isolation, directly supports advanced power management techniques defined by open industry standards like IEEE 1801 (Unified Power Format - UPF). In a complex System-on-Chip (SoC) incorporating these memory blocks, the air gaps 844 between word lines contribute to the physical isolation required for distinct power domains. During design, UPF would be used to formally describe these power domains, their isolation strategies, and voltage levels. The air gaps enable highly efficient power gating or voltage scaling techniques by minimizing leakage paths between an active memory block and a power-gated adjacent block. The lower parasitic capacitance due to the air gaps facilitates faster power-up and power-down transitions for the word lines, further improving energy efficiency. The explicit modeling of the memory block's isolation (enabled by air gaps) within a UPF framework for power optimization, including considerations for reduced leakage and faster switching, represents a straightforward application of existing industry standards to the disclosed structure, making its power-saving benefits apparent to SoC designers.