US 8063674

I'll search for authoritative information on US patent 8063674, including any 2026 CAFC activity.

Let me verify the current post-IPR status and check specifically for any 2026 CAFC docket activity.

US Patent 8,063,674 — Analyst Summary

Sourcing note: The following is drawn from the full patent text you supplied (Google Patents, https://patents.google.com/patent/[US8063674](/patent/US8063674)/en) plus targeted web searches. I did not find any live USPTO or CAFC docket record indicating 2026 appellate activity specific to this patent (see "Litigation status" below). Where I lack authoritative confirmation, I flag it explicitly.

1. Bibliographic data

The patent text also notes a 165-day term adjustment under 35 U.S.C. § 154(b), consistent with the July 19, 2029 adjusted expiration shown on the Google Patents record.

2. Abstract (verbatim)

"A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector."

3. Plain-language overview of the independent claims

Background context (for readability): The patent addresses multi-supply ICs in which a lower-voltage "core" and a higher-voltage I/O network communicate through level shifters. A power-on/off-control (POC) signal tells the I/O side when the core is collapsed, so stray signals aren't transmitted. The prior-art detector (Fig. 1, labeled "PRIOR ART") can leak current when the I/O supply is up and the core is off, and shrinking transistors to cut leakage slows detection. The invention adds feedback that dynamically changes the detector's current capacity — high capacity (fast detection) when the core is off, low capacity (low leakage) when the core is on.

Claim 1 — the apparatus claim ("multiple supply voltage device")
A device with two main parts:

• a core network running at a first supply voltage; and
• a control network that outputs a control signal and contains:
  • an up/down detector that senses the core network's power state;
  • processing circuitry that turns that state into the control signal;
  • one or more feedback circuits that feed back signals to adjust the detector's current capacity;
  • at least one first transistor coupled to a second supply voltage that turns on when the first supply voltage is down and off when it is up;
  • at least one second transistor in series with the first and coupled to the first supply voltage, turning on when the first supply voltage is up and off when it is down; and
  • at least one third transistor coupled in series between the first and second transistors.

(Note a terminology quirk: Claim 1 calls the core network voltage the "first supply voltage," while the Abstract/Summary call the I/O voltage the "first supply voltage." The claim language is internally consistent with itself but inverted relative to the Abstract.)

Claim 8 — the method claim
A method of reducing power consumption in a POC network:

• detect a power-on of a second supply voltage while a first supply voltage is already on;
• decrease the power on/off detector's current capacity in response;
• detect a power-down of the second supply voltage while the first is on;
• increase the detector's current capacity in response;
• receive a logic-high signal at the control gates of first, second, and third series-connected transistors (first transistor switches off, second transistor switches on); and
• transmit a detection signal from the second transistor to a signal processor.

Claim 17 — the system claim (means-plus-function)
A system comprising means for: detecting a power-on of a second supply voltage while a first is on; decreasing detector current capacity in response; detecting a power-down of the second supply voltage while the first is on; increasing detector current capacity in response; receiving the logic-high signal at the gates of the first/second/third series transistors (first off, second on); and transmitting a detection signal from the second transistor to a signal processor.

Dependent-claim families: Claims 2–7 depend from claim 1 (feedback transistor variants, I/O network, semiconductor die/device incorporation); claims 9–16 depend from claim 8 (feedback-signal and logic-low detection specifics); claims 18–22 depend from claim 17 (feedback means, die/device incorporation).

Drafting observation: Granted claims 21 and 22 are written as "The multiple supply voltage device of claim 17/21," even though claim 17 is a system claim and claim 21 likewise refers to a "device." This is an apparent antecedent-basis/typographical inconsistency in the granted text. Separately, the pre-grant publication (US 2010/0194200 A1) carried 27 claims with different numbering (e.g., its claim 2 recited the detector transistor structure, and its independent method claim was claim 10) — so the granted claim set differs materially in numbering from the published application; rely on the granted claims.

4. Post-grant / litigation status (searched)

The Google Patents record and search results show substantial post-grant activity, all of which resolved in Qualcomm's favor at the Federal Circuit:

• IPR2018-01315 and IPR2018-01316 — petitions filed by [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) on June 29, 2018. PTAB issued a consolidated Final Written Decision on January 3, 2020 holding challenged claims unpatentable over Applicant Admitted Prior Art ("AAPA," the Figure 1 "PRIOR ART" circuit) in view of Majcherczak (and Matthews).
• Qualcomm I — CAFC Nos. 20-1558 / 20-1559: On February 1, 2022, the Federal Circuit vacated the PTAB decision (Qualcomm Inc. v. Apple Inc., 24 F.4th 1367), holding AAPA is not "prior art consisting of patents or printed publications" under 35 U.S.C. § 311(b), and remanded to determine whether AAPA improperly formed the basis of the challenge. (Opinion PDF: finnegan.com link returned in search.)
• PTAB on remand again found the claims unpatentable under Ground 2, applying Director Vidal's June 2022 "in combination" guidance.
• Qualcomm II — CAFC Nos. 23-1208 / 23-1209: On April 23, 2025, the Federal Circuit reversed the PTAB's remand decision (Qualcomm Inc. v. Apple Inc., 134 F.4th 1355), holding that Apple impermissibly designated AAPA as part of the "basis" of its grounds. Cases 23-1208/23-1209 are recorded as closed April 23, 2025 with disposition "Reversed."
• ITC — Investigation 337-TA-1093 ("Mobile Electronic Devices and Radio Frequency and Processing Components"); listed as resolved in Qualcomm's CAFC brief.
• District court — Qualcomm Incorporated v. Apple Inc., No. 3:17-cv-02398 (S.D. Cal.); listed as resolved.
• IPR certificate — Google Patents' legal-events table shows an "INTER PARTES REVIEW CERTIFICATE" (kind code K1) with effective date September 25, 2025, citing Trial Nos. IPR2018-01315 and IPR2018-01316. Uncertainty flag: I could not independently confirm the content of that certificate (e.g., whether it confirms the claims as patentable or effects any cancellation). Based on the April 23, 2025 CAFC reversal, the certificate would be expected to reflect the claims surviving, but I have not verified this.

2026 CAFC dockets — none found for this patent. My searches surfaced 2026 Federal Circuit activity involving Qualcomm on other patents (e.g., Federal Express Corp. v. Qualcomm Inc., Nos. 24-1235/24-1237, decided April 29, 2026, concerning U.S. Patent 9,182,231; and ParkerVision, Inc. v. Qualcomm, argued June 1, 2026). I found no 2026 CAFC docket specifically docketing U.S. Patent 8,063,674. I cannot rule out a very recent or sealed filing that is not yet in the sources searched.

5. Uncertainty / caveats

1. 2026 CAFC docket: No 2026 appellate docket for the '674 patent was located. This is a negative finding based on the searches run, not proof of absence.
2. IPR certificate content: Reported as issued Sept. 25, 2025, but I did not verify its substantive effect on the claims.
3. Claim numbering discrepancy: The granted 22-claim set differs from the 27-claim pre-grant publication; treat the granted claims as authoritative.
4. Internal terminology inconsistency between the Abstract ("first supply voltage" = I/O) and claim 1 ("first supply voltage" = core) exists in the patent as published.
5. I did not auto-correct any identifier; all numbers (8,063,674 / 12,365,559 / IPR2018-01315 / -01316 / 23-1208 / 23-1209 / 20-1558 / 20-1559 / 337-TA-1093 / 3:17-cv-02398) are reproduced as they appear in the sources.

Primary URLs cited:

• https://patents.google.com/patent/US8063674/en
• https://patents.justia.com/patent/8063674
• https://www.finnegan.com/a/web/39aXXPsCZcBQJDHjEHUYd1/20-1558opinion2-1-2022_1901450.pdf
• https://www.akingump.com/print/v2/content/[1116776](/patent/1116776)/... (AAPA / § 311(b) analysis)
• https://portal.unifiedpatents.com/ptab/case/IPR2018-01315 and .../IPR2018-01316

I'll research litigation involving US patent 8063674. Let me start with searches on the patent litigation portals.

Let me dig into the specific cases identified — the district court case, ITC investigation, and IPRs/appeals.

Known Litigation & Contested Proceedings — U.S. Patent No. 8,063,674

Patent: US 8,063,674 B2 ("Multiple supply-voltage power-up/down detectors"), assigned to Qualcomm Incorporated (inventors Chang Ki Kwon and Vivek Mohan; filed Feb. 4, 2009; granted Nov. 22, 2011).

Every identified proceeding involving the '674 patent pitted Qualcomm (patent owner/plaintiff) against [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) (accused infringer/petitioner). The patent was one of several asserted in the global Qualcomm–Apple dispute (2017–2019) and was later the subject of two Apple IPRs that produced two Federal Circuit appeals. Set out below are the district court case, the ITC investigation, the IPRs, and the appeals.

1. District Court — Qualcomm Inc. v. Apple Inc. (S.D. Cal.)

Qualcomm's complaint asserted the '674 patent together with U.S. Patent Nos. 9,154,356; 9,473,336; 7,693,002; and 9,552,633, and sought an injunction plus damages. Docket records keyed to "patent:8063674" confirm the '674 patent as one of the patents-in-suit in this case (claim chart/complaint at Dkt. 1). Source: Docket Alarm docket 3:17-cv-02398 and the complaint PDF.

Note: This case is distinct from the companion S.D. Cal. case 3:17-cv-01375 (which went to a March 2019 jury verdict on the '936, '490, and '949 patents). The '934/'674 case was resolved by the settlement rather than tried.

2. ITC Section 337 Investigation — Certain Mobile Electronic Devices and RF and Processing Components Thereof (II)

Sources: ITC "Analysis and Findings with Respect to the Public Interest, and Recommendation on Remedy and Bond," Inv. No. 337-TA-1093 (Apr. 16, 2019); Wolf Greenfield summary of the 1093 Initial Determination; IPWatchdog coverage.

3. PTAB Inter Partes Reviews — Apple Inc. v. Qualcomm Inc.

Panel included APJ Trevor M. Jeffer… (Unified Patents PTAB case list). Source: Unified Patents PTAB portal; Board FWD (Banner & Witcoff copy at bannerwitcoff.com/wp-content/uploads/2022/11/IPR2018-01315.pdf).

4. Federal Circuit Appeal (First Round) — Qualcomm Inc. v. Apple Inc., Nos. 2020-1558 & 2020-1559

5. Federal Circuit Appeal (Second Round) — Qualcomm Inc. v. Apple Inc., Nos. 2023-1208 & 2023-1209

Sources: Fed. Cir. combined opinion (23-1208/23-1209) (slip op. at case-law.vlex.com); Patsnap case summary: 23-1209, Fed. Cir., closed 23 Apr 2025, "REVERSED".

Notes, Caveats, and Limitations

• Google Patents' own litigation record for the '674 family lists exactly these U.S. proceedings: ITC Inv. No. 337-TA-1093, district court case 3:17-cv-02398, the two CAFC appeals (20-1558/20-1559 and 23-1208/23-1209), and the two IPRs. No other U.S. cases were identified. (Google Patents – US8063674B2.)
• No NPE/assertion campaign, damages verdict, or injunction specific to the '674 patent was found; the patent's disputes were all part of the Qualcomm–Apple conflict and ended without a trial verdict on the '674 patent.
• German/foreign activity: Some press accounts of the broader Qualcomm–Apple dispute reference a December 2018 Munich Regional Court injunction against certain iPhones tied to Qualcomm power-management technology and sometimes link it to the '674 patent. I could not independently confirm that the '674 patent (or its EP family member, EP 2 394 364) was the patent enforced in that German action — the Google Patents litigation data for this family does not list it. Treat any such German linkage as unverified.
• Not litigation, but related: The Federal Circuit's 2025 decision (Nos. 23-1208/23-1209) resolved an important § 311(b)/AAPA question; this is a validity/procedural ruling, not a district-court infringement outcome.
• Status of the patent: Active; Google Patents shows adjusted expiration of July 19, 2029, and an IPR certificate issued September 25, 2025.

If you want, I can pull the full docket sheets (PACER/CourtListener) for 3:17-cv-02398 and the complete ITC 337-TA-1093 record to confirm the parties' stipulation of dismissal and the settlement-termination order.

I'll reconcile the structured ODP block against the patent's own embedded litigation metadata (which lists two IPRs), then fill in claim-level outcomes from public sources.

Now let me pin down the second appeal (23-1208/-1209), the remand FWD, and the resulting IPR certificate.

PTAB proceedings overview

Reconciliation note up front: the ODP-derived block in this prompt is empty ("no AIA trial proceedings"), but that is inconsistent with the patent's own Google Patents legal-events metadata and the public record. The patent's "Family has litigation" fields list PTAB case IPR2018-01315 filed (Final Written Decision) and PTAB case IPR2018-01316 filed (Final Written Decision), both against petitioner [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), plus CAFC dockets 20-1558/20-1559 and 23-1208/23-1209, an ITC investigation, and a K1 IPR certificate issued 2025-09-25. The likely explanation is that ODP's trial endpoint is reflecting only open proceedings — these two IPRs are closed and certified. I treat the two IPRs below as confirmed; I do not invent any additional proceeding numbers.

Bottom line: two IPRs were filed and consolidated; all challenged claims (1, 2, 5–9, 12, 13, and 16–22) were held unpatentable twice by the PTAB, and both times the Federal Circuit reversed Qualcomm's loss on a statutory (§ 311(b) "AAPA" / "basis") ground — not on the merits of the prior art. Qualcomm reinstated the patent in April 2025. The patent is therefore un-narrowed: no claims are canceled, and every challenged claim survives. A defendant today faces a patent whose claims have already survived two full IPR cycles, but whose survival rests on a technical rule about the basis of an IPR ground, leaving the obviousness merits of the Majcherczak-based combination formally unresolved.

IPR2018-01315 — Apple Inc. v. Qualcomm Incorporated (consolidated with IPR2018-01316)

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2018-06-29
• Status: Closed — Final Written Decision issued; reversed on appeal; IPR certificate (K1) issued 2025-09-25. (Patent listed as Active, adjusted expiration 2029-07-19.)
• Judge panel: Trevor M. Jefferson, Daniel J. Galligan, Scott B. Howard (Administrative Patent Judges); opinion authored by Howard.
• Claims challenged / instituted: IPR2018-01315 challenged claims 1, 2, and 5–7; IPR2018-01316 challenged claims 8, 9, 12, 13, and 16–22. Both were instituted on all grounds on 2019-01-18. Claims 3, 4, 10, 11, 14, and 15 were never challenged in either petition.
• Petition grounds (identical in both petitions):
  • Ground 1 — § 103 over Steinacker (U.S. Pat. No. 7,279,943), Doyle (U.S. Pat. No. 4,717,836), and Park ("Sleepy Stack Leakage Reduction," IEEE TVLSI, Nov. 2006).
  • Ground 2 — § 103 over Applicant Admitted Prior Art (AAPA) — Figure 1 and its description in the '674 patent itself — in view of Majcherczak (U.S. Pub. No. 2002/0163364); for claims 7, 16, and 22, further in view of Matthews (U.S. Pat. No. 6,646,844).
• Institution decision: Instituted 2019-01-18, all grounds, though the Board flagged "concerns regarding whether Petitioner's arguments and evidence are based on impermissible hindsight," particularly the Steinacker + Doyle motivation to combine.
• Joint oral hearing: 2019-10-11.
• Final Written Decision (consolidated): 2020-01-03 (Paper 26). The Board found all challenged claims unpatentable under § 103 on Ground 2:
  • Claims 1, 2, 5, 6, 8, 9, 12, 13, and 17–21 obvious over AAPA + Majcherczak;
  • Claims 7, 16, and 22 obvious over AAPA + Majcherczak + Matthews.
  • Order: "claims 1, 2, 5–9, 12, 13, and 16–22 of the '674 patent are held unpatentable."
  • Ground 1 failed on the merits: the Board held Apple "had not proven" the Steinacker/Doyle/Park combination rendered the claims unpatentable, for lack of a persuasive motivation to combine Doyle (1986) with Steinacker (2005) — the panel expressly worried this was hindsight reconstruction.
• Settlement / termination: None. No adverse judgment, no motion to amend, no settlement — this went to a merits FWD.
• Appeal #1: Qualcomm appealed 2020-03-04. Qualcomm Inc. v. Apple Inc., Nos. 2020-1558, -1559 (Fed. Cir. Feb. 1, 2022), 24 F.4th 1367 (precedential) — panel Taranto, Bryson, Chen (Chen authored). Held: the Board "incorrectly interpreted § 311(b)'s 'prior art consisting of patents or printed publications' to encompass AAPA contained in the challenged patent." Vacated and remanded for the Board to decide whether Apple's challenge was nonetheless "on the basis of prior art consisting of patents or printed publications." The court affirmed the Board's rejection of Ground 1 ("no error in the Board's finding that Apple made an insufficient showing of a motivation to combine Doyle with Steinacker"). Mandate 2022-06-24. Opinion: https://www.courtlistener.com/opinion/[6248915](/patent/6248915)/qualcomm-incorporated-v-apple-inc/
• Remand: Board Order on Conduct of Proceedings on Remand 2022-07-25 (Paper 28); two rounds of simultaneous 10-page/5-page briefing. Applying the USPTO's June 2022 Updated Guidance on the Treatment of Statements of the Applicant in the Challenged Patent in IPRs Under § 311(b), the Board held that reliance on AAPA "in combination" with Majcherczak did not make AAPA "the basis" of the ground. Final Written Decision on Remand, 2022-11-10 (Paper 40): claims 1, 2, 5–9, 12, 13, and 16–22 unpatentable again (claims 1, 2, 5, 6, 8, 9, 12, 13, 17–21 over AAPA + Majcherczak; claims 7, 16, 22 over AAPA + Majcherczak + Matthews).
• Appeal #2: Qualcomm appealed again — Qualcomm Inc. v. Apple Inc., Nos. 2023-1208, -1209 (Fed. Cir. Apr. 23, 2025) (precedential, per Jones Day/Sheppard; also docketed as 23-1209 on the Google Patents record). Reversed. Holdings: (1) under § 314(d), a petitioner's compliance with § 311(b) is reviewable on appeal; (2) the Board misinterpreted § 311(b)'s "basis" requirement; (3) because Apple's own petition stated the "Basis" of Ground 2 was "AAPA in view of Majcherczak," Apple was held to that phrasing as "master of its own petition," and AAPA impermissibly formed the basis of the ground. The court expressly rejected the Director's contrary Updated Guidance. The reversal reinstated the patent. Opinion: https://www.courtlistener.com/opinion/[10382636](/patent/10382636)/qualcomm-incorporated-v-apple-inc/
• Certificate: An inter partes review certificate (K1) issued 2025-09-25 for IPR2018-01315/-01316. Because the unpatentability determinations were reversed, the certificate should confirm the claims rather than cancel them — but I could not retrieve the certificate text to verify claim-by-claim, so treat the confirmatory effect as inferred from the reversal, not independently confirmed.
• Defensive value: This is the single most important fact for any defendant — Apple lost, and claim 1 is not dead. An assertion letter citing claim 1, 8, or 17 (the independent claims) cites claims that have now survived a full IPR + two CAFC appeals. The win, however, was procedural: Apple's art-based case failed only because AAPA can't be the basis of a ground. A future petitioner who re-packages the same substance using Majcherczak as an actual prior-art publication (and, if needed, a real prior-art patent/publication in place of the '674 Background's Fig. 1 admission) is not obviously barred by this ruling. Conversely, Ground 1 (Steinacker/Doyle/Park) is a dead end — rejected by the Board and affirmed on appeal.

IPR2018-01316 — Apple Inc. v. Qualcomm Incorporated (consolidated with IPR2018-01315)

• Type: Inter Partes Review
• Filed: 2018-06-29
• Status: Closed — Final Written Decision issued; reversed on appeal; certificate (K1) issued 2025-09-25.
• Judge panel: Same panel — Jefferson, Galligan, Howard.
• Claims challenged / instituted: claims 8, 9, 12, 13, and 16–22; instituted on all grounds 2019-01-18.
• Petition grounds: Identical two grounds to -01315 (Ground 1: Steinacker/Doyle/Park; Ground 2: AAPA + Majcherczak, plus Matthews for claims 7, 16, 22).
• Institution decision: Instituted 2019-01-18, all grounds.
• Final Written Decision: Consolidated with -01315; 2020-01-03. All challenged claims (8, 9, 12, 13, 16–22) held unpatentable; then again unpatentable in the FWD on Remand, 2022-11-10.
• Settlement / termination: None.
• Appeal: Same two appeals: 2020-1559 (vacate/remand, 2022-02-01) and 2023-1209 (reverse, 2025-04-23).
• Defensive value: Same as above — claims 8 (independent method claim), 16–22 (system claims) survive, so a method- or system-claim theory is not vulnerable to a § 315(e)(2) "already invalidated" attack. Note the ITC already found in Qualcomm's favor on this family: ALJ McNamara's 2019-03-26 Final Initial Determination in Inv. No. 337-TA-1093 found Apple infringed claim 1 and that claims 1 and 8 were valid, recommending a limited exclusion order.

Strategic summary

Claim-by-claim status of US 8,063,674 (as it stands today):

There are no canceled claims. Any statement that "claims 1–5 were canceled" would be false; the entire claim set is enforceable, and the patent is listed Active with adjusted expiration 2029-07-19.

Estoppel landscape. Apple is the only petitioner, and it is the real party in interest (it identified itself as such in both petitions). Under § 315(e)(2), Apple (and its privies/RPIs) is estopped in district court and the ITC from asserting invalidity on any ground it raised or reasonably could have raised in these IPRs — i.e., Steinacker/Doyle/Park and AAPA/Majcherczak/Matthews. Two caveats: (1) estoppel ordinarily attaches to a final written decision; where the FWD was reversed on appeal, the estoppel's scope is contestable, though Apple has little practical incentive to re-litigate. (2) Estoppel runs only to Apple and privies — a new, unrelated defendant is not estopped, so the full universe of prior art (including Majcherczak used as a true § 311(b) reference, and any art Apple did not raise) remains available. What a new petitioner cannot easily do is rely on AAPA — under the 2025 decision, admissions in the challenged patent can support general-knowledge/skill findings and a motivation to combine, but "may not form the basis of a ground." Ground 1's rejection (Steinacker + Doyle) was affirmed on the merits and is effectively foreclosed as a theory.

Pattern signals. Apple filed two IPRs on the same day on the same patent, on identical grounds, splitting the claims — a classic allocation strategy after SAS. There is no defensive aggregator in the chain: Unified Patents appears only as the data source for the Google Patents litigation overlay, not as petitioner. The patent owner (Qualcomm, represented by Jones Day) appealed twice, won twice, and the 2025 decision is precedential and expressly rejects the USPTO Director's guidance — a significant, portable win for patent owners on § 311(b). The broader Qualcomm/Apple campaign (ITC 337-TA-1093; S.D. Cal. 3:17-cv-02398) has been resolved.

Recommended next steps

• If you are a defendant: the patent is not narrowed. Do not build a defense on "these claims were canceled" — they were reinstated. The FWD that found all challenged claims unpatentable is Qualcomm Inc. v. Apple Inc., Nos. 2023-1208, -1209 (Fed. Cir. Apr. 23, 2025) (reversal), https://www.courtlistener.com/opinion/10382636/qualcomm-incorporated-v-apple-inc/, and the earlier vacatur is 24 F.4th 1367 (Fed. Cir. 2022), https://www.courtlistener.com/opinion/6248915/qualcomm-incorporated-v-apple-inc/. Both PTAB FWDs (2020-01-03 and 2022-11-10) are accessible via PTAB E2E, https://ptacts.uspto.gov/ptabweb/ (Case IPR2018-01315 / IPR2018-01316); a public copy of the consolidated 2020 FWD is at http://bannerwitcoff.com/wp-content/uploads/2022/11/IPR2018-01315.pdf.
• If you want to file a new IPR: the realistic path is a Ground-2-style obviousness case re-based on § 311(b)-qualified art — using Majcherczak (U.S. Pub. No. 2002/0163364) as a publication, and substituting for the '674 Background's Fig. 1 admission a genuine prior-art patent or printed publication showing the same POC detector. Watch the § 315(b) one-year bar (from service of any infringement complaint), and confirm the certificate's claim-by-claim content before relying on any characterization of the post-appeal claim set.
• If you are evaluating the patent for licensing/valuation: the claims have survived the strongest challenge available to the most motivated challenger, which materially hardens them — but the survival reason (the basis rule) means the merits were never finally adjudicated either way. There are no pending PTAB proceedings; the K1 certificate of 2025-09-25 closes the record.
• Confidence caveats: I could not independently verify (a) the identity of the Federal Circuit panel in the 2025 appeal, (b) the text of the 2025-09-25 IPR certificate, or (c) the exact docket correspondence between 23-1208/23-1209 and the individual IPRs. The proceedings list above rests on the patent's own metadata plus public FWD/CAFC sources and contradicts the empty ODP block — verify against PTAB E2E before filing anything that turns on certification status.

I'll research the assignment record for US 8063674, checking USPTO assignment sources and cross-referencing litigation/ownership data.

Let me try to locate the original assignment cover sheet to identify the correspondent of record, and verify there are no post-issuance assignments.

Let me attempt to locate the recorded assignment cover sheet for reel 022207/0060 and confirm there are no later transfers.

Assignment & Ownership Analysis — US 8,063,674 B2

Scope note: The USPTO Assignment Center interface (assignmentcenter.uspto.gov / assignment.uspto.gov) is not directly queryable through the tools available to me, so I reconstructed the chain from (a) the legal-events table embedded in the Google Patents record you supplied, which reproduces the recorded-assignment metadata (conveyance, owner name, reel/frame, execution/effective date), and (b) cross-checks against litigation records. I could not retrieve the actual assignment cover-sheet image, so the correspondent of record for the one recorded assignment could not be confirmed and is flagged as a gap rather than guessed.

Inventors

Unusual patterns: None found. Both inventors assigned to Qualcomm by an instrument executed 2008-11-05 (before the 2009-02-04 filing), i.e., a standard pre-filing employment assignment — not a departure-driven transfer. I found no evidence that either inventor left Qualcomm within 12 months of filing, and I did not locate any secondary-market or fire-sale behavior tied to them. Their patent output is consistent with long-tenure Qualcomm engineers.

Original assignee

Qualcomm Incorporated — a Delaware corporation, 5775 Morehouse Drive, San Diego, CA 92121-1714. It is the entity named on the issued patent (Google Patents: "Original Assignee: Qualcomm Inc"; Patsnap: "Prosecution counsel: QUALCOMM INCORPORATED").

• Primary line of business: Fabless semiconductor design and wireless-technology licensing (Snapdragon SoCs, modem/RF chipsets, and the Qualcomm Technology Licensing arm).
• Did they ship a product embodying the claims? Yes. This patent covers power-on-control (POC) circuitry for multi-supply ICs, and Qualcomm asserted the patent against Apple's A10, A11 and A12 application processors (iPhones 7 through the X-generation), i.e., the claimed circuitry was identified in shipping chips. Qualcomm's own product line (Snapdragon application processors) uses the same dual-supply I/O-core architecture.
• Current status: Operating. Publicly traded (NASDAQ: QCOM); no bankruptcy, acquisition, or dissolution. It also remains the current assignee per Google Patents and Patsnap ("assigned to QUALCOMM INCORPORATED, currently active").

Assignment timeline

The record contains exactly one recorded assignment. There are no post-issuance assignments (no LLC transfers, no security agreements, no mergers, no name changes, no licenses recorded). Post-grant activity in the legal-events table consists only of a Certificate of Correction (2017-12-05) and IPR proceedings (2018+) — not property transfers.

• 2008-11-05 (executed) / recorded 2009-02-04 — Reel 022207 / 0060
  • Conveyance: Assignment (of inventors' interest)
  • Assignor: Chang Ki Kwon and Vivek Mohan (joint inventors)
  • Assignee: Qualcomm Incorporated, San Diego, California
  • Correspondent: Not retrieved. The assignment cover sheet (reel 022207/0060) was not accessible through the sources available; Google Patents' events table reproduces the reel/frame and parties but not the correspondent block. This is the single metadata gap in the chain and should be confirmed directly at assignmentcenter.uspto.gov. Because this is the only link in the chain, no recurrence pattern can be assessed.
  • Context: Ordinary pre-filing employment/inventor assignment — the founders' standard conveyance of rights to their employer before the February 2009 application was filed. Not an acquisition, fire-sale, or reorg.

(Note: the legal-events table lists "Effective date: 20081105" for this record, matching the instrument's execution date; the recording occurred on the 2009-02-04 filing date.)

Timeline diagram

timeline
    title Ownership of US 8063674
    2008 : Inventors execute assignment to Qualcomm
    2009 : Assignment recorded reel 022207 frame 0060
         : Application filed Feb 4 2009
    2011 : Patent issued Nov 22
    2017 : Qualcomm sues Apple in S D Cal
    2018 : Apple files IPRs 2018-01315 and 01316
    2025 : CAFC reversal claims survive

NPE / troll-pattern signals

Litigation corroboration of ownership: Qualcomm v. Apple proceeded with Qualcomm as plaintiff/patent owner — ITC Inv. 337-TA-1093 (ALJ McNamara initial determination found the '674 patent valid and infringed by Apple, with a recommended limited exclusion order), S.D. Cal. 3:17-cv-02398, and the Apple-initiated IPRs IPR2018-01315 / -01316. On appeal (9th Cir. no — Fed. Cir. Nos. 23-1208 / 23-1209, closed 2025-04-23, "REVERSED"), the Federal Circuit reversed the PTAB's remand decision, leaving Qualcomm as the owner of surviving claims. The IPR certificate (kind code K1, effective 2025-09-25) in the legal-events table is consistent with that posture.

Verdict

Operating-company assertion.

The record shows a single, ordinary pre-filing inventor→employer assignment to Qualcomm Incorporated (executed 2008-11-05, recorded 2009-02-04, reel 022207/0060) and no subsequent transfers of any kind. Qualcomm is a large, publicly traded operating company that both builds products using the claimed dual-supply POC circuitry and enforced this patent in its own name against a direct competitor (Apple's A10–A12 processors), through the ITC, district court, and two rounds of Federal Circuit appeals. Every NPE hallmark (shell LLC, known asserter, cascading transfers, pre-suit transfer, fire-sale, privateering, defensive-aggregator termination) is absent. This is a classic operating-company assertion, not an NPE chain.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 8063674) — and confirm the correspondent of record for reel 022207/0060, the one field I could not retrieve.

Caveats

1. Correspondent not confirmed for reel 022207/0060 — cover sheet not retrievable with available tools; treat "repeat correspondent" as not assessable, not as "not present."
2. IPR certificate content (K1, eff. 2025-09-25) inferred as claims-surviving based on the April 2025 CAFC reversal; not independently verified.
3. All identifiers reproduced as recorded (8063674 / 12,365,559 / 022207/0060 / IPR2018-01315 / -01316 / 23-1208 / 23-1209 / 337-TA-1093 / 3:17-cv-02398); none auto-corrected.

I'll research US 8,063,674 directly and each of its cited references, prioritizing authoritative sources.

Now let me research the remaining key cited references.

Prior-Art Analysis — US 8,063,674 B2

A note on method and tool limits. I searched for the record of U.S. Patent No. 8,063,674 (application 12/365,559, filed Feb. 4, 2009, granted Nov. 22, 2011, Qualcomm Incorporated) and retrieved its front-page citation data and the PTAB record. I was able to open and read the full text of three of the cited references (US 2007/0030039 A1; US 2008/0218223 A1; US 6,646,844 B1). Four of my searches (for US 2006/0103437 A1, US 2009/0027087 A1, WO 2007/091211 A2, US 2002/0163364 A1) hit the tool step limit before returning results, so for those I rely on the patent's own front-page citation table (titles, numbers, dates) plus general knowledge, and I flag that accordingly. I did not auto-correct any identifier.

Because the numeric citation list is reproduced from the granted patent's front page ("Patent Citations (17)"), it is authoritative for which references were cited and their listed dates, even where I could not independently open the reference.

1. The patent under analysis

Anticipation standard applied. Under 35 U.S.C. § 102 a single reference must disclose every limitation of the claim, arranged as claimed. The feature that distinguishes claim 1 is the combination of (a) an up/down detector, (b) processing circuitry, and (c) one or more feedback circuits providing feedback signals to adjust the detector's current capacity, plus (d) the first/second/third series-transistor arrangement of claim 1's closing paragraphs. On the face of the 17 cited references, none discloses the complete combination, which is consistent with the fact that the examiner and the PTAB litigated this patent under § 103 (obviousness), not § 102. My mapping below therefore states, for each reference, the claims it is most relevant to and whether true § 102 anticipation is made out — and in most cases the honest answer is "no, this is § 103 material."

2. The 17 cited patent references

Tier 1 — Closest to the claimed subject matter

1. US 2007/0030039 A1 — "Regenerative power-on control circuit" (granted as US 7,295,052 B2)

• Citation: US 2007/0030039 A1; filed 2005-08-03; published 2007-02-08; Taiwan Semiconductor Manufacturing Co., Ltd. (Verified: I read the full description and claims.)
• Description: A power-on control circuit for sequenced multi-supply ICs. A coupling device (PMOS/NMOS capacitors), a first inverter driven by the core supply, and a level shifter generate a power-on control signal when the I/O supply is up and the core supply is off, and disable that signal when the core powers up. Critically, it expressly addresses the same problem as the '674 patent: the coupling device "eliminates a leakage current path from the first voltage supply to the complementary voltage." It also regenerates the control signal on repeated core power-down/power-up.
• § 102 relevance: Closest, but anticipation not made out. It does not disclose feedback circuit(s) coupled to an up/down detector to adjust current capacity, nor the claimed three-series-transistor detector with the first/second transistor switch logic of claim 1's closing clauses, nor claim 8/17's "logic-high signal at the control gates of first, second and third series transistors." It is strong § 103 material against the leakage-avoidance motivation and against claim 1's "leakage reduction" functional backdrop; a combination could target claims 1, 5, 6, 8, 17.
• Primary URL: https://patents.google.com/patent/US20070030039A1/en

2. US 6,646,844 B1 — "Apparatus for power-on disable in a multiple power supply system and a method therefor"

• Citation: US 6,646,844 B1; filed 1999-12-15; published 2003-11-11; Motorola, Inc. (inventor Lloyd P. Matthews). (Verified: read the full disclosure.)
• Description: A multi-supply system (VDDH high / VDD low) with a controller that compares the two supply signals and asserts an "enable override" to disable output pads during power sequencing, to prevent erroneous data — explicitly naming automotive, wireless-communication-device and computer-system contexts. This is the Matthews (Ex. 1009) reference that Apple used in the Apple v. Qualcomm IPRs.
• § 102 relevance: No § 102 anticipation. It disables pads via a comparator/controller, not via a detector whose current capacity is feedback-adjusted. It was used in the IPRs as § 103 support, and specifically against the device-context claims — the PTAB found it taught the limitations of dependent claims 7, 16 and 22 (die-in-device / device-selection recitations: mobile phone, PDA, navigation device, set-top box, computer, etc.).
• Primary URL: https://patents.google.com/patent/US6646844

3. WO 2007/091211 A2 — "Circuit arrangement and method for detecting a power down situation of a voltage supply source"

• Citation: WO 2007/091211 A2; priority 2006-02-09; published 2007-08-16; NXP B.V. (Title/date verified from the '674 front page; full text not opened — tool limit.)
• Description (per title/abstract-level): A circuit arrangement and method for detecting a power-down situation of a supply source — directly on-point to the "detect power-down of the second supply voltage" step of method claim 8.
• § 102 relevance: Relevant to claim 8's detection step and to claims 12–15 (logic-low detection and current-capacity increase). Anticipation of claim 8 as a whole is not made out on the face of the title alone — the reference would need to also disclose adjusting the detector's current capacity via feedback. Flagged as § 103 relevance to claims 8, 12–15.

4. US 2009/0027087 A1 — "Low power voltage detection circuit and method therefor"

• Citation: US 2009/0027087 A1; priority 2005-06-06; published 2009-01-29; inventor Frantisek Sukup. (Title/date verified from the '674 front page; full text not opened — tool limit.)
• Description: A low-power voltage detection circuit and method — squarely in the "reduce power while detecting supply level" space the '674 patent is about.
• § 102 relevance: Relevant to claim 8's "reducing power consumption in a POC network" preamble. Again, no showing of the detector-current-capacity feedback limitation, so § 103, not § 102.

5. US 5,130,569 A — "Power-on reset circuit"

• Citation: US 5,130,569 A; filed 1991-03-12; published 1992-07-14; Harris Corporation. (Title/date from the '674 front page; text not opened.)
• Description: A classic power-on reset circuit. This is one of the two references the record identifies as cited by the examiner (it appears without the third-party asterisk and is a §102/§103 foundational POR reference).
• § 102 relevance: Generic POR art; it does not address multi-supply feedback-controlled detection. § 103 background only; claims 1, 8, 17 not anticipated.

6. US 5,781,051 A — "Power-up detector for low power systems"

• Citation: US 5,781,051 A; filed 1996-07-26; published 1998-07-14; Exel Microelectronics, Inc. (Title/date from the '674 front page; text not opened.)
• Description: A power-up detector for low-power systems — the antecedent of the '674 "power up/down detector" element.
• § 102 relevance: Relevant to claim 1's "up/down detector configured to detect a power state"; does not disclose the feedback/current-capacity adjustment. § 103, not § 102.

7. US 6,577,166 B2 — "Voltage level detector and voltage generator using the same"

• Citation: US 6,577,166 B2; filed 2000-10-19; published 2003-06-10; Samsung Electronics Co., Ltd. (Title/date from the '674 front page; text not opened.)
• Description: A voltage level detector and a generator using it.
• § 102 relevance: Relates to claim 1's "up/down detector… configured to detect a power state." § 103 background; no anticipation.

Tier 2 — General power-on-reset / detection art

Tier 3 — Apparently anomalous citation

17. US 4,781,051 A — "Rolling mill stand with axially shiftable rolls"

• Citation: US 4,781,051 A; filed 1985-04-16; published 1988-11-01; SMS Schloemann-Siemag AG (inventors Schultes et al.).
• Description: A mechanical rolling-mill stand — electrically and technically unrelated to power-up/down detection.
• § 102 relevance: None. I flag this rather than silently dropping it, because (i) the rules direct me not to auto-correct identifiers, and (ii) the citation data plausibly reflects an OCR/indexing artifact or a mis-citation in the underlying record. Do not treat US 4,781,051 A as prior art to any claim of the '674 patent on the strength of this listing. (Note also that the granted patent PDF prints this entry as "4,781,051 A … Schultes et al.," consistent with the front-page row.)

3. Non-patent citation

• International Search Report and Written Opinion — PCT/US2010/023081, International Search Authority — European Patent Office, Aug. 5, 2010. This is the international counterpart search report for the '674 family (WO 2010/091105 A2). It is the examiner-visible NPL reference on the front page and may itself list further art not reproduced in the Google Patents "Patent Citations" table.

4. The art actually litigated (important context — not front-page "citations")

The references that came closest to invalidating the '674 claims were not among the 17 examiner citations. In IPR2018-01315 / IPR2018-01316 (Apple Inc., petitioned June 29, 2018), the PTAB's Final Written Decision relied on:

• AAPA — Applicant Admitted Prior Art, i.e. the Figure 1 circuit of the '674 patent itself (the PMOS/NMOS stack M1–M3). This is the practical "anticipation" candidate for the first/second/third series-transistor language of granted claims 1, 8 and 17 — the AAPA circuit is exactly the three-transistor stack recited at the close of those claims.
• Majcherczak — the primary secondary reference in Ground 2.
• Matthews = US 6,646,844 B1 (see Tier 1, item 2) — used against device-context claims 7, 16, 22.
• Steinacker — "Circuit Arrangement Receiving Different Supply Voltages."
• Doyle — "CMOS Input Level Shifting Circuit with Temperature-Compensating N-Channel Field Effect Transistor Structure."
• Park — "Sleepy Stack Leakage Reduction."

Two cautions grounded in the record I reviewed:

1. These were applied as § 103 combinations, not § 102 anticipations. The PTAB found claims obvious "based on the combined teachings of AAPA and Majcherczak," and separately over AAPA + Majcherczak + Matthews.
2. The Federal Circuit held (Nos. 20-1558/20-1559, then Nos. 23-1208/23-1209, reversed Apr. 23, 2025) that AAPA cannot serve as the "basis" of an IPR ground under § 311(b) — the thrust of Qualcomm Inc. v. Apple Inc. This means the AAPA-centered grounds are legally infirm, even though AAPA remains technically descriptive of the recited transistor stack. (Consistent with the "previously generated sections" of this analysis, which are authoritative on the litigation history; I am not repeating that history here.)

Additional post-issuance art (not anticipatory; noting for completeness): the record's "Cited By" list includes US 10,094,859 B1 (Invecas, "Voltage detector," 2018) and US 11,165,425 B2 (Nexperia, "Power supply detection circuit," 2021) — both later-filed and therefore incapable of anticipating the '674 patent under § 102.

5. Bottom line

• Most relevant cited references: US 2007/0030039 A1 (TSMC), US 6,646,844 B1 (Motorola/Matthews), WO 2007/091211 A2 (NXP), and US 2009/0027087 A1 (Sukup) — each addresses multi-supply sequencing and/or leakage-current reduction, but none discloses the feedback circuit that adjusts the detector's current capacity, which is the point of novelty in independent claims 1, 8 and 17.
• No single reference among the 17 anticipates any independent claim under § 102. Their realistic significance is as § 103 material, chiefly against claims 1, 5, 8, 12–15, 17–20, and (for the device-context recitations) claims 7, 16, 21, 22.
• The only reference exhibiting the "first/second/third series transistor" structure of claims 1, 8 and 17 is the '674 patent's own Figure 1 (AAPA) — which, per the 2025 Federal Circuit decisions, cannot form the basis of an IPR ground under § 311(b).
• US 4,781,051 A (rolling-mill stand) is not relevant prior art to any claim and appears to be a record artifact; I have flagged rather than corrected it.

Confidence/uncertainty: The citation list and dates are high-confidence (taken from the granted front page). My § 102/§ 103 characterizations are high-confidence for the three references I opened in full and are inferred from title/subject-matter for US 2006/0103437 A1, US 2009/0027087 A1, WO 2007/091211 A2, and US 2002/0163364 A1, which I could not open within the search budget; those four should be re-verified against full text before being relied on. I did not find any 2026 docket activity specific to this patent.

Primary URLs:

• https://patents.google.com/patent/US8063674/en
• https://patents.google.com/patent/US20070030039A1/en
• https://patents.google.com/patent/US20080218223A1/en
• https://patents.google.com/patent/US6646844
• https://patentimages.storage.googleapis.com/36/96/4b/92e4a5118be1af/US8063674.pdf (granted front page / citation list)
• PTAB FWD excerpts: https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1514995](/patent/1514995)/...

I'll ground the obviousness analysis in the patent's own cited prior art. Let me pull details on the key references from the Prior Art section.

Let me pull the remaining cited references and the IPR record for the grounds analysis.

Obviousness Analysis of U.S. Patent No. 8,063,674 Under 35 U.S.C. § 103

Scope note: This analysis builds on the earlier-generated bibliographic, abstract, claim-overview, and litigation sections without repeating them. It is limited to the references appearing in the Prior Art / Patent Citations / Family Cites Families / Non-Patent Citations portions of the Google Patents record (https://patents.google.com/patent/[US8063674](/patent/US8063674)/en), plus the IPR-based references noted in the litigation section (which I flag as reported but not independently verified in this session).

Date caveat (contradiction flagged): The task header states "Current Date: April 26, 2026," while the system date is 2026‑09‑27 and the patent text was fetched 2026‑09‑26. All "as-of" statements below therefore relate to the 2025–2026 window generally (the last confirmed event being the IPR certificate effective September 25, 2025).

1. Legal framework and what must be established

Under Graham v. John Deere, 383 U.S. 1 (1966), and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), obviousness turns on: (1) the scope and content of the prior art; (2) the differences between the prior art and the claims; (3) the level of ordinary skill; and (4) secondary considerations. Under KSR, a combination is obvious where the references address the same problem, come from the same field of endeavor, and the combination yields predictable results — and under MPEP § 2143, a claimed improvement is obvious where "a known technique [is] used to improve a similar device in the same way."

Critical threshold issue — AAPA is not "prior art" for IPR, but can be an admission for § 103 generally. The Federal Circuit in Qualcomm Inc. v. [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), 24 F.4th 1367 (Fed. Cir. 2022) ("Qualcomm I") and again in 134 F.4th 1355 (Fed. Cir. 2025) ("Qualcomm II") held that Applicant Admitted Prior Art ("AAPA") — the Figure 1/Figure 2 "PRIOR ART" POC circuit of the '674 patent itself — is not "prior art consisting of patents or printed publications" under 35 U.S.C. § 311(b) and cannot form the basis of an IPR ground. That is a procedural limitation specific to IPR. In district-court litigation, however, statements in a patent specification describing the prior art are usable as evidentiary admissions (In re Nomiya; MPEP § 2129), so the Figure 1 POC detector remains fair game as an admission for a § 103 challenge — but a well-pleaded invalidity contention will still want true patents/printed publications to supply each structural element. That is the lens I apply below: I use the AAPA circuit only to supply the undisputed backdrop (the M1/M2/M3 detector with gates tied to Vcore, the amplifier, and the output buffer), and I identify actual printed references to supply every claimed element.

2. Level of ordinary skill in the art (POSITA)

A POSITA here would be a circuit designer with a B.S. in electrical engineering (or equivalent) and 2–4 years of experience designing multi-supply CMOS ICs, power-on-reset/under-voltage-lockout (UVLO) detectors, level shifters, and I/O power sequencing circuits. This person would be familiar with: (a) leakage in stacked MOS detectors when one supply is up and the other is down; (b) the speed/leakage tradeoff in transistor sizing and threshold-voltage selection; and (c) the routine design technique of tying a detection output back to a switch that changes the detector's bias or device complement. This skill level is corroborated by the '674 patent's own framing of the problem (power-collapse leakage vs. detection speed) and by the referenced art's data sheets (e.g., National Semiconductor "LMS33460 3V Under Voltage Detector," cited in Freescale's US 2008/0218223 A1).

3. Reference inventory (from the page's Prior Art section)

4. The key claim elements and where they are found

Adopting claim 1's own internal convention (in which "first supply voltage" = the core/Vcore and "second supply voltage" = the I/O/VI/O — see the previously flagged inversion relative to the Abstract), the material limitations are:

(A) core network at a first supply voltage; (B) a control network transmitting a control signal, comprising (i) an up/down detector sensing the core's power state, (ii) processing circuitry generating the control signal from that state; (C) one or more feedback circuits coupled to the detector and configured to provide feedback signals to adjust a current capacity of the detector; (D) a first transistor coupled to a second supply voltage, ON when the first supply is down and OFF when it is up; (E) a second transistor in series with the first and coupled to the first supply, ON when first supply is up; (F) a third transistor in series between the first and second transistors.

The decisive, patentability-bearing element is (C) — the feedback-controlled current capacity. Elements (A), (B), (D), (E), (F) are all shown in the AAPA circuit: the spec. describes M1 (coupled to VI/O, on when Vcore is down), M2/M3 (coupled to Vcore, on when Vcore is up), stacked in series with gates tied to Vcore, feeding amplifier 105 (processing circuitry) and output buffer 106.

5. Proposed § 103 grounds

Ground 1 (primary): AAPA + Freescale/Kimura (US 2008/0218223 A1) — and optionally Motorola '844

Mapping. AAPA supplies (A), (B), (D), (E), (F) and the multi-supply context. Kimura supplies (C): a detection circuit whose latch produces a feedback signal that turns off current-carrying transistor(s) (M3 and M4) when power-on is detected, expressly "to reduce power consumption when the power goes on." Kimura's Fig. 2 timing chart ("the current values at a current source I1 and a transistor M2") and its operation paragraphs map directly onto "decrease the detector's current capacity in response to power-on detection" (claim 8) and "feedback signals to adjust a current capacity of said up/down detector" (claim 1).

Motivation to combine. Both references address the identical problem the '674 patent identifies: excess current in a supply-threshold detector after the monitored supply has reached operating level. Kimura states the motivation in terms ("power consumption can be reduced"). The combination is a known technique (feedback-disable of a detector leg) applied to a similar device (a threshold-based supply detector) in the same way, with predictable results — the KSR / MPEP § 2143 rationales. There is no teaching away; Kimura's feedback is agnostic to the number of supplies.

Adding Motorola '844 strengthens the "multiple supply voltage device" and "I/O network … configured to receive said control signal" elements of claim 5: Motorola expressly discloses a multi-supply system with output pads disabled by a control ("enable override") derived from comparing the two supplies, i.e., the same architecture-level solution (disable I/O when the core is not up). A POSITA seeking to implement the '674 detector in a real multi-supply SoC would naturally look to Motorola's pad-disable teaching.

Weakness / rebuttal. Kimura's detector is a current-comparator/latch POR, not a stacked PMOS/NMOS threshold detector with gates tied to the other supply. Qualcomm would argue non-analogous art (POR for a single rail vs. cross-supply POC). Counter: KSR rejects rigid field-of-endeavor boundaries where the references are drawn from the same field of endeavor (supply-voltage detection) and address the same problem; Motorola '844 and NXP bridge the multi-supply gap.

Ground 2: AAPA + Sukup (US 2009/0027087 A1 / US 7,733,155 B2) — with Motorola '844

Mapping. Sukup's switched feedback network (resistor 38/39 + feedback decoupling transistor 35) changes the detector's bias/threshold as a function of the detected supply state, and its first voltage-detection device 11 is described as deliberately low-current ("Circuit 11 has very low power consumption …"), with the higher-power comparator 37 switched in only after power-up. That is feedback-driven adjustment of the detection circuitry's current demand.

Motivation. Both are UVLO/threshold-detection circuits; Sukup's stated object ("it is desirable to have a voltage detection circuit that has low power dissipation, and that has accurate detection of at least the lower threshold value") is the same leakage-accuracy tradeoff the '674 patent recites. A POSITA would combine the switched-feedback concept with the AAPA stacked detector to obtain low leakage after power-up plus fast response at thresholds. Adding Motorola '844 supplies the multi-supply/I-O-disable architecture and die-integration teaching (claims 5–7).

Weakness. Sukup is hysteresis/threshold-shifting rather than device-complement switching; Qualcomm may argue that it does not teach changing current capacity via switched transistor legs. This is why Ground 1 (Kimura) is the stronger primary ground and Ground 2 is a cumulative/alternative ground.

Ground 3: AAPA + NXP (WO 2007/091211 A2 / US 2009/0002034 A1)

Mapping. NXP discloses a multi-supply (Vdd/Vcc) power-down detector with a fourth switching element (MN4) in parallel with a detector transistor (MN1), driven by a feedback node (E) derived from the detection circuitry itself, to speed the detector's response on power-down and to hold static current at femtoampere levels. This is materially the '674 claiming structure: a parallel feedback transistor (claims 2–4) that adjusts the detector leg's current capacity in response to the processing circuitry's output.

Motivation. NXP expressly states the two objectives the '674 patent claims — faster detection ("the power down detection … is much faster and much more reliable") and low leakage ("the total power dissipated … may be reduced"). Same field, same problem, predictable result. Directly supports claims 2, 3, 4, 9–11 and 13–15 (feedback transistors paralleling the first/second detector transistors).

Weakness. NXP figures focus on power-down detection speed; its feedback transistor accelerates discharge rather than reducing current on power-up. Qualcomm would argue the feedback direction differs from claim 8's "decrease on power-on." Ground 3 is best used as a supplemental ground (or in combination with Kimura, which supplies the power-on current reduction).

Ground 4: Motorola '844 + Kimura + Sukup (no AAPA reliance)

For a challenge that avoids AAPA entirely (to sidestep the Qualcomm I/II § 311(b) concern in an IPR, or to build a robust litigation record), use:

• Motorola '844 as the base multi-supply device with a core/pad split and a supply-comparison-derived disable signal (satisfies (A), (B)(i)-(ii), the I/O network, and the die/device claims 5–7);
• Kimura for the feedback signal that disables detector current after power-on ((C), (D)-(F) in a stacked switch form; claim 8 steps);
• Sukup for the switched feedback network / low-power detection bias (changing current capacity; claim 8's decrease/increase steps);
• Rochester US 6,900,666 for the express teaching that dual-threshold devices change detection speed vs. leakage (supports the "current capacity" design lever and the dependent claims touching low-threshold NMOS use, which the '674 spec. itself invokes at Fig. 5).

This ground is weaker on the exact stacked first/second/third transistor topology but avoids the AAPA admission problem. A well-constructed invalidity case would plead Ground 4 as the primary, non-IPR-affected ground and Grounds 1–3 as supplemental.

Claims 6, 7, 16, 21, 22 (die/device incorporation)

Motorola '844 (die-level integration; "the data processing system 100 could be a microprocessor, a microcontroller, a wireless communication device, an embedded system"), Sukup (Fig. 2 semiconductor device 70 on die 71), and the '674 patent's own wireless-device list make these "integrated into a semiconductor die / incorporated in [list of devices]" claims an obvious application of the underlying circuit; no separate inventive contribution. Note the drafting defect already flagged (claims 21/22 recite "multiple supply voltage device" while depending from system claim 17) — treat these as formal, not substantive.

Claim 17 (means-plus-function)

Each means is a purely functional recitation of the structures described above (detector switch legs; feedback switch; processor). Under Williamson v. Citrix, the corresponding structures are those in the '674 spec. (M4–M10, inverter 400, buffer 401), all of which are disclosed or rendered obvious by Grounds 1–3.

6. Secondary considerations

No evidence of record in the materials reviewed supports: unexpected results (the '674 patent asserts only conventional leakage/speed tradeoffs), long-felt need (the problem was already addressed by Kimura, Sukup, NXP, and Motorola), failure of others, or commercial success tied to the claimed feedback feature. The extensive litigation (IPR2018-01315/-01316; ITC 337-TA-1093; S.D. Cal. 3:17-cv-02398) is evidence of commercial significance, not of non-obviousness — and the PTAB on two occasions found the claims unpatentable under AAPA-based grounds (later reversed on § 311(b) procedural grounds, not on the merits of the technical combination). That merits history actually confirms the technical weakness of the feedback limitations against the art.

7. Assessment and confidence

• Claim 1 / claims 2–7 (feedback transistors, I/O network, die/device): Moderately strong obviousness case via AAPA + Kimura (Ground 1) and, independently, Motorola + Kimura + Sukup (Ground 4). Confidence: moderate. The main vulnerabilities are (a) the AAPA-as-basis problem (Qualcomm I/II), and (b) whether Kimura/NXP's feedback direction is close enough to the claim's "adjust a current capacity."
• Claim 8 / claims 9–16 (method): Same analysis; Kimura's operation paragraphs literally describe decreasing detector current on power-on detection, which maps to claim 8's core steps. Confidence: moderate.
• Claim 17 / claims 18–22 (means-plus-function): Weakest of the three independent claims from a defendant's perspective, because functional claiming invites broad prior-art mapping. Confidence in obviousness: moderate-to-high.

Explicit uncertainties:

1. I could not verify the disclosures of Majcherczak and Matthews (the IPR secondary references) in this session; the previous section's account of those grounds should be treated as reported, not confirmed.
2. My searches of the page's cited references did not include a document-by-document figure-level reading of US 5,130,569, US 5,495,453, US 5,723,990, US 6,577,166, US 2002/0163364, US 2005/0174130-type, US 2006/0044027, US 2006/0103437, US 7,253,655, and US 2008/0100341; those are characterized at a level consistent with their titles/abstracts and could yield additional or stronger element-by-element mappings on review.
3. The "Family Cites Families" art (JPH01223820A, JP3169775B2, KR100487526B1, US7057907B2, JP2006352204A) is background; I did not analyze it for independent anticipation/obviousness value.
4. The Cited By documents (US 10,094,859 B1; US 11,165,425 B2) and the 16 "Families Citing" documents post-date the '674 priority and were excluded as non-prior-art.
5. All identifiers are reproduced as they appear in the source; none were auto-corrected.

Bottom line: On the record available, the '674 claims are vulnerable under § 103 through several overlapping combinations, the strongest being (AAPA or Motorola '844) + Freescale/Kimura US 2008/0218223 A1, supplemented by Sukup US 2009/0027087 A1 and NXP WO 2007/091211 A2 for the feedback-adjusts-current-capacity and parallel-feedback-transistor limitations. The motivation is supplied by the shared, expressly-stated objective — cutting detector leakage while preserving detection speed in a multi-supply device — which is exactly the rationale the AIA/KSR line of cases requires. The principal obstacle to a clean invalidity holding is not the technical combination but the procedural bar on using AAPA as the basis of an IPR ground (Qualcomm I/II), which a challenger must route around by anchoring the ground in true patents/printed publications such as Motorola '844, Kimura, and Sukup.