Summary of US Patent 7,812,399 (US7812399B2)

Authoritative bibliographic data

Abstract (as published)

"The present invention provides a semiconductor device which includes a gate electrode shaped in the form of an approximately quadrangular prism, including a laminated body of a gate oxide layer, a gate polysilicon layer and a gate silicon nitride layer provided in a first conduction type substrate, a second conduction type implantation region provided in a region outside the gate electrode, a sidewall that exposes a top face of the gate electrode and is formed by laminating a sidewall mask oxide layer covering side surfaces, an electron storage nitride layer and a sidewall silicon oxide layer, and a source/drain diffusion layer provided in the first conduction type substrate exposed from the gate electrode and the sidewall."

Plain-language overview of the independent claims

The full claims section was truncated in the source material, so the claim analysis below is based on the independent claims as recited in the patent's "Summary of the Invention" (verified against the Google Patents and FreePatentsOnline records found in search). There appear to be two independent claims: one apparatus claim and one method claim. Note the uncertainty: I could not verify the exact claim numbering or confirm whether additional independent claims exist, because the complete claims text was not available in the fetched document.

Independent apparatus claim (semiconductor device) — covers a transistor/memory cell comprising:

• A first-conduction-type (e.g., P-type) substrate;
• A gate electrode shaped as an approximately quadrangular prism, formed as a stack of a gate oxide layer, a gate polysilicon layer, and a gate silicon nitride layer, with a rectangular top face and four side surfaces (first, second opposite to first, third between them, and fourth opposite to third);
• A second-conduction-type (e.g., N-type) implantation region in the substrate outside the gate electrode, having four implantation regions each abutting (in junction with) a respective one of the four side surfaces;
• A sidewall that exposes the top face and covers all four side surfaces as an integral body, composed of three laminated layers: a sidewall mask oxide layer, an electron storage nitride layer (with four partial regions respectively opposite the four side surfaces, able to store charge independently for 4-bit operation), and a sidewall silicon oxide layer; and
• A source/drain diffusion layer in the substrate exposed from the gate electrode and sidewall.

Independent method claim (manufacturing method) — covers a process of:

1. Forming a gate oxide film, gate polysilicon film, and gate silicon nitride film over the substrate;
2. Patterning them into an approximately quadrangular-prism gate electrode having a rectangular top face and first/second/third/fourth side surfaces;
3. Forming a sidewall mask oxide film covering the exposed substrate and gate electrode;
4. Implanting a second-conduction-type impurity using the gate electrode as a mask to form the four-part implantation region;
5. Forming an electron storage nitride film over the sidewall mask oxide film, then a sidewall silicon oxide film over it;
6. Etching back the three films to form a sidewall exposing the gate top face, reaching part of the substrate, and integrally covering all four side surfaces; and
7. Implanting a second-conduction-type impurity into the exposed substrate to form the source/drain diffusion layer.

CAFC 2026 docket search result

Searches of CAFC 2026 dockets for "7812399" returned no results. I found no indication of any appeal, litigation, or CAFC proceeding involving this patent. If you need a definitive docket check, the CAFC's public docket database (PACER/CM/ECF) should be queried directly, as web-search coverage of 2026 dockets appears incomplete.

Other notes

• Search results confirm the Google Patents record (patents.google.com/patent/US7812399B2/en) and FreePatentsOnline (FreePatentsOnline.com/7812399.html), which agree on title, inventor, assignee chain (Oki Electric Industry → Oki Semiconductor → Lapis Semiconductor), and dates.
• The invention addresses a known problem: in conventional 2-bit-per-side transistors, cell current (memory) windows narrow when electrons are stored in storage layers on opposite sides of the gate; by storing charge in four independent regions around all four sides of a quadrangular gate, the patent claims more reliable 4-bit write/read with stable cell current windows.

I'll search multiple litigation databases and sources for cases involving US Patent 7,812,399.

The initial searches surfaced many results for 7,818,399 (the DDR Holdings e-commerce patent) — that is a different patent number and I will not conflate it with 7,812,399. Let me run more targeted searches on the correct number.

Litigation Search Results: US Patent 7,812,399 (US7812399B2)

Based on my searches across general web sources, CourtListener, Unified Patents, and the previously conducted CAFC docket check, I found no known litigation involving US Patent 7,812,399 as of April 26, 2026.

Searches performed

1. General web search — "7812399" patent litigation and "7,812,399" lawsuit patent infringement: no results referencing 7,812,399 in any litigation context.
2. Unified Patents litigation portal (site:portal.unifiedpatents.com "7812399"): zero results returned.
3. CourtListener (site:courtlistener.com "7812399"): zero results returned.
4. CAFC 2026 docket search (conducted in the prior analysis section): no results for "7812399" — no indication of any appeal or Federal Circuit proceeding.
5. Assignee-based search ("7,812,399" Lapis Semiconductor OR Oki Semiconductor): only patent-record and portfolio pages (e.g., patent leaderboards, assignee listings), no litigation records.

Critical caveat: do not conflate with 7,818,399

The searches surfaced substantial litigation involving US Patent 7,818,399 B1 — the DDR Holdings, LLC e-commerce patent (composite web pages / "outsource provider" technology). That patent is owned by DDR Holdings and has been litigated in multiple actions, including:

• DDR Holdings, LLC v. Priceline.com LLC, D. Del., No. 1:17-cv-00498 (filed ~May 2, 2017; involved US 7,818,399 among others)
• DDR Holdings, LLC v. Booking.com BV, D. Del., No. 1:17-cv-00499
• DDR Holdings, LLC v. Hotels.com, L.P., Fed. Cir., 773 F.3d 1245 (2014)
• DDR Holdings, LLC v. Priceline.com LLC, Fed. Cir. (2020) — after IPR and stipulation of non-infringement

These cases are entirely unrelated to 7,812,399. The numbers differ (7,818,399 vs. 7,812,399), the technology differs (e-commerce web-page generation vs. multi-layer gate-electrode semiconductor memory cells), and the owners differ (DDR Holdings vs. Oki Semiconductor/Lapis Semiconductor). Per your instruction to interpret patent numbers literally, I am flagging this rather than reporting the DDR Holdings cases as litigation involving your patent.

Conclusion

• Plaintiff(s): None identified
• Defendant(s): None identified
• Jurisdiction / case number / filing date: N/A
• Outcome / current status: No litigation located

Confidence and limitations

I have moderate-to-high confidence that US 7,812,399 has not been asserted in US district court litigation, based on the absence of hits in CourtListener, Unified Patents, general web searches, and CAFC dockets. However, I must state an important limitation: web-search coverage is not exhaustive, and I could not directly query PACER or the full Unified Patents case-list interface. A definitive clearance would require:

• A PACER nationwide party-name / patent-number search (covering all district courts), and
• Direct queries of the USPTO Patent Trial and Appeal Board (PTAB) for any inter partes review, post-grant review, or covered-business-method challenges, and of the ITC for any Section 337 investigations.

If you need that deeper verification, I can run those specific database queries in a follow-up.

Proceedings overview

Zero AIA trial proceedings exist on US Patent 7,812,399. The USPTO Open Data Portal (ODP) structured data in this prompt — the canonical list — reports no inter partes review, post-grant review, or covered business method review on file for this patent, and my independent web searches corroborate that: searches combining the patent number with "PTAB," "IPR," "inter partes review," and the assignee names (Lapis Semiconductor, Oki Semiconductor) returned no proceeding records whatsoever. Status breakdown: 0 instituted, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution-denied. The defensive posture this gives a defendant: the patent is entirely untested at the PTAB — no claim has ever been canceled, but equally no claim has ever survived Board scrutiny; every invalidity ground remains available to a challenger who files within the statutory window.

No proceedings to report

There are no IPR/PGR/CBM proceeding entries to list. I will not fabricate proceeding numbers, judge panels, institution decisions, or Final Written Decisions — none exist in the ODP ingest or in any public source I could locate.

Two near-miss patent numbers to avoid conflating with 7,812,399 (per the literal-number rule, these are unrelated and must not be reported as activity on this patent):

• US 7,818,399 B1 (DDR Holdings) — the e-commerce "composite web page" patent, which has been through extensive PTAB and district-court litigation (e.g., Shopify, Inc. v. DDR Holdings, LLC, IPR2018-01008 through IPR2018-01014; DDR Holdings, LLC v. Hotels.com, 773 F.3d 1245 (Fed. Cir. 2014)). Different number, different owner, different technology.
• US 7,812,409 B2 (Force MOS Technology) — a trenched-MOSFET patent challenged in IPR2024-00094-style proceedings by Inergy Technology. Again, a different patent.

Neither has anything to do with 7,812,399.

Strategic summary

Claim status: 100% UNTESTED. Because the ODP list is empty and no FWD exists, no claim of US 7,812,399 — independent or dependent — has been canceled, and none has been sustained. For planning purposes, the patent should be treated as having its full original claim set intact (the published record suggests two independent claims — one apparatus, one method — plus dependents, but the complete claims text was truncated in the source material, so confirm the claim set from the USPTO full-text before drafting).

Estoppel landscape: clean slate. No petition has been filed, so no one is subject to § 315(e)(2) estoppel with respect to this patent. Every § 102/§ 103 ground built on patents or printed publications is still available to a defendant — there is no "reasonably could have raised" bar because no AIA trial has ever been conducted. The only timing constraint that matters is the § 315(b) one-year bar: an IPR petition must be filed within one year of service of a complaint alleging infringement of this patent. If you are served today (2026-08-27), the filing window closes 2027-08-27.

Pattern signals: none. No repeat petitioner, no defensive aggregator (Unified Patents or similar) in the chain, and no patent-owner aggressiveness at the Board to account for. The absence of PTAB activity is itself a meaningful signal: this patent issued in 2010, has a 2006 priority date, and its adjusted expiration is ~2028-03-16 — it is in its final ~18 months of life, and after ~16 years on the books it has attracted zero AIA challenges. That profile is consistent with a patent that has not been commercially asserted (recall the prior analysis found no district-court litigation and no CAFC docket activity either). Patents that are actually being asserted at scale tend to draw IPRs; this one has not.

Recommended next steps

1. If you are a defendant facing a demand letter citing 7,812,399, the practical read is that this is likely a low-quality assertion. No court case, no PTAB challenge, and a patent expiring ~2028-03-16. But do not rely on my web-search silence alone — verify with primary sources:

   • USPTO PTAB E2E / ODP API — query by patent number to confirm zero AIA trials (the ODP ingest in this prompt is authoritative but dated).
   • PACER nationwide search — run a patent-number search across all district courts to confirm no newly-filed case naming 7,812,399 (web coverage of 2026 filings is incomplete).
   • USPTO Patent Center / Assignment DB — confirm the current owner chain (Lapis Semiconductor Co., Ltd. via Oki Semiconductor Co., Ltd.) so you are negotiating with the right party.

2. If you are served with a complaint, the IPR calculus is straightforward but time-boxed: file within the one-year § 315(b) window; because no prior Board decision exists, you face no estoppel and can run your best § 102/§ 103 grounds. Given the patent's ~18-month remaining life, weigh IPR cost against the alternative of riding out expiration — a stay motion tied to a short remaining term may be an efficient play.

3. If you are evaluating the patent for purchase/licensing diligence: the clean PTAB record cuts both ways — it means no claim has been weakened, but also that the claims have never been battle-tested; obtain the full claims text (the fetched record was truncated) and run a fresh prior-art search before assigning any value.

Bottom line: there is no PTAB history on this patent — and that absence is consistent with a patent that appears never to have been asserted in court. Treat the claims as presumptively valid but entirely unproven, and treat any assertion letter as one you can likely outlast or defeat on the merits with untapped prior art.

Inventors

Takashi Yuda — sole named inventor.

• Employer at time of filing: Oki Electric Industry Co., Ltd. (LSI / semiconductor division), Tokyo, Japan. This is corroborated by the Japanese priority application (JP2006-100891, filed 2006-03-31 by Oki Electric Industry, counterpart JP4680116B2) and by the recorded assignment of 2007-03-29, which names the assignor as "YUDA, TAKASHI" conveying to Oki Electric Industry Co., Ltd. — the standard employee-inventor-to-employer pattern.
• Unusual patterns: None evident. I found no data suggesting Yuda departed Oki within 12 months of filing or that the filing was tied to a portfolio fire-sale. The patent lists one inventor only; no co-inventor anomalies.

Original assignee

• Entity named on the issued patent: Oki Electric Industry Co., Ltd. via the 2007-03-29 recorded assignment of the inventor's interest (Google Patents now displays the current assignee as Lapis Semiconductor Co., Ltd., reflecting the later name changes). Note a display quirk: Google's "Application filed by Oki Semiconductor Co Ltd (2007-03-29)" is anachronistic — Oki Semiconductor Co., Ltd. was not incorporated until October 2008; at filing the application belonged to Oki Electric Industry's LSI division, and the recorded conveyance on the same date runs to Oki Electric Industry Co., Ltd.
• Line of business: Oki Electric Industry is a diversified Japanese electronics manufacturer (telecommunications equipment, printers, and — at filing — LSI/semiconductor products). The invention is a 4-bit non-volatile memory transistor cell for the LSI business.
• Product embodying the claims: Unverified. Oki's LSI division produced semiconductor products, but I could not confirm a specific shipped product embodying the exact quadrangular-gate/four-sidewall-charge-storage claims.
• Current status: Oki Electric Industry Co., Ltd. still operates. Its semiconductor business was transferred to Oki Semiconductor Co., Ltd. (established October 2008), renamed Lapis Semiconductor Co., Ltd. (2014), and acquired by ROHM Co., Ltd. (2016). Lapis continues to operate as a ROHM-group semiconductor company (microcontrollers, display drivers, LSI). No dissolution or bankruptcy found.

Assignment timeline

The USPTO Assignment Center records could not be retrieved through web search — searches for the patent number returned no indexed reel/frame entries, so I cannot supply reel/frame numbers or correspondent names. I am not fabricating them. The three recorded conveyances below come from the Google Patents legal-events feed for US7812399B2, which is authoritative for dates and conveyance types:

• 2007-03-29 (executed) / recorded 2007-03-29 — Reel not retrievable (searches returned no Assignment Center record)

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Takashi Yuda
  • Assignee: Oki Electric Industry Co., Ltd.
  • Correspondent: not retrievable from available sources
  • Context: Employee-inventor assignment to employer at filing — normal, not a red flag.

• 2009-01-22 (recorded) — Reel not retrievable

  • Conveyance: Change of Name
  • Assignor: Oki Electric Industry Co., Ltd.
  • Assignee: Oki Semiconductor Co., Ltd.
  • Correspondent: not retrievable from available sources
  • Context: Internal reorganization — Oki's LSI business spun into the newly formed Oki Semiconductor subsidiary.

• 2014-03-21 (recorded) — Reel not retrievable

  • Conveyance: Change of Name
  • Assignor: Oki Semiconductor Co., Ltd.
  • Assignee: Lapis Semiconductor Co., Ltd.
  • Correspondent: not retrievable from available sources
  • Context: Corporate rename; no transfer to any third party. Lapis was later acquired by ROHM in 2016, and no further recorded assignment to an outside entity appears in the record.

Plain finding: The record shows only the original inventor assignment plus two intra-family name changes. There is no recorded post-issuance transfer to any LLC, NPE, licensor, or aggregator — which typically means the original corporate family (now Lapis Semiconductor / ROHM group) still owns the patent. If you can reach the Assignment Center directly, verify whether any security agreements or releases (e.g., bank collateral filings) were recorded, as those would not surface in Google's legal-events feed.

Timeline diagram

timeline
    title Ownership of US 7812399
    2006 : Priority filed in Japan
    2007 : Filed in US by Oki Electric
         : Inventor assignment to Oki Electric
    2009 : Name change to Oki Semiconductor
    2010 : US patent issued
    2014 : Name change to Lapis Semiconductor
    2016 : ROHM acquires Lapis Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — not present. Every recorded conveyance stays inside the Oki corporate family (inventor → Oki Electric Industry → Oki Semiconductor → Lapis Semiconductor). Lapis is an operating ROHM-group semiconductor manufacturer, not a licensing-only LLC; no registered-agent-address or single-purpose-LLC pattern appears in any conveyance.
2. Known asserter in the chain — not present. None of Oki Electric Industry, Oki Semiconductor, Lapis Semiconductor, or ROHM appears on standard NPE lists (Acacia, Marathon, Intellectual Ventures, Wi-LAN, Conversant/Mosaid, Innovatio, Round Rock, etc.). The prior litigation analysis found no district-court, CAFC, PTAB, or ITC proceeding naming 7,812,399.
3. Repeat correspondent across the chain — unclear. Correspondent names were not retrievable from any source I could access, so recurrence cannot be assessed. This is a data gap, not a finding either way.
4. Cascading transfers — not present. Only three recorded events spanning ~7 years, two of which are pure name changes. No chained LLCs, no shared-correspondent-address pattern, no rapid-fire conveyancing.
5. Pre-litigation transfer — not present. There is no litigation to precede; the last recorded conveyance (2014 name change) long post-dates issuance and is purely corporate.
6. Bankruptcy fire-sale — not present. No bankruptcy of Oki Electric, Oki Semiconductor, or Lapis was found; Oki Electric Industry continues to operate today.
7. Privateering — not present. No transfer to an NPE for assertion on Oki's behalf; no SEC filing or press coverage suggesting such an arrangement.
8. Defensive aggregator — not present. The chain terminates at Lapis Semiconductor (an operating company), not at RPX, AST, LOT Network, Unified Patents, or OIN. (ROHM/Lapis LOT membership is unverified; I am not inferring it.)

Verdict

Insufficient data

The recorded chain is a clean intra-family corporate succession — inventor → Oki Electric Industry (2007) → Oki Semiconductor (2009, name change) → Lapis Semiconductor (2014, name change) — with zero NPE signals and no litigation anywhere in the record. I am not selecting "Operating-company assertion" or "Defensive / non-asserting" because I could neither verify the USPTO Assignment Center reel/frame entries and correspondents (searches returned no indexed records) nor confirm that Lapis ships a product embodying the exact claims or has asserted the patent. Every available piece of evidence points away from NPE involvement; the classification is limited only by unverified Assignment Center detail. Verify directly at the USPTO Assignment Center search: https://assignmentcenter.uspto.gov/ (search by patent number 7812399).

I'll search for the prior-art citations listed on the face of US Patent 7,812,399 (US7812399B2). Let me query multiple sources.

The second search surfaced the unrelated DDR Holdings patent (7,818,399) — I will disregard it per the strict literal-number rule. Let me now pull the actual "References Cited" list on the face of US7812399B2 from Google Patents and the USPTO.

The direct citation list hasn't surfaced yet. Let me query Espacenet's cited-documents data and the Google Patents citation section specifically.

I've reached the search-step limit, so I'll answer from the available record, being explicit about what is and is not confirmable. The searches did not return the full "References Cited" (examiner citation) list for US7812399B2, and I will not fabricate citations. What is confirmable from the patent's own specification — and from the previously fetched Google Patents record — is the pair of Japanese references expressly identified in the Background section. (Note: searches also returned litigation hits for the unrelated US 7,818,399 DDR Holdings patent; per the literal-number rule, I have excluded that entirely.)

Prior Art Analysis — US Patent 7,812,399 (US7812399B2)

Patent in issue: US 7,812,399 B2, "Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions," inventor Takashi Yuda, filed 2007-03-29 (US 11/693,408), priority 2006-03-31 (JP 2006-100891; granted counterpart JP 4680116 B2), issued 2010-10-12, assignee chain Oki Electric Industry → Oki Semiconductor → Lapis Semiconductor.

Claim scope (for the § 102 analysis below): Per the prior analysis, the full claims text was truncated in the source record, so claim numbering could not be verified. The analysis relies on the two independent claims as recited in the patent's Summary: (1) an apparatus claim — quadrangular-prism gate (gate oxide / gate polysilicon / gate silicon nitride stack) with rectangular top face and first/second/third/fourth side surfaces; a four-part N-type implantation region (first–fourth implantation regions) each in junction with a respective side surface; an integral sidewall of three laminated layers (sidewall mask oxide / electron-storage nitride with four partial regions / sidewall silicon oxide) exposing the gate top face; and a source/drain diffusion layer; and (2) a method claim — the corresponding seven-step fabrication process.

Reference 1 — JP 2004-047593 A (patent document 1 in the '2399 specification)

Description (as characterized in the '2399 specification): Discloses a semiconductor device implementing a ferroelectric memory cell capable of storing polarization data of a multivalue of three values or more in one ferroelectric film. Information equivalent to 4 bits in total is stored at 4 points: two points at both ends as viewed in a first direction of the ferroelectric element, and two points at both ends as viewed in a second direction orthogonal to the first direction.

§ 102 anticipation assessment: This reference supplies the four-position, 4-bit conceptual framework that the '2399 claims build on. However, as characterized in the '2399 specification, it is a ferroelectric storage element. It does not disclose (and the '2399 does not credit it with): the quadrangular-prism gate stack of gate oxide/gate polysilicon/gate silicon nitride; the four-part N-type implantation region in junction with all four side surfaces; the integral three-layer sidewall (sidewall mask oxide / electron-storage nitride with four independently chargeable partial regions / sidewall silicon oxide); or the source/drain diffusion layer. On that record, it does not anticipate either independent claim in full under § 102 — every element of the claimed combination is not present. Its strongest use would be as a § 103 obviousness background reference for the "4 bits at 4 points" concept, and possibly against dependent limitations reciting matrix-array/4-bit operation — but no full-claim anticipation can be substantiated.

Reference 2 — JP 2004-342927 A (patent document 2 in the '2399 specification)

Description (as characterized in the '2399 specification): This is the closest technical-field reference. Discloses a semiconductor device capable of a storage holding operation of 2 bits or more by one transistor and amenable to scale-down, comprising a gate electrode and memory functional bodies formed on both sides of the gate electrode having the function of holding electrons; the amount of current flowing from one diffusion region to the other diffusion region upon application of a voltage to the gate electrode changes depending on the magnitude of electrons held in the memory functional bodies. This is a two-sided, charge-trapping (SONOS-type/NROM-type) sidewall-memory transistor.

§ 102 anticipation assessment: This reference is the most relevant starting point. It discloses a charge-trapping transistor with electron-holding sidewall memory bodies — structurally overlapping the '2399 sidewall charge-storage concept. But, per the '2399's own characterization of the conventional device, it performs 2-bit writing/reading on one pair of opposing side surfaces only (as viewed in the gate-length direction). It does not disclose: storage regions opposite all four side surfaces of a quadrangular gate; the four-part implantation region in junction with all four side surfaces; or the complete three-layer ONO sidewall surrounding the gate as an integral body. The '2399 was designed precisely to fix the memory-window narrowing caused by this two-sided configuration (FIG. 26). Accordingly, this reference does not anticipate the independent apparatus claim or the independent method claim in full — the four-sided storage-region limitation and the four-sided implantation-region limitation are absent. It is the primary § 103 obviousness reference (closest prior art) and could, in combination with Reference 1, form the basis of an obviousness case; but no § 102 anticipation of the full independent claims can be made out on the available record.

What I could not verify (stated explicitly)

1. Complete examiner citation list. The Google Patents fetch provided with the assignment contained the specification but was truncated before the claims and the "References Cited" section, and the web searches conducted did not return the citation tab for US7812399B2. It is very likely the front page carries additional examiner-cited U.S. patents and/or non-patent literature (e.g., the NROM/SONOS art family), but I cannot confirm any specific additional numbers and will not guess them. A definitive list requires a direct query of the USPTO Patent Center (or the Google Patents "Citations" tab), which is the recommended next step.
2. Exact publication days, filing dates, and applicants for the two Japanese references. The '2399 specification cites them only by Kokai number; I have not confirmed the assignees or precise dates from any source, so I have deliberately omitted them.
3. Claim numbering. As noted, the claims text was truncated; the § 102 analysis above maps to the two independent claims (apparatus and method) reconstructed from the Summary of the Invention.

Bottom line: The two confirmable prior-art references for US 7,812,399 are JP 2004-047593 A (ferroelectric, 4-bit-at-4-points concept) and JP 2004-342927 A (two-sided electron-storage sidewall transistor — closest art). On the available record, neither anticipates the independent claims in full under 35 U.S.C. § 102; each is best characterized as relevant § 103 obviousness art, with JP 2004-342927 A being the strongest starting point.

I'll research prior art for US 7,812,399. Since no prior-art section was included in the materials provided, I'll search for the references cited in the patent itself and for other relevant art, then build the § 103 analysis.

I've identified the key cited references. Now let me dig deeper into the patent's citation list, the first cited Japanese reference, and additional 4-bit/sidewall charge-trapping prior art.

I was unable to complete all of my planned searches due to step limits, so I'll answer based on (a) the patent text itself, (b) the references confirmed in my searches, and (c) well-established art in this field. One important scope note first: no "Prior Art" section was included in the materials provided, so I have treated the search results I gathered (plus the two Japanese references the patent itself cites in its Background) as the prior-art universe.

Obviousness Analysis of US 7,812,399 Under 35 U.S.C. § 103

0. Preliminary notes and caveats

• Claims available. The full claims text was truncated in the fetched patent record. This analysis therefore addresses the two independent claims (apparatus + method) as recited in the Summary of the Invention and mirrored in the published application US20070228483A1. Dependent-claim details (matrix array, 45° word lines, first/second bit-line architecture, damascene gate process) are addressed only where they bear on the independent claims.
• Priority date. 2006-03-31 (JP2006-100891). All references must be prior art as of that date to qualify under § 102/§ 103 (pre-AIA rules apply, since the application was filed 2007-03-29).
• Confidence flags. For two candidate references found in search (US20070057318, published 2007-03-15; US20070075354/US7514738, published 2007-04-05), the publication dates fall after the priority date and I could not verify their underlying filing dates, so I cannot confirm they qualify as prior art. They are discussed only secondarily. The references I treat as primary are all confirmed (or nearly certain) to predate 2006-03-31.

1. Elements of the independent claims (claim chart targets)

Apparatus claim:

1. First-conduction-type (P-type) substrate;
2. Gate electrode = approximately quadrangular prism, stack of gate oxide layer / gate polysilicon layer / gate silicon nitride layer, rectangular top face, four side surfaces (1st, 2nd opposite, 3rd between, 4th opposite 3rd);
3. Second-conduction-type (N-type) implantation region outside the gate, with four implantation regions each in junction with one side surface;
4. Sidewall exposing the gate top face, integrally covering all four side surfaces, composed of three laminated layers: sidewall mask oxide / electron storage nitride layer with four partial regions opposite the four side surfaces / sidewall silicon oxide;
5. Source/drain diffusion layer in the substrate exposed from gate + sidewall.

Method claim:

1. Form gate oxide film → gate polysilicon film → gate silicon nitride film;
2. Pattern into quadrangular-prism gate electrode (rectangular top face, four side surfaces);
3. Form sidewall mask oxide film over exposed substrate and gate;
4. Implant N-type impurity using gate as mask → four-part implantation region;
5. Form electron storage nitride film over sidewall mask oxide film;
6. Form sidewall silicon oxide film over nitride film;
7. Etch back the three films → sidewall exposing top face, integrally covering all four side surfaces;
8. Implant N-type impurity → source/drain diffusion layer.

2. Prior-art references identified (with dates)

Also relevant as background for the gate stack: US20040228499 (Oki family) discloses a gate electrode stack with a mask insulating film (oxide, nitride, or oxynitride) on the gate electrode material — i.e., a nitride cap on the gate stack was conventional.

3. Primary § 103 combinations

Combination A — JP2004-342927 + JP2004-047593 + NROM/ONO sidewall-spacer knowledge (Eitan 2000)

This is the strongest combination, and it is built entirely from references the patent itself admits as prior art.

Element mapping (apparatus claim):

Method claim: JP2004-342927's device necessarily requires the same process skeleton (gate stack formation, patterning, LDD implant, charge-storage body formation on gate sides, S/D formation), and every claimed step — oxide/poly/nitride deposition, gate patterning, sidewall-mask oxide, gate-masked implant, nitride + oxide deposition, anisotropic etch-back, S/D implant — was a textbook CMOS + NROM process sequence by 2004 (Eitan 2000; Samsung TSM-ISp 2003). Nothing in the method claim is structurally novel once the 4-sided storage goal is adopted.

Motivation to combine:

• The patent's own Background concedes JP2004-342927 (2-bit-per-side) suffers from narrowed cell current windows when electrons sit on opposite sides of the gate. The patent's stated object is precisely to enable reliable 4-bit write/read.
• JP2004-047593 supplies the direct design incentive: a single memory element can hold 4 bits at four points defined by two orthogonal directions. A PHOSITA seeking higher density would recognize that the 2-bit-per-side transistor of JP2004-342927 can be extended to 4 bits by providing charge storage at all four side surfaces of a quadrangular gate — the natural, geometric implementation of JP2004-047593's four-point teaching in the transistor context of JP2004-342927.
• The ONO sidewall ring is the obvious vehicle: NROM and spacer-SONOS art already used nitride sidewall storage; an etch-back of a conformal ONO stack around a rectangular gate produces, automatically and predictably, an integral spacer covering all four side faces with four discrete partial regions.
• Under KSR International Co. v. Teleflex Inc. (2007), the combination is of known elements (gate stack, ONO charge trapping, sidewall spacers, four-point storage concept) combined according to known methods (CMOS spacer flow, NROM programming) to yield a predictable result (four independently programmable regions), driven by the known design incentive to increase bits per cell. The "problem" (window narrowing) was known, and the solution is the predictable next step of extending storage to the two unused sides.

Combination B — US20050242391A1 (She, 4-bit SONOS) + JP2004-342927 + Eitan 2000

She is the strongest single reference for the 4-bit goal with physically separated nitride storage sites. It teaches:

• Four bits per cell that are "physically and electrically separate from each other, hence they do not interfere or disturb each other during programming/erasing or sensing" — which is verbatim the problem US 7,812,399 solves;
• Spacer-formed nitride charge-storage sites with controllable lateral dimensions;
• Buried-bit-line compatibility.

She, however, implements 4 bits in a FinFET/double-gate geometry (two channels per cell × 2 bits per channel). JP2004-342927 supplies the planar single-gate transistor with side charge-storage functional bodies. Motivation to combine: a PHOSITA wanting She's 4-bit capability without fin processing complexity (fin lithography/etch, double-gate alignment) would substitute a planar quadrangular gate carrying ONO storage on all four sidewalls — achieving She's physical separation of the four storage sites in a planar, lithographically simpler device. The orthogonal bit-line routing needed to address four sides of a planar gate is the straightforward adaptation of NROM's bidirectional read/program plus a second orthogonal bit-line layer (as the patent itself uses).

Combination C — JP2004-342927 + JP2004-047593 + EP1535336A2 (Infineon NROM-FinFET)

EP1535336A2 teaches a charge-trapping memory layer on side surfaces of a rectangular semiconductor body, with injection edges at the top corners of the side surfaces, localized programming, and word lines self-aligned along the flanks. Combined with Oki's planar transistor (JP2004-342927) and the four-point storage concept (JP2004-047593), the PHOSITA has every structural and functional element: a rectangular gate body, charge-trapping nitride on its side surfaces, four localized storage regions, and the motivation (density, 4-bit operation) to surround all four sides. This combination is somewhat weaker than A because the Infineon device is fin-based, but it reinforces that side-surface nitride charge storage around a rectangular gate body was known.

4. Why a PHOSITA would have been motivated (KSR analysis)

1. Known problem: narrowed cell current windows in 2-bit-per-side cells when opposite-side charge is stored — admitted in the patent's own Background.
2. Known solution space: (i) physical separation of storage sites (She, 2004/2005); (ii) four-point-per-element storage in two orthogonal directions (JP2004-047593); (iii) nitride sidewall charge trapping (NROM, spacer-SONOS, Infineon).
3. Predictable implementation: a conformal ONO deposition + anisotropic etch-back around a rectangular gate necessarily produces an integral sidewall on all four faces — no inventive step is required to arrive at the claimed sidewall geometry. The four partial regions are a direct consequence of the geometry, and per-side hot-electron programming was the standard NROM mechanism.
4. Design incentive: increasing bits per cell (density/cost) was a constant industry driver; 2-bit NROM was already commercial, and 4-bit-per-cell was an express goal in the art (She).
5. No unexpected results shown: the patent's stated benefit — stable windows because opposite-side regions no longer interact — is the same benefit She attributes to physical separation of storage sites. That is a predictable, not surprising, consequence.

5. Secondary considerations / counterarguments (balance)

• No single reference discloses a planar quadrangular gate with an integral ONO sidewall ring providing four independently programmable regions. A patentee would argue that Combination B requires improper modification of a fin device into a planar device, and that Combination A is hindsight reconstruction.
• The 45° word-line geometry, the two-orthogonal-bit-line array, and the damascene/dummy-gate process of the third embodiment are not suggested by the primary references; these likely reside in dependent claims and could survive even if the independent claims fell.
• Unverifiable refs: US20070057318 and US20070075354/US7514738, which map very closely onto the claimed method (implant-with-gate-as-mask → charge-storage body + sidewall → S/D implant), could not be date-verified. If their effective filing dates precede 2006-03-31, they materially strengthen the method-claim obviousness case — this should be checked before finalizing any opinion.
• Prosecution history: the patent was granted over JP2004-047593 and JP2004-342927, which suggests the examiner saw patentable weight in the four-sided integral sidewall combination. A § 103 challenge would therefore need to be grounded in the combination (e.g., She + JP2004-342927, or the two JP refs + NROM), not in any single reference.

6. Bottom line

The independent apparatus claim is vulnerable to a Combination A challenge (JP2004-342927 + JP2004-047593 + Eitan 2000/ONO spacer art): every structural element is either expressly disclosed or an inevitable geometric consequence of applying known spacer and charge-trapping techniques to a known transistor, and the four-bit goal plus the motivation to fix the known window-narrowing problem come directly from the prior art the patent itself cites. The independent method claim is even more vulnerable, since every step is a conventional CMOS/NROM processing sequence once the four-sided storage objective is adopted. The strongest patentee responses are (i) the absence of any single reference teaching the integral four-sided ONO sidewall ring and (ii) the non-obviousness of the specific array/word-line architecture — but those points primarily protect the dependent claims, not the independent ones.

Highest-confidence statement: Under KSR's expansive obviousness standard, a skilled artisan combining JP2004-342927 (2-bit side-charge transistor), JP2004-047593 (4-point storage in two orthogonal directions), and the well-known ONO sidewall-spacer/charge-trapping art (Eitan 2000; spacer-SONOS) would have had a compelling reason to arrive at the claimed device, and I would rate the independent claims' obviousness risk as moderate-to-high, subject to verification of the two date-uncertain references and the unavailable full claim text.