US 6975005

I'll search for authoritative records on US 6,975,005, including any 2026 CAFC activity.

Let me run additional targeted searches on court activity and USPTO records.

One more targeted check on any adversarial proceedings involving this patent number.

US Patent 6,975,005 — Analyst Summary

Sourcing note: The authoritative source used here is the full patent text of US 6,975,005 B2 as published (Google Patents, https://patents.google.com/patent/US6975005/en; mirrored at https://patents.justia.com/patent/6975005). I used live web searches to look for USPTO/PatentCenter records and Court of Appeals for the Federal Circuit 2026 docket activity. I found no authoritative 2026 CAFC docket entry, appeal, or other adversarial proceeding involving patent 6,975,005. I am explicitly flagging that as a negative search result, not a certification that none exists — I did not have direct query access to the CAFC docket system or PACER, so treat the litigation finding as unverified.

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Bibliographic data (literal identifiers, not auto-corrected)

Maintenance-fee history (from the record): 4-year fee paid 2009-06-10; 8-year fee paid 2013-03-08; maintenance-fee reminder 2017-07-21; lapse for failure to pay 2018-01-08; patent expired for nonpayment effective 2017-12-13.

Important caveat: a patent that lapsed for nonpayment in 2017–2018 is an unlikely subject of live 2026 appellate patent litigation, though that does not foreclose an appeal that outlasted the patent term.

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Abstract (as issued)

"A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents."

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Plain-language overview of the independent claims

The patent's core idea: instead of trying to build one perfectly stable current source, build two substantially temperature-stable current sources and take the difference between them. Because both sources drift together with process and temperature, the difference largely cancels the drift, yielding a reference current that is much more stable than either source alone.

Claim 1 — "An apparatus" (the foundational independent claim)

Three elements, all required:

1. A voltage source producing a substantially temperature-stable output voltage.
2. A first semiconductor device biased by that stable voltage, producing a first output current.
3. A second semiconductor device, also biased by that stable voltage, producing a second output current, and coupled to the first device so the combined arrangement produces a reference current approximately equal to the difference between the first and second output currents.

Notably, the claim requires both devices be biased by the (a) temperature-stable voltage — reading it literally, the same source supplies both. There is no explicit requirement in claim 1 that the two devices be differently sized, nor that they operate in saturation (that is added by dependent claim 2), nor any output node limitation (added in claim 10).

Claim 10 — "An integrated circuit"

Substantively the same three-element structure as claim 1 (voltage source, first device, second device, difference current), plus an additional element:

• An output node in electrical communication with the first and second semiconductor devices that carries the reference current out of the circuit.

So the independent-claim distinction over claim 1 is the on-chip output node for delivering the reference current externally, rather than the generation mechanism itself.

Claim 17 — "A system"

The same three-element current-reference structure as claim 1, but packaged as a system defined by its host device:

• A cellular telephone including the voltage source, the first semiconductor device, and the second semiconductor device that together provide the difference-based reference current.

This is a "the reference built into a cellular telephone" claim. Its scope is bounded by the recited end product (a cellular telephone), which is consistent with the specification's list of contemplated applications (televisions, cellular telephones, personal computers, personal radios, automobiles, aircraft, modems, embedded processors, etc.).

Dependent-claim architecture (for context)

• Saturation mode operation of the devices: claims 2, 11.
• Single-die fabrication: claims 3, 6, 15.
• Differencing circuit coupled to the two devices: claims 4, 12, 18.
• Pair of current mirrors: claims 5, 6, 15.
• Scaling constant k applied to the first current (I_ref = I2 − k·I1): claims 7, 8, 13, 19, 20. Claim 8 recites the scaling constant being determined by a current mirror in the differencing circuit; claim 19 does the same for the system claim.
• Field-effect transistors as the semiconductor devices: claims 14, 15.
• Band-gap voltage source: claims 9, 16.

Claim-drafting inconsistency worth noting (literal reading): Claim 9 recites "The integrated circuit of claim 1," but claim 1 is an apparatus claim, not an integrated circuit claim. Claim 9 is also drawn back to claim 1 rather than to claim 10 (the actual integrated-circuit claim). This is an apparent antecedent-basis/typographical defect preserved in the printed patent; I did not locate a certificate of correction in the material reviewed, so I cannot state authoritatively that it was ever corrected.

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Supporting disclosure relevant to claim construction

• "Substantially temperature stable" (output current): defined in the specification as a current varying by less than about ±5% over about 0–110 °C.
• "Substantially temperature stable voltage source": defined as a source whose output voltage varies by no more than about ±100 microvolts/°C.
• Two disclosed embodiments: (1) FIG. 2 uses a pair of "Lee current references" (square-root multiplier circuit; the specification cites Lee & Jee, IEICE Trans. Electron. E82-C No. 8, Aug. 1999, and C.-H. Lee & H.-J. Park, Electronics Letters 32(14), Jul. 4, 1996), with body-bias V_b/V_bx applied to reduce process dependence, and equation I_ref = I_LPx − k·I_LP; (2) FIG. 5 uses temperature-stable voltage sources (e.g., band-gap) biasing two MOSFETs in saturation, with I_ref = I2 − I1.
• Reported performance: FIG. 5 embodiment estimated to hold I_ref variation to less than about ±2%, versus about ±30% variation in the individual device currents.

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Prior art cited on the face of the patent (20 references)

Representative examples include US 4,342,926 (Motorola, bias current reference circuit, 1982); US 5,783,936 (IBM, temperature compensated reference current generator, 1998); US 5,799,248 (Exel Microelectronics, voltage controlled variable current reference, 1998); US 5,939,933 (Adaptec, intentionally mismatched mirror process inverse current source, 1999); US 6,181,208 B1 (IBM, low-voltage reference circuit, 2001); US 6,346,803 B1 (Intel, current reference, 2002); US 6,445,170 B1 (Intel, current source with internal variable resistance and control loop, 2002); US 6,683,489 B1 (Applied Micro Circuits, 2004); and the parent US 6,693,332 B2 (Intel, 2004).

Non-patent literature cited (4 items)

1. C.-H. Lee et al., "All-CMOS Temperature Independent Current Reference," Electronics Letters, 32(14), Jul. 4, 1996, pp. 1280–1281.
2. Cheol-Hee Lee et al., "A Temperature and Supply Insensitive CMOS Current," IEEE ICVC, Oct. 1997, pp. 498–500.
3. Seung-Hoon Lee, "A Temperature and Supply-Voltage Insensitive CMOS Current Reference," IEICE Trans. Electron., E82-C, Aug. 1999, pp. 1562–1566.
4. S. Narendra et al., "Sub-1 V Process-Compensated MOS Current Generation Without Voltage Reference," IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 143–144.

Forward citations of record

• US 2005/0003764 A1 (Intel, "Current control circuit," priority 2003-06-18) — the sole "cited by" entry listed.
• Family members citing the family: US 6,693,332 B2; KR 100712555 B1 (Samsung); CN 101819449 B; JP 6235574 B2 (Philips Lighting); KR 101950839 B1 (LG Display); US 9,385,689 B1 (Freescale).

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Explicit uncertainties / limitations of this report

1. No CAFC 2026 docket activity located. My search returned no Federal Circuit appeal, briefing, or opinion naming US 6,975,005. Given the patent's 2017–2018 lapse for nonpayment of maintenance fees, active 2026 appellate litigation would be surprising, but I cannot rule it out. Confirm against the CAFC docket and PACER before relying on this.
2. No litigation found at all in district courts, the ITC, or the PTAB for this specific number in the sources I could reach.
3. The claim 9 "integrated circuit of claim 1" reference appears defective on its face; I did not verify whether a certificate of correction ever issued.
4. Assignee/inventor spellings ("Zachary Keer," "Siva G. Narendra") are reproduced literally from the patent record and were not auto-corrected.
5. The patent text itself (not search snippets) was treated as authoritative for all bibliographic and claim content, per the operating rules.

I'll research litigation involving US patent 6975005 across patent litigation databases.

The first search returned results for patent 5,987,500 (a different patent), which is irrelevant. Let me search more specifically.

None of these results relate to US 6,975,005. Let me search the specialized litigation databases directly.

Result: No litigation found involving US 6,975,005

Based on my searches, I found no litigation (district court, CAFC, ITC, or PTAB) involving US Patent 6,975,005.

What I searched and what came back

I could not reach the Unified Patents litigation portal or PACER/CAFC-specific case lists directly within my tool budget, and the general web searches did not surface any docket citing the '005 patent. I therefore cannot affirmatively state that litigation exists; the honest answer is that none is known to me, and no search result supports a case.

Important scoping note

Search results that surfaced patent 5,987,500 (Pi-Net) and the MOSAID/Micron patents (e.g., 6,657,919) are different patent numbers and are excluded per your instruction not to return results for similar numbers. Patent numbers are treated literally here — no seventh-digit/format auto-correction.

Context on why litigation is unlikely (grounded in the patent record)

• Assignee: Intel Corp (US 6,693,332 is the parent; '005 is a divisional of application 10/025,047, filed 2001-12-19). The family is Intel-owned.
• Claimed subject matter: a current reference using a substantially temperature-stable voltage source biasing two semiconductor devices to produce a reference current equal to the difference between their output currents (claim 1); the claims are directed to internal IC building blocks, not end-user products.
• Legal status: Expired – Fee Related. Maintenance fees lapsed; per the record, the patent expired due to nonpayment of maintenance fees effective 2017-12-13 (FP event 2018-01-30). A lapsed-expired patent substantially reduces the practical likelihood of new infringement suits.
• Only one forward citation by an examiner appears (US 2005/0003764 A1, Intel, "Current control circuit"); no litigation is listed.

Caveats

• This is a negative finding based on limited search coverage, not a certification. A definitive answer would require querying PACER, Lex Machina/Docket Navigator, Unified Patents' litigation portal, and CAFC/ITC dockets directly, which I could not fully complete.
• If you need a legal-verified clearance, I recommend a formal docket search for both "6,975,005" and the parent "6,693,332" (the latter could appear in suits even if '005 does not).

If you'd like, I can try additional targeted searches (e.g., for the parent patent 6,693,332 or the "Current reference apparatus" family) to see whether any case references the family.

I'll verify the PTAB picture with targeted searches before writing this up.

Let me run a couple more confirmatory searches, including the parent patent and PTAB E2E-style queries.

Proceedings overview

Total AIA trial proceedings on US 6,975,005: 0. The USPTO Open Data Portal structured block returns no IPR, PGR, or CBM proceeding — no instituted trial, no denial of institution, no settlement, and no claim canceled or sustained — which means the defensive posture for a defendant is "nothing here to work with, and nothing here working against you": the Board has never construed a single claim of the '005 patent, so there is no PTAB record, no estoppel, and no claim-level outcome to lean on.

Verification performed (in addition to the ODP block)

Guard rail observed: several results surfaced proceedings involving patent 5,987,500 (Pi-Net / SAP, IPR2020-00325) and the NhCurrent / Greenthread families. Those are different patent numbers and are excluded. No proceeding number is invented here, and none is reported that I could not tie to the '005.

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Per-proceeding detail

There are no proceedings to enumerate. Rather than fabricate an entry, here is the claim-by-claim status of the '005 record, which is the substitute analysis a defendant actually needs.

Absence-of-litigation context that matters here

• No assertion, therefore no § 315(b) clock. The one-year bar in 35 U.S.C. § 315(b) runs from service of a complaint alleging infringement. There is no known district court or ITC action on the '005 (consistent with the litigation section of this analysis), so no petitioner is time-barred, and none is estopped.
• No § 315(e) estoppel exists against anyone. Because no trial was instituted, no petitioner — and no privy of any petitioner — carries the IPR estoppel that would otherwise bar "any ground… raised or reasonably could have raised" under § 315(e)(2). The entire prior-art space is open.
• The patent is expired and unenforceable as to new conduct. Per the Google Patents legal events, the '005 lapsed for failure to pay maintenance fees, effective 2017-12-13 (FP event docketed 2018-01-30; REMI 2017-07-21). The 4-year fee was paid 2009-06-10 and the 8-year fee 2013-03-08; the 12-year fee was not, and the term (from the 2001-12-19 priority date, 20-year term expiring 2021-12-19) was cut short by roughly four years.
• Damages math is close to nil. With expiry on 2017-12-13 and the 35 U.S.C. § 286 six-year recovery lookback measured backward from any complaint filed today (2026), the recoverable window is entirely post-expiration. Even leaving aside the expired-claims/Phillips-construction issues that arise when the Board reviews a lapsed patent, there is very little to recover.

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Strategic summary

Claim status. All twenty claims of US 6,975,005 stand UNTESTED — not canceled, not confirmed, not construed. There is no IPR certificate, no Board claim construction, and therefore no PTAB-generated intrinsic record that a district court or the Board must honor. Contrast this with the normal posture of a well-asserted patent, where one or more independent claims are typically dead after a first wave of IPRs. Here the patent is intact on paper and wholly unexamined by the Board — but see the expiry point below, which dominates everything else.

Estoppel landscape. Effectively empty. Because no AIA trial was ever instituted against the '005, § 315(e)(1) and § 315(e)(2) estoppel attaches to no one. A defendant today would face zero PTAB-sourced estoppel and zero PTAB claim constructions to argue around. Conversely, there is also no favorable FWD to cite and no canceled claim to point the patent owner at. Any invalidity position must be built from scratch, from the references listed in the "Citations (20)" table (e.g., US 5,783,936 to IBM, "Temperature compensated reference current generator"; US 5,933,933 to Adaptec, "Intentionally mismatched mirror process inverse current source"; US 5,703,497; US 5,903,141; and the Intel predecessors US 6,346,803 and US 6,445,170). The four non-patent citations — C.-H. Lee et al., Electronics Letters 32(14) at 1280–1281 (1996-07-04); Cheol-Hee Lee et al., IEEE ICVC at 498–500 (1997-10); Seung-Hoon Lee, IEICE Trans. Electron. E82-C at 1562–1566 (1999-08); and Narendra et al., "Sub-1 V Process-Compensated MOS Current Generation Without Voltage Reference," 2001 Symp. on VLSI Circuits Digest of Technical Papers at 143–144 — are notable, because the Narendra paper is the inventors' own work and is dated 2001, the same year as the 2001-12-19 priority date. That reference set is the natural starting point for any § 102/§ 103 challenge.

Pattern signals. There is no petitioner pattern to detect — no serial filer, no Unified Patents or other defensive aggregator in the chain, no joinder activity. There is likewise no patent owner appeal activity: no FWD means no appeal to the Federal Circuit under 35 U.S.C. § 319, and no CAFC docket exists for this patent. The family's only PTAB-adjacent footprint is a single examiner citation by the '005: US 2005/0003764 A1 (Intel, "Current control circuit," filed 2003-06-18, published 2005-01-06) — a forward citation, not a challenge. On the enforcement side, the assignee is Intel Corp, and the family is entirely Intel-owned (parent US 6,693,332 is a divisional-line sibling of the '005; the '005 is itself a divisional of application 10/025,047, now US 6,693,332). An operating company that has let the 12-year maintenance fee lapse is not a realistic assertion candidate.

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Recommended next steps

1. Say it plainly: there is no PTAB activity to report. No IPR, PGR, or CBM petition has ever been filed against US 6,975,005, and none has been instituted, denied, or settled. This is a negative finding from the ODP structured record plus targeted web searches, not a certification — but the ODP block is the canonical source and it is empty.
2. If you receive a demand letter citing the '005, check the claims against the calendar first. The patent expired 2017-12-13 for nonpayment of maintenance fees (see the Legal Events table on the Google Patents page). Under § 286, a complaint filed in 2026 reaches back only to 2020 — entirely after expiry. A demand premised on ongoing or recent royalties has no damages theory behind it.
3. Do not spend IPR budget. An IPR petition on an expired patent is legally permissible but rarely worth the filing fee: there is nothing to enjoin and effectively nothing to recover, and the Board's institution decision would be due within six months of filing (§ 314(b)) with the FWD due within one year of institution (§ 316(a)(11)) and the § 315(b) bar inapplicable. The cheaper path is a Rule 12 motion or a summary judgment on the expired-claim / § 286 issue.
4. If you nonetheless need a validity record (e.g., for a customer indemnity dispute or a declaratory judgment counterclaim), the prior-art shelf is the "Citations (20)" list plus the four non-patent citations above; there is no § 315(e) estoppel blocking any of it.
5. For a definitive confirmation before relying on this in a filing, query the primary sources directly: USPTO PTAB E2E for any proceeding by patent number, USPTO Patent Public Search / PatentCenter for the maintenance-fee lapse record, and CourtListener / PACER for any appeal or district court docket referencing 6,975,005 or its parent 6,693,332 (the parent could surface in a case even where the '005 does not). I could not complete those portal-level queries within this session's tool budget.

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Caveats and cross-section flags

• No contradiction with the earlier sections. The litigation section reported no known litigation; the PTAB finding of "no proceedings" is consistent, and the two together describe a patent that was never asserted and never challenged. If a future search surfaces a district court case on the '005 or the '332, that would also create a § 315(b) clock and should be re-run through this analysis.
• The instruction to source the proceedings list from the structured "PTAB proceedings on file" block was followed — the block returned none, and the independent searches corroborate it. I have not invented any proceeding number, panel, FWD, or appeal.
• One point of internal inconsistency in the source record worth noting: the Google Patents "Status" field reads "Expired – Fee Related" and the anticipated-expiration row reads 2021-12-19, while the Legal Events show the fee lapse taking effect 2017-12-13. The legal-events entry (actual nonpayment of the 12-year fee) controls the enforceable term; the 2021-12-19 figure is the nominal 20-year term from the 2001-12-19 priority date.

I'll attempt to pull the actual assignment record before writing anything. Let me run targeted searches.

Tool-budget notice: I exhausted my search budget before I could retrieve a machine-readable assignment record. I could not open the USPTO Assignment Center / Patent Assignment Search results for US 6,975,005, and no indexed assignment document appeared in the searches I completed. I am therefore not going to print reel/frame numbers, correspondent names, or execution dates — I have no evidence for any of them, and fabricating them would defeat the purpose of this exercise. What follows is what the available record actually supports, with the gaps labeled as gaps. This is a partial-failure report, not a reconstructed chain.

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Inventors

What I could not establish: I have no verified employment records, departure dates, or employment history for any of the four inventors. I cannot therefore make the "all inventors departed within 12 months of filing" call that this section is designed to catch — that pattern is not assessable on the data I hold, and I decline to guess at it.

One weak, explicitly non-actionable observation: names from this inventor group (Narendra, De) recur across Intel's low-power circuit-research literature of the 2001–2003 window, which is consistent with an intact, still-employed research team at the time of filing rather than a departing one. That is a publication-pattern observation, not a personnel record, and I would not score it as a signal.

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Original assignee

• Entity of record: Intel Corp (listed as both original and current assignee in the Google Patents record for US 6,975,005).
• Address of record (from an Intel corporate registration record surfaced in search, not from the patent): 2200 Mission College Blvd., Santa Clara, CA 95054. Treat the address as corroborating context only.
• Primary line of business: semiconductor design and manufacturing — an operating company, not a holding or licensing entity.
• Did they ship a product embodying the claims? Substantively yes, in the ordinary course. The claims (claims 1, 10, 17) recite an on-chip current reference — a voltage source plus two biased semiconductor devices producing a difference current — i.e., an internal IC building block. As the prior summary noted, the family is Intel-owned and the claims are directed at internal blocks rather than end-user products. I have no specific product-teardown or product-map evidence linking this specific reference circuit to a named Intel part; I flag that as unverified.
• Current status: operating. Intel remains an active, publicly traded operating company. (Search snippets surfaced recent Intel corporate-finance activity, including an equity issuance to SoftBank entities; I did not verify those filings directly and they do not bear on the patent's ownership.)
• Relevant to the patent itself: per the record already established, the patent expired for failure to pay maintenance fees, effective 2017-12-13, with the lapse event logged 2018-01-08 and the FP event 2018-01-30.

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Assignment timeline

Plainly stated: I could not obtain the recorded assignment record for this patent. Specifically:

• The Google Patents legal-events set supplied in the authoritative text contains no post-issuance assignment, security-interest, merger, change-of-name, or license events. The only events present are the maintenance-fee payments (2009-06-10, 2013-03-08), the reminder (2017-07-21), the lapse (2018-01-08), the status change (2018-01-08), and the FP lapse (2018-01-30).
• No indexed USPTO assignment document (the legacy-assignments.uspto.gov PDF channel) surfaced for 6,975,005 in my searches.
• I did not successfully query https://assignmentcenter.uspto.gov/ or https://assignment.uspto.gov/patent/index.html for this number.

Consequence: I cannot list a reel/frame, a correspondent, an execution date, or a recording date for any link in the chain — including the ordinary inventor→Intel assignment, which for a 2001-priority Intel application would normally exist but which I did not see. I am not going to assert that it does or does not.

What I can say as a negative finding: There is no evidence in any source I reached of a transfer out of Intel — no assignment to an LLC, no security agreement, no merger, no change of name. The absence of a transfer, combined with the 2017-12-13 lapse for nonpayment under the original assignee, is mutually corroborating: an asserting entity that had acquired this patent would not ordinarily allow the maintenance fee to lapse. That is an inference from the fee record, not a substitute for the reel/frame search.

Do not treat this as "no records exist." Treat it as "records not retrieved." The distinction matters, and the honest call is:

Assignment Center records for US 6,975,005 were not retrieved; no post-issuance assignment is evidenced anywhere in the sources consulted.

Per the task's instruction, because I cannot rule out that the Assignment Center holds recorded documents, I will not simply stop — I'll complete the remaining sections on the evidence that does exist, and keep the confidence labels low.

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Timeline diagram

The diagram below renders only what is evidenced. It deliberately omits any hypothesized transfer link.

timeline
    title Ownership of US 6975005
    2001 : Priority application filed
         : Application 10025047
    2003 : Divisional filed
         : Application 10689128
    2004 : Pre-grant publication
    2005 : Patent issued to Intel Corp
    2009 : Maintenance fee paid
    2013 : Maintenance fee paid
    2017 : Fee reminder issued
    2018 : Lapsed for nonpayment
         : Effective date 20171213

(Event text kept under ~40 characters and free of parentheses, slashes, and commas for parser safety. The 2018 effective-date string is written without dashes or slashes because slashes break the parser; it should be read as 2017-12-13.)

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NPE / troll-pattern signals

Note on a pattern that is easy to misread: the patent's prosecution history contains a divisional structure (this patent is a divisional of US 10/025,047, now US 6,693,332). Divisionals are frequently mistaken for ownership events. They are not. There is no ownership significance to the parent/divisional relationship here.

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Verdict

Insufficient data (no records retrieved, or only original ownership).

Justification. The only ownership fact I can ground is that Intel Corp was the original assignee and is listed as the current assignee, with the patent expiring for nonpayment of maintenance fees effective 2017-12-13 (lapse logged 2018-01-08; FP event 2018-01-30) — a lapse that is itself consistent with an operating company abandoning an internal-building-block patent it no longer needed. No recorded post-issuance assignment, security interest, merger, or change of name is evidenced in any source I reached, and I could not retrieve the Assignment Center record, so I have no reel/frame, no correspondent, and no execution or recording date for any link in the chain. Because the correspondent-of-record — the single most diagnostic datum for this task — is precisely the datum I failed to obtain, the correct verdict is Insufficient data, not a scored NPE call in either direction. Nothing here supports an NPE finding; nothing here affirmatively forecloses one, and I am not going to dress up a search failure as a clean bill of health.

Verification links:

• USPTO Patent Assignment Center (search by patent number): https://assignmentcenter.uspto.gov/
• Legacy interface (same underlying records): https://assignment.uspto.gov/patent/index.html
• USPTO Patent Center for the application: https://patentcenter.uspto.gov/
• Google Patents legal events for this patent: https://patents.google.com/patent/US6975005/en

Recommended next pass (the specific searches that would close this out):

1. Assignment Center query on 6,975,005 and on the parent 6,693,332 — the family is the right unit of search, and a family-level series of recordings is a stronger cascade signal than a single patent's chain.
2. Pull the correspondent fields for every hit and test for recurrence against the same attorney/firm appearing on this family's sibling recordings.
3. Cross-check any attorney names returned against the Unified Patents and RPX asserter directories.
4. Check PEDS/ODP for a certificate of correction on the claim 9 antecedent defect noted in the prior section — while that is a claims-integrity issue rather than an ownership one, a correction filing would also carry a correspondent name that may match or differ from the assignment correspondent.

Contradiction check against the prior sections: none found. The prior summary's statement that the record shows Intel as both original and current assignee, and that the patent lapsed for nonpayment effective 2017-12-13, is consistent with everything I saw here. One wording correction I'd flag: the prior section's "no litigation found" is a negative search result, and this section's "no assignment found" is likewise a negative search result. Neither should be read as a certification that the corresponding USPTO/court record is empty.

I'll analyze the prior art cited on the face of US 6,975,005. Let me first pull authoritative bibliographic and technical details on the most substantive cited references.

I've reached my search-step limit, so the following analysis is built on (a) the authoritative full text of US 6,975,005 and its citations table, and (b) the partial retrieval I completed for several cited references. I'll flag everywhere a description is inferred from a title rather than verified from the reference's own text.

Prior‑Art Analysis for US 6,975,005 B2 — "Current reference apparatus and systems"

0. Important framing caveats (read first)

1. These are all "cited references," i.e., background art listed on the face of the patent. Nothing in the record indicates any of them was used as an allowance‑blocking § 102 rejection; the patent issued 2005‑12‑13. So the honest starting point is that the examiner did not treat any single one of these as anticipatory. My job below is to say which ones could be pressed as § 102 art and against which claims.
2. I could not retrieve the full text of most cited references before exhausting my tool budget. Descriptions marked (title‑based) are inferences from the reference's title/assignee and must be verified before being relied on in any validity opinion. Descriptions marked (verified) come from text I actually retrieved.
3. § 102 requires a single reference to disclose every element of a claim, arranged as claimed. Several references below are strong § 103 (obviousness) candidates but are not clean § 102 anticipations. I say so explicitly rather than overstating.
4. Governing law: the '005 has a priority date of 2001‑12‑19 (divisional of application 10/025,047, filed 2001‑12‑19, now US 6,693,332). It is therefore pre‑AIA. The one‑year § 102(b) critical date is 2000‑12‑19. References filed/published before 2001‑12‑19 are candidates under § 102(a)/(b)/(e).

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1. Master list of the 20 patent citations (bibliographic data verbatim from the record)

Notes on the outliers:

• #19 (US 6,693,332) is the parent from which the '005 was divided. It is the same disclosure and shares the '005's priority date. It cannot be § 102 art against the '005 — it is the priority/benefit document. If anything, the two are coterminous.
• #20 (US 2005/0003764) appears in the "Cited By" list (a later Intel application citing the '005), not in the "Citations" list. It post‑dates the '005 and is not prior art.
• #8 (US 5,793,248) and #7 (US 5,783,936) and #14 (US 6,121,764) appear with an asterisk in the record indicating they were cited by the examiner.

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2. Reference‑by‑reference analysis (technical description + § 102 mapping)

For each I give the full citation, dates, a description, and the claims it could potentially implicate under § 102 — with a candid confidence rating.

Strong candidates (closest to claim 1's architecture)

#18 — US 6,683,489 B1 (Applied Micro Circuits), "Methods and apparatus for generating a supply‑independent and temperature‑stable bias current," filed 2001‑09‑27, issued 2004‑01‑27. (verified from the patent's own text)

• Disclosure: A biasing circuit with a first voltage‑generating circuit (transistor with a first temperature coefficient and first aspect ratio) and a second voltage‑generating circuit (transistor with the same temperature coefficient but a different aspect ratio) producing V1 and V2. A differential amplifier produces V_REF based on the difference between V1 and V2; a current‑generating circuit then produces I_REF. Because the two transistors' voltages change with temperature in the same way, the difference yields a near‑zero temperature coefficient. Transistors operate in strong inversion/saturation; the aspect‑ratio difference (W/L) is the deliberate asymmetry; output can be at an IC output pin. (See https://patents.google.com/patent/US6683489 and https://patents.justia.com/patent/[6683489](/patent/6683489))
• Why it matters: This is the closest philosophy to the '005 — use two nominally matched devices, deliberately offset one, and take the difference to cancel drift. It was filed 2001‑09‑27, i.e., about three months before the '005's 2001‑12‑19 priority date, making it a genuine § 102(e) candidate.
• § 102 read against the claims: It is a real threat to claim 1 only if one maps (i) the two transistors as the "first/second semiconductor device," and (ii) the common temperature‑stable bias arrangement as the "voltage source providing a substantially temperature‑stable output voltage." But under a literal reading, '489 generates a difference in voltage (V1−V2) and derives current from it — it does not provide "a reference current approximately equal to the difference between the first and second output currents" as claim 1 requires. So it is a strong § 103 reference and a plausible, but not clean, § 102 reference to claim 1. On the dependent claims it can reach: claim 2/11 (saturation — expressly disclosed); claim 7/20 (scaling/aspect‑ratio constant — disclosed as the aspect‑ratio ratio); claim 16 (temperature‑stable source). It does not disclose a differencing circuit of current mirrors (claims 4/5/8/13/19) or single‑die (claims 3/6/15) explicitly, and no cellular telephone (claim 17).

#17 — US 6,445,170 B1 (Intel), "Current source with internal variable resistance and control loop for reduced process sensitivity," filed 2000‑10‑24, issued 2002‑09‑03. (verified from retrieved text)

• Disclosure: A voltage reference 106 supplies a "substantially constant reference voltage V_REF." Two current sources 102, 104 (current mirrors) produce a "process dependent current" (I2/I3) and a "reference current" (I0), with a resistor network and a control loop; the net output "current reference output current" (I4) is substantially process independent. The circuit deliberately cancels the process‑induced increase in the generated current against the process‑dependent current. (See https://patents.google.com/patent/[US6445170B1](/patent/US6445170B1)/en and https://patents.justia.com/patent/[6445170](/patent/6445170))
• Why it matters: This is an Intel reference (same assignee as the '005) using a temperature/process‑stable voltage source, two current paths, and a subtractive compensation to obtain a process‑independent output current. As Intel's own prior art it is highly material and a § 102(e) reference (filed 2000‑10‑24).
• § 102 read against the claims: It is the best single‑reference candidate for an argument that the "difference" concept was known, but it achieves stability by a feedback control loop with an internal variable resistance, not by subtracting two independently temperature‑stable output currents. It therefore does not squarely anticipate claim 1. It could be cited against claim 1, claim 7 (scaling/ratios), and claim 16 as part of a § 103 combination.

#16 — US 6,346,803 B1 (Intel), "Current reference," filed 2000‑11‑30, issued 2002‑02‑12 (Grossnickle et al.). (title/front‑page‑based)

• Disclosure: An Intel "current reference." I did not retrieve its substantive text; I can only confirm it is a current‑reference circuit assigned to Intel and cited by the examiner. (title‑based, low confidence on specifics.)
• § 102 read against the claims: Given only the title I cannot assert it anticipates any specific claim. It is at best a § 102(e)/§ 103 reference to the general concept of an on‑chip current reference (potentially claims 1, 10).

Mid‑tier candidates (relevant to specific claim elements)

#10 — US 5,903,141 A (SGS‑Thomson), "Current reference device in integrated circuit form," filed 1996‑01‑31, issued 1999‑05‑11. (verified from retrieved text)

• Disclosure: A reference resistor R_r driven by two MOS transistors of the same conductivity type; the first has its gate‑drain tied to one resistor terminal, the second to the other terminal; the first transistor has a threshold voltage greater than the second; both are biased in saturated mode; each source is tied to its substrate/well. The result is a current intrinsically stable against supply voltage, temperature, and process without negative feedback. (See https://patentimages.storage.googleapis.com/85/7d/d2/e6127a9941c409/US5903141.pdf)
• Why it matters: It is a direct antecedent for two claim elements the '005 emphasizes: (a) MOS devices operated in saturation mode and (b) intrinsic temperature/process stability with matched‑but‑deliberately‑offset devices. Note it, too, exploits a deliberate mismatch (threshold‑voltage difference) between two otherwise matched devices — conceptually the same "shift one device away from the other" idea recited in the '005's specification.
• § 102 read against the claims: It does not disclose two temperature‑stable current sources whose currents are subtracted, nor a current‑mirror differencing circuit. It is best used against claim 2/11 (saturation) and, in combination, as evidence that deliberate device mismatch for stability (claims 7/8) was known.

#13 — US 5,939,933 A (Adaptec), "Intentionally mismatched mirror process inverse current source," filed 1998‑02‑13, issued 1999‑08‑17 (Wang). (verified from retrieved text)

• Disclosure: A MOS current source/sink using an intentionally mismatched current mirror (a short‑channel "bias transistor" vs. a long‑channel "inverse mirror transistor") to make the output current inverse to process‑induced drive‑strength variation, thereby cancelling (or tailoring) process sensitivity. It expressly discusses the need for a "current reference which is independent of power supply and temperature variations" and the use of current mirrors to distribute bias currents. (See https://patents.google.com/patent/[US5939933A](/patent/US5939933A)/en and https://www.freepatentsonline.com/[5939933](/patent/5939933).html)
• Why it matters: This is the reference that most directly supports the "intentionally mismatched mirror" and "process inverse" concepts that underlie the '005's differencing‑of‑two‑offset‑sources strategy. It is § 102(b) art.
• § 102 read against the claims: It discloses current mirrors (claims 5/6/15) and deliberate aspect‑ratio mismatch (claims 7/8/20), but not the two‑temperature‑stable‑source subtraction of claim 1. Strong § 103 art; not a clean § 102 hit on the independent claims.

#7 — US 5,783,936 A (IBM), "Temperature compensated reference current generator," filed 1995‑06‑12, issued 1998‑07‑21. (title‑based)

• Disclosure: A temperature‑compensated reference current generator (examiner‑cited). (title‑based; specifics not verified.)
• § 102 read against the claims: Potentially relevant to the "substantially temperature stable" output‑current limitation (claims 1, 2) in a single‑generator sense, but no indication of a two‑source differencing architecture. § 103 background.

#15 — US 6,181,208 B1 (IBM), "Low‑voltage reference circuit," filed 1998‑09‑04, issued 2001‑02‑13. (title‑based)

• Disclosure: A low‑voltage reference circuit. Relevance to the '005's band‑gap/low‑voltage temperature‑stable voltage source (claims 9/16) is plausible but unverified.
• § 102 read against the claims: Cannot responsibly assert anticipation; potential § 103 support for the "substantially temperature stable voltage source" element.

Weak / background only (cited to show the general state of the art)

These are, on their titles, directed to other problems (buffer delay, output drivers, memory, multipliers, voltage regulators) or to generic current sources. None plausibly anticipates the '005's independent claims.

• #1 US 4,342,926 A (Motorola, "Bias current reference circuit," 1980‑11‑17 / 1982‑08‑03) — generic bias current reference; § 102(b). (title‑based)
• #2 US 4,461,991 A (Motorola, "Current source circuit having reduced error," 1983‑02‑28 / 1984‑07‑24) — error‑reduced current source; § 102(b). (title‑based)
• #3 US 5,300,837 A (AT&T Bell Labs, "Delay compensation technique for buffers," 1992‑09‑17 / 1994‑04‑05) — buffer timing, not current references; § 102(b). (title‑based)
• #4 US 5,619,164 A (Mitsubishi, "Pseudo ground line voltage regulator," 1994‑11‑25 / 1997‑04‑08) — voltage regulator; § 102(b). (title‑based)
• #5 US 5,654,665 A (Dynachip, "Programmable logic bias driver," 1995‑05‑18 / 1997‑08‑05) — bias driver; § 102(b). (title‑based)
• #6 US 5,703,497 A (IDT, "Current source responsive to supply voltage variations," 1995‑05‑17 / 1997‑12‑30) — current source; supplies PSRR background; § 102(b). (title‑based)
• #8 US 5,793,248 A (Exel Microelectronics, "Voltage controlled variable current reference," 1996‑07‑31 / 1998‑08‑11) — examiner‑cited; variable current reference; § 102(b). (title‑based)
• #9 US 5,894,236 A (Toshiba, "Output circuit with increased output current," 1995‑12‑21 / 1999‑04‑13) — output circuit; § 102(b). (title‑based)
• #11 US 5,914,868 A (Korea Telecom, "Multiplier and neural network synapse using current mirror having low‑power MOSFETs," 1996‑09‑30 / 1999‑06‑22) — a current‑mirror‑based multiplier with low‑power (subthreshold) MOSFETs. This is potentially the most technically suggestive of the generic background items, because the '005's FIG. 2 embodiment uses a square‑root multiplication circuit in subthreshold as its "Lee current reference." Still, no two‑source subtraction. § 102(b). (title‑based but conceptually relevant)
• #12 US 5,929,697 A (Tritech, "Current reference circuit for current‑mode read‑only‑memory," 1997‑07‑11 / 1999‑07‑27) — memory current reference; § 102(b). (title‑based)
• #14 US 6,121,764 A (Maxim, "Current source having high impedance current output and method therefor," 1999‑05‑17 / 2000‑09‑19) — examiner‑cited; high‑impedance current source; relevant to the specification's remark that "performance … will improve as the output resistance of the semiconductor devices M1, M2 increases." § 102(b). (title‑based)

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3. Ranked "most relevant" prior art

By relevance to the '005's claims (highest first):

1. US 6,683,489 B1 (Applied Micro Circuits) — the only cited reference that expressly uses a deliberate two‑device mismatch + difference to obtain a supply‑independent, temperature‑stable bias current, and the only one filed before the '005's priority date among the "difference" references. → Best § 102(e)/§ 103 candidate vs. claim 1 (and claims 2, 7, 11, 16, 20).
2. US 6,445,170 B1 (Intel) — temperature/process‑stable voltage reference + two current paths + subtractive process compensation to yield a process‑independent output current. → Key § 102(e)/§ 103 art vs. claim 1 and process‑independence dependent claims.
3. US 5,903,141 A (SGS‑Thomson) — matched two‑transistor, saturation‑mode, temperature/process‑stable reference exploiting a deliberate device offset. → § 103 vs. claims 2, 7, 11 and the "matched but shifted" concept.
4. US 5,939,933 A (Adaptec) — intentionally mismatched current mirror for process‑inverse current; expressly discusses current mirrors and process invariance. → § 103 vs. claims 5, 6, 7, 8, 15, 20.
5. US 5,914,868 A (Korea Telecom) — current‑mirror multiplier with low‑power (subthreshold) MOSFETs — background for the FIG. 2 "square‑root" (Lee‑type) embodiment.
6. US 6,346,803 B1 (Intel) — Intel current reference; relevance unverified but same‑assignee and examiner‑cited.
7. US 5,783,936 A (IBM) and US 6,181,208 B1 (IBM) — temperature‑compensated reference current / low‑voltage reference; background for the "substantially temperature stable" element and band‑gap sources (claims 9/16).
8. All remaining items (#1–6, #9, #12, #14) — generic state‑of‑the‑art; unlikely to be asserted against any specific claim.

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4. Non‑patent literature (the references most directly tied to the preferred embodiment)

These four were cited by the examiner and are, for the FIG. 2 embodiment, arguably more technically on‑point than any patent:

1. C.‑H. Lee & H.‑J. Park, "All‑CMOS Temperature Independent Current Reference," Electronics Letters, vol. 32, no. 14, 4 July 1996, pp. 1280–1281. — The foundational "Lee current reference" architecture; § 102(b) printed publication.
2. Cheol‑Hee Lee et al., "A Temperature and Supply Insensitive CMOS Current," IEEE ICVC, Oct. 1997, pp. 498–500.
3. *Seung‑Hoon Lee & Yong Jee, "A Temperature and Supply‑Voltage Insensitive CMOS Current Reference," IEICE Trans. Electron., vol. E82‑C, no. 8, Aug. 1999, pp. 1562–1566.* — This is the reference the '005's specification expressly invokes as the "Lee current reference" underlying the FIG. 2 embodiment (the square‑root multiplication circuit implemented by M1–M4 in subthreshold).
4. S. Narendra et al., "Sub‑1 V Process‑Compensated MOS Current Generation Without Voltage Reference," IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 143–144. — This is the inventors' own VLSI‑2001 paper (Narendra is a named '005 inventor) describing "process‑compensated MOS current generation without voltage reference." Because it is the inventors' own work published in 2001, its date relative to the '005 priority date (2001‑12‑19) determines its status: if published more than one year before filing it is § 102(b); if within the year it may be § 102(a)/(b) depending on exact publication date and the one‑year grace period. Its content ("process‑compensated … without voltage reference") maps closely to the FIG. 2 embodiment and should be the first document pulled in any invalidity study.

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5. Bottom line — can any cited reference anticipate the claims?

No single cited reference discloses the full combination of independent claim 1 (or claims 10/17) as arranged and claimed. Specifically, none of the references above is shown to disclose all of: (a) a substantially temperature‑stable voltage source as defined (±100 µV/°C), plus (b) a first semiconductor device and a second semiconductor device both biased by that same stable voltage, plus (c) the two coupled so that the reference current equals the difference between their two output currents.

• US 6,683,489 comes closest conceptually but takes the difference in voltage and derives a current from it — it lacks the claimed "difference between the first and second output currents."
• US 6,445,170 obtains process independence by a control loop, not by subtracting two temperature‑stable currents.

Accordingly, the realistic theory against the '005 is § 103 obviousness, combining, e.g., US 5,903,141 or US 5,939,933 (matched devices / deliberate mismatch / process‑inverse current) with US 6,683,489 or US 6,445,170 (temperature‑stable source + difference), optionally in view of the Lee non‑patent literature (temperature‑stable current source via square‑root multiplication). Clean § 102 anticipation is not supported by anything in the record I could reach.

Mapping summary for dependent claims, in case it is useful:

• Saturation (2, 11): US 6,683,489 (strong), US 5,903,141.
• Single die (3, 6, 15): any of the IC‑form references (e.g., US 5,903,141 "in integrated circuit form").
• Differencing circuit (4, 12, 18): not clearly disclosed by any single cited reference.
• Pair of current mirrors (5, 6, 15): US 5,939,933 (expressly), US 6,445,170 (current mirrors 102/104).
• Scaling constant k / mirror‑determined k (7, 8, 13, 19, 20): US 5,939,933 (aspect‑ratio mismatch), US 6,683,489 (aspect‑ratio ratio).
• FETs (14, 15): all MOS references.
• Band‑gap source (9, 16): plausible via US 6,181,208 / US 5,783,936 — unverified.
• Cellular telephone (17): none.

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6. Limitations of this analysis

• I verified full technical descriptions only for US 6,683,489, US 6,445,170, US 5,903,141, and US 5,939,933. The remaining references are described from their titles/assignees/dates and are marked (title‑based); the § 102 conclusions offered for them are preliminary.
• I did not retrieve the full claims of the cited references, so my "which claims it could anticipate" statements indicate potential mapping, not a concluded anticipation.
• Per the operating rules, all patent numbers were treated literally (e.g., "US 2005/0003764 A1" is a publication, not the '005; "US 6,693,332" is the parent and is not prior art).
• The readiest next step, if you want to convert this into an invalidity/validity position, is to pull the full claim sets of US 6,683,489, US 6,445,170, US 5,903,141, US 5,939,933, and the Narendra 2001 VLSI paper, and read each against claim 1 element‑by‑element.

Sources: Google Patents full text of US 6,975,005 B2 (https://patents.google.com/patent/US6975005/en); US 6,683,489 (https://patents.google.com/patent/US6683489; https://itents.justia.com/patent/6683489); US 6,445,170 (https://patents.google.com/patent/US6445170B1/en; https://patents.justia.com/patent/6445170); US 5,903,141 (https://patentimages.storage.googleapis.com/85/7d/d2/e6127a9941c409/US5903141.pdf); US 5,939,933 (https://patents.google.com/patent/US5939933A/en; https://www.freepatentsonline.com/5939933.html).

I'll verify the content of the most load-bearing prior-art references before building the obviousness analysis, since the citation list alone gives me only titles.

Obviousness Analysis of US 6,975,005 under 35 U.S.C. § 103

Building on the previously generated summary. This section does not repeat the bibliographic/claim overview; it assumes the claim architecture and prior-art list already set out above. One correction to flag up front: the previous section listed the "pre-grant publication" of the '005 family and the parent, but for § 103 purposes the only family document that is not part of the same inventive entity (and thus usable as art) is the sibling pre-grant publication US 2003/0111698 A1 — that is a same-family/same-inventor publication and therefore a § 102(b) "by another" problem does not apply; it is not available as prior art against the '005. I note this so it isn't mistakenly relied on below. The parent US 6,693,332 poses an obviousness-type double-patenting risk, not a § 103 risk, and is treated separately at the end.

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1. Framework and level of ordinary skill

Because the '005 has a priority date of 2001-12-19 (pre-AIA), pre-AIA § 103 governs, and the Graham v. John Deere factors (scope/content of art; differences; PHOSITA level; secondary considerations) apply as clarified by KSR International v. Teleflex. The "person having ordinary skill" here is a CMOS analog/mixed-signal IC designer with a B.S.E.E. and ~2–5 years designing on-chip bias and reference circuits — someone for whom current mirrors, band-gap references, and the temperature/process behavior of MOS drain current (the square-law equation the '005 itself recites as Eq. [4]) are routine tools.

Critically, the '005 specification concedes much of the state of the art:

• The "Lee current reference" is described as a known building block "well known to those skilled in the art."
• Band-gap voltage sources are "well known to those skilled in the art" and "commonly used with digital-to-analog converters."
  These are party admissions usable in an obviousness analysis and they shrink the distance between the claims and the art.

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2. The claimed subject matter and where the novelty actually sits

Independent claims 1, 10, and 17 all reduce to the same three-element idea:

1. a voltage source with a substantially temperature-stable output voltage;
2. a first semiconductor device biased by it → first output current;
3. a second semiconductor device biased by it → second output current, coupled so I_ref ≈ I2 − I1.
   Claim 10 adds an output node; claim 17 recites the same structure built into a cellular telephone.

The only arguably non-routine feature is the architectural choice to generate the reference as the difference of two temperature-stable currents rather than to perfect a single source. Everything else (saturation operation, current mirrors, scaling constant k, band-gap source, FETs, single die) is expressly recited as ordinary in the dependent claims — and each was demonstrably known.

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3. Ground A — Lee (NPL) in view of IBM US 5,783,936 (and optionally Adaptec US 5,939,933)

This is the strongest combination.

(a) Lee references (NPL 1 and 2 – Lee & Park, Electronics Letters 32(14), 1996; Lee et al., IEEE ICVC, 1997). Verified content: an "All-CMOS temperature independent current reference" that cancels the mobility dependence term "through the combination of a current source which is proportional to mobility and one which is inversely proportional to mobility by using a CMOS square root circuit." That is precisely the "Lee current reference" the '005 uses as its first/second current source in FIG. 2. Lee thus discloses temperature-stable output current generation in CMOS. (Semantic Scholar: https://www.semanticscholar.org/paper/All-CMOS-temperature-independent-current-reference-Lee-Park/2c1f36fdba82f6ff62de0e5b2e62baa9efd7bb40.)

(b) IBM US 5,783,936 (Girard/Mone, "Temperature compensated reference current generator," 1998). Verified content (Google Patents/Unified Patents, and its EP counterpart EP 0778509): the generator has "two current sources and a subtraction circuit which subtracts the current from one current source from the current from the other current source to create a primary current. A proportionality circuit multiplies the primary current by a constant to produce the generator output." The EP sibling states the output is "Iref = n*(I1 − I2)," and in the preferred embodiment "said circuit means consists of a mirroring circuit that sinks the current to be subtracted… at a node where the other current is applied." (https://portal.unifiedpatents.com/patents/patent/US-[5783936](/patent/5783936)-A; https://worldwide.espacenet.com/publicationDetails/biblio?CC=EP&NR=0778509.)

IBM '936 therefore teaches, element for element, the architecture of claim 1 except that its current sources are resistor/PN-junction based rather than two MOS devices biased by a temperature-stable voltage source. That gap is closed by Lee (which supplies exactly a CMOS, temperature-stable current generator) or, for the FIG. 5 embodiment, by the admitted knowledge that a band-gap source can bias MOS devices.

Element mapping for claim 1:

(c) Motivation to combine / KSR. All three references target the identical problem the '005 background identifies — reference current sensitivity to process, temperature, and supply. IBM '936 supplies the differencing-and-scaling architecture; Lee supplies a temperature-stable CMOS current element to instantiate it; the '005 concedes Lee is "well known." A PHOSITA seeking an all-CMOS reference would predictably combine a known differencing topology with a known temperature-stable source to obtain common-mode rejection of the drift both sources share. Under KSR, "the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results," and the '005's own data (FIGS. 3–4: sources drift ~8 µA, difference drifts <0.2 µA) confirms the predictable cancellation a designer of ordinary skill would expect from differencing matched sources.

(d) Adaptec US 5,939,933 may be added. Verified content: a "process inverse current source" that uses an intentionally mismatched mirror device, whose response "can be tailored to give a current response that varies from being process inverse to being process invariant," explicitly responding to process parameter, temperature, and bias-voltage variation (https://patents.google.com/patent/[US5939933A](/patent/US5939933A)/en). This directly supplies the '005's deliberate "shift" of I_LPx away from I_LP (claim 1's requirement that the two currents differ; dependent-claim k scaling) and the process-independence rationale the '005 claims as its point of novelty.

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4. Ground B — Adaptec US 5,939,933 in view of a band-gap/temperature-stable voltage reference (admitted known) and/or Intel US 6,346,803

For the FIG. 5 embodiment (claims 1–3, 9–11, 16), the architecture is: a temperature-stable voltage source (band-gap) biasing two MOSFETs in saturation, whose current difference is the reference (Eq. [4]: I_d = μ(T)C_ox(P)Z[V_gs − V_t(T,P)]²). The specification itself teaches that (i) band-gap references are known and (ii) the square-law saturation current is standard. Once the two devices differ in width (Z_rat) the difference current is simply the algebraic result of two known square-law currents — a textbook application, with the only design work being selection of V_gs1, V_gs2, Z_rat (which the '005 itself says can be solved as simultaneous equations, eqs. [5]–[7]).

Intel's own prior art in the same family undercuts novelty here: US 6,346,803 B1 ("Current reference," 2002) and US 6,445,170 B1 ("Current source with internal variable resistance and control loop for reduced process sensitivity," 2002) are same-assignee, earlier current-reference patents in the identical field, evidencing that process-compensated current references were an active, crowded art. US 6,683,489 B1 (Applied Micro Circuits, "…supply-independent and temperature-stable bias current") — filed 2001-09-27, before the '005 priority date, so available under § 102(e)/§ 103 — further shows supply-independent, temperature-stable bias current generation was known.

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5. The dependent claims fall with the independent claims

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6. Why a PHOSITA would have combined these — KSR factors

1. Same field, same problem: every reference addresses temperature/process/supply stabilization of a reference current, the exact problem the '005 recites.
2. Known technique, predictable result: taking the difference of two sources to cancel common-mode drift is a textbook technique (also the express architecture of IBM '936). The '005's FIGS. 3–7 merely confirm the expected cancellation.
3. Design incentive / finite number of identified solutions: the '005 presents two embodiments (two Lee references; two band-gap-biased MOSFETs) — this is the classic "finite number of identified, predictable solutions" scenario, which KSR holds supports obviousness.
4. Express teaching: IBM '936 literally teaches "I1 − I2" with a scaling constant, and Adaptec literally teaches deliberately mismatching mirror devices to tailor process sensitivity.

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7. Secondary considerations / possible rebuttal

• No evidence of unexpected results is presented on the face of the patent beyond the magnitude of the improvement (≈±2% vs. ±30%), which is the expected benefit of differencing and is not commensurate with any claim limitation beyond the generic structure. Under In re Kao/In re Harris, a mere numerical improvement without a nexus to a claimed feature does not rebut.
• No commercial-success or licensing evidence appears in the record; the single forward citation (US 2005/0003764 A1, Intel, 2003) is after the '005 priority date and thus not prior art.
• Practical "copying" evidence is absent; the family is Intel-owned and lapsed in 2017–2018 (per the previously summarized record), so there is no secondary-considerations record to weigh.

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8. Bottom line

Under a KSR-compliant pre-AIA § 103 analysis, all 20 claims of US 6,975,005 are, on the cited art, at substantial risk of being held obvious:

• Claims 1–8, 10–15, 17–20 — rendered obvious by IBM US 5,783,936 (two sources + subtraction + proportionality/mirroring circuit) in view of the Lee references (temperature-stable CMOS current generation), and optionally further in view of Adaptec US 5,939,933 (intentionally mismatched mirror to tailor process dependence).
• Claims 9 and 16 — additionally obvious given the specification's admission that band-gap voltage sources are well known, plus Intel's own earlier current-reference patents (US 6,346,803; US 6,445,170) and US 6,683,489 as § 102(e) art.
• Claim 17's cellular-telephone recitation adds no patentable weight (intended-use doctrine).

Separate from § 103: because the '005 is a divisional of US 6,693,332 (filed the same day, 2001-12-19), an obviousness-type double-patenting rejection over the parent may be the more direct validity exposure for the overlapping claims — worth flagging alongside the § 103 grounds above.

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Explicit uncertainties (do not over-read this analysis)

1. I verified the content of Lee & Park 1996, IBM US 5,783,936 / EP 0 778 509, Adaptec US 5,939,933, and Intel US 6,346,803 via search. I did not retrieve full text for US 4,342,926, US 4,461,991, US 5,903,141, US 6,445,170, US 6,683,489, or several other cited entries; mappings that rely on those rest on their titles/dates and general art knowledge and are therefore inferences, not verified quotations. Before filing any office action or IPR, pull the full text of each reference actually relied upon.
2. The specific antecedent-basis defect in claim 9 ("The integrated circuit of claim 1") noted in the earlier section was not resolved by a certificate of correction in the material I reviewed; this affects how claim 9 is construed but not the § 103 conclusion above.
3. No litigation or PTAB proceeding involving '005 was located (consistent with the prior section); this is a validity/obviousness analysis only and is not a legal opinion or a substitute for full-text review of every asserted reference.