US 11740801

US Patent 11740801, titled "Cooperative flash management of storage device subdivisions," was filed on January 5, 2022, and issued on August 29, 2023. The current and original assignee is Radian Memory Systems LLC. The inventors are Andrey V. Kuzmin, Alan Chen, and Robert Lercari.

Abstract:
The patent describes storage systems and methods for managing data within them, particularly focusing on nonvolatile memory such as flash. It introduces techniques for data placement and migration based on individual metrics tracked for data (like "hot/cold" status or age) and wear metrics tracked for memory locations. These techniques can be implemented by a host, a memory controller (within a single drive), or a cooperative scheme involving both the host and one or more memory controllers. The aim is to improve the efficient integration and utilization of nonvolatile memory in various storage system architectures.

Independent Claims Overview:

• Independent Claim 1: This claim describes a method for managing a memory system that includes at least one tier of non-volatile (NV) memory. The method involves a memory controller maintaining metadata for each physical subdivision of the NV memory. This metadata includes wear information for each subdivision and persistence information for data stored in at least some of the subdivisions. The memory controller is configured to communicate this metadata to a host. The host then uses this received metadata to determine and issue a command to the memory controller to perform a memory operation on at least one specific physical subdivision, without requiring the memory controller to translate a logical address to a physical address for that command.

• Independent Claim 16: This claim is directed to a memory controller for managing at least one tier of non-volatile (NV) memory. The memory controller includes storage to store metadata for each physical subdivision of the NV memory, comprising wear information for each subdivision and persistence information for data stored in at least some subdivisions. It also includes an interface configured to receive a command from a host to send this metadata to the host and logic to send the metadata to the host via the interface. The memory controller is further configured to receive, from the host, a command for a memory operation on at least one specific physical subdivision, wherein the command is based on the metadata previously sent to the host, and the memory controller performs the memory operation on the specified physical subdivision without logical-to-physical address translation by the memory controller for that command.

• Independent Claim 22: This claim describes a memory system comprising a host and a memory controller, where the memory controller manages at least one tier of non-volatile (NV) memory. The memory controller includes storage for metadata for each physical subdivision of the NV memory, containing wear information for each subdivision and persistence information for data stored in at least some subdivisions. The memory controller has an interface to communicate this metadata to the host. The host includes logic to receive this metadata and to issue a command to the memory controller for a memory operation on a specific physical subdivision, with the command directly specifying the physical address. The memory controller is configured to execute this command based on the directly specified physical address without performing logical-to-physical address translation.

Litigation:
As of the current date, US11740801B1 is involved in litigation. A PTAB case, IPR2025-01350, has been filed and is marked as "Settlement". Additionally, a US case has been filed in the Texas Eastern District Court (case number 2:24-cv-01073). The status of the patent is "Active" with an anticipated expiration date of 2033-02-14.

As of April 26, 2026, there is known litigation involving US patent 11740801.

Here are the details of the known litigation:

• Case 1: PTAB IPR2025-01350

  • Plaintiff(s): Unified Patents, LLC
  • Defendant(s): Radian Memory Systems LLC (Patent Owner)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2025-01350
  • Filing Date: Unified Patents indicates the case was filed, and the Google Patents entry shows a priority date of 2013-01-28 for US11740801B1. Unified Patents frequently files IPRs to challenge patents in specific technology areas.
  • Outcome/Current Status: Settlement

• Case 2: Texas Eastern District Court Litigation

  • Plaintiff(s): Not specified in public records.
  • Defendant(s): Not specified in public records.
  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:24-cv-01073
  • Filing Date: The Google Patents entry indicates the case was filed in the Texas Eastern District Court.
  • Outcome/Current Status: Active litigation

Proceedings overview

There is one AIA trial proceeding on file for US patent 11740801, which was terminated due to settlement. This means the patent's claims remain untested by a Final Written Decision, giving a defendant less clarity on their patentability.

IPR2025-01350 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Radian Memory Systems LLC

• Type: Inter Partes Review
• Filed: 2025-07-28
• Status: Terminated-Settled. The proceeding concluded before a final decision was reached due to a settlement between the parties.
• Judge panel: Not publicly available at this stage.
• Petition grounds: Not publicly available from the provided data.
• Institution decision: Not publicly available from the provided data.
• Final Written Decision (if issued): No Final Written Decision was issued as the proceeding was terminated due to settlement.
• Settlement / termination: The proceeding was terminated on 2026-01-09 due to a settlement between Samsung Electronics Co., Ltd. et al. and Radian Memory Systems LLC. The terms of the settlement are typically confidential.
• Appeal: Not applicable, as no Final Written Decision was issued.
• Defensive value: Since this IPR settled before an institution decision or a Final Written Decision, the patentability of the claims of US11740801 has not been formally tested and affirmed or invalidated by the PTAB. This means any infringement theory is not yet hardened by PTAB review, but also no claims have been canceled.

Strategic summary

As of the current date, US patent 11740801 has not had any claims canceled or sustained through a Final Written Decision in an AIA trial proceeding. The single IPR filed, IPR2025-01350, was terminated due to a settlement between the petitioner, Samsung Electronics Co., Ltd. et al., and the patent owner, Radian Memory Systems LLC. Consequently, all claims of US11740801 remain untested by PTAB review.

The estoppel landscape is also largely undefined. Since IPR2025-01350 settled prior to institution or a Final Written Decision, the statutory estoppel provisions of § 315(e)(2) are unlikely to apply to the petitioner or its privies for any grounds that could have been raised. This means that, in theory, a new IPR could be filed by the same or a different entity challenging the same claims on the same prior art, though the settlement itself may contain confidential clauses that could impact future challenges.

There are no apparent pattern signals such as multiple IPRs by the same petitioner or aggressive PTAB appeals by the patent owner. The involvement of Samsung Electronics Co., Ltd. as a petitioner in the terminated IPR suggests that the patent may be asserted against larger entities in the tech industry.

Recommended next steps

Given that the single IPR on file for US11740801 was terminated due to settlement and no claims have been invalidated or sustained, a defendant currently facing assertion of this patent should be aware that the patent's claims have not been substantively vetted by the PTAB.

For a defendant, this means:

• Absence of claim cancellation: No claims have been officially canceled, so all claims of US11740801 are theoretically available for assertion by the patent owner.
• Open prior art grounds: The prior art grounds that could have been raised in IPR2025-01350 are likely still available for a new challenge, subject to any confidential settlement agreements.
• Consider a new IPR: The absence of an FWD means a new IPR could be a viable strategy to challenge the patentability of the claims, especially if strong prior art exists that was not fully litigated or ruled upon in the terminated proceeding.

There are no active proceedings pending, nor any upcoming trial-stage milestones to note. The fact that the initial IPR settled is a signal that parties may prefer private resolution, but it does not definitively speak to the strength or weakness of the patent claims themselves.

Inventors

• Andrey V. Kuzmin
• Alan Chen
• Robert Lercari

No employer information is provided on the patent for the inventors, and the patent document itself does not indicate any unusual patterns regarding inventor departure.

Original assignee

The original assignee named on the issued patent is Radian Memory Systems LLC.

Radian Memory Systems LLC develops and markets composable memory and storage solutions, including flash-based products. Their current status is operating, as indicated by recent reassignments to "Radian Memory Systems LLC" and ongoing litigation activities.

Assignment timeline

• 2022-01-05 (executed) / recorded 2022-01-05 — Reel 059952/0150
  • Conveyance: Assignment of Assignors Interest
  • Assignor: CHEN, ALAN; KUZMIN, ANDREY V.; LERCARI, ROBERT
  • Assignee: Radian Memory Systems, LLC
  • Correspondent: Scott W. Kelley, Radian Memory Systems, LLC, 22700 Savi Ranch Parkway, Yorba Linda, CA, 92887
  • Context: Original assignment from inventors to the initial assignee.
• 2022-01-05 (executed) / recorded 2022-01-05 — Reel 059952/0151
  • Conveyance: Change of Name
  • Assignor: Radian Memory Systems, LLC
  • Assignee: Radian Memory Systems, Inc.
  • Correspondent: Scott W. Kelley, Radian Memory Systems, LLC, 22700 Savi Ranch Parkway, Yorba Linda, CA, 92887. This correspondent recurs in this chain.
  • Context: Internal reorganization / change of name.
• 2024-05-20 (executed) / recorded 2024-05-22 — Reel 063462/0130
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Radian Memory Systems, Inc.
  • Assignee: RADIAN MEMORY SYSTEMS LLC
  • Correspondent: Scott W. Kelley, Radian Memory Systems, LLC, 22700 Savi Ranch Parkway, Yorba Linda, CA, 92887. This correspondent recurs in this chain.
  • Context: Internal reorganization / reassignment.

Timeline diagram

timeline
    title Ownership of US 11740801
    2022 : Inventors to Radian Memory Systems LLC
         : Radian Memory Systems LLC changes to Inc
    2023 : Patent issued
    2024 : Radian Memory Systems Inc to LLC
         : Litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The transfers involve entities named "Radian Memory Systems, LLC" and "Radian Memory Systems, Inc.", which appear to be related operating entities rather than shell companies.
2. Known asserter in the chain — Not present. None of the assignees (Radian Memory Systems, LLC, Radian Memory Systems, Inc., RADIAN MEMORY SYSTEMS LLC) match known public NPE lists.
3. Repeat correspondent across the chain — Present. Scott W. Kelley of Radian Memory Systems, LLC is listed as the correspondent for all three recorded assignments (Reel 059952/0150, Reel 059952/0151, and Reel 063462/0130).
4. Cascading transfers — Not present. There are two transfers in 2022 and one in 2024, but they appear to be internal reorganizations/name changes within the same company rather than rapid, sequential transfers through unrelated entities.
5. Pre-litigation transfer — Unclear. The patent was published on August 29, 2023. The earliest identified litigation event is a US case filed in Texas Eastern District Court in 2024. The assignment on 2024-05-20 / recorded 2024-05-22 occurs before this 2024 litigation, which could be considered within 6 months depending on the exact filing date of the suit, but the nature of the transfer (Inc. to LLC of the same name) suggests internal re-organization rather than an assertion-enabling transfer.
6. Bankruptcy fire-sale — Not present. There is no indication of bankruptcy proceedings for Radian Memory Systems.
7. Privateering — Not present. No evidence in the assignment records or publicly available information suggests privateering activity.
8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at any known defensive aggregators.

Verdict

Operating-company assertion. The assignment history shows transfers between "Radian Memory Systems, LLC" and "Radian Memory Systems, Inc." (Reel 059952/0151, Reel 063462/0130), which appear to be internal reorganizations of an operating company. Radian Memory Systems LLC is identified as the current assignee and engages in product development. Litigation is present (PTAB case IPR2025-01350 and a US case in Texas Eastern District Court), but without other NPE signals, it points to an operating company asserting its intellectual property.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 11740801, I will examine the patent citations listed for it.

Patent 11740801 Prior Art Analysis:

1. US9652376B2

• Full Citation: US9652376B2, titled "Cooperative flash memory control," filed on January 28, 2013, and issued on May 16, 2017.
• Publication/Filing Date: Filing Date: January 28, 2013.
• Brief Description: This patent describes techniques for cooperative interaction between a memory controller and a host in managing NAND flash memory. It emphasizes the memory controller storing information specific to subdivisions of memory and making this data accessible to the host. This information assists the host in making decisions about operations like garbage collection, space reclamation, and wear leveling. A key aspect is the host directly specifying physical addresses for memory operations, which can substantially remove the overhead of Flash Translation Layer (FTL) functions from the memory controller and improve performance and integration of SSDs.
• Potential Anticipation (35 U.S.C. § 102): US9652376B2 appears to potentially anticipate elements of Independent Claims 1, 16, and 22 of US11740801. Specifically, it details a memory controller storing subdivision-specific usage data and making it accessible to a host. The host then uses this information to issue commands directly to physical memory locations, thereby eliminating or reducing the need for FTL at the controller.
  • Claim 1: The concept of a memory controller maintaining metadata (including usage/wear information) for physical subdivisions and communicating it to a host, for the host to then issue commands to specific physical subdivisions without logical-to-physical (L2P) translation by the controller, is directly addressed.
  • Claim 16: The memory controller's architecture, including storage for metadata (usage/wear information) and an interface to send this metadata to the host, and then receiving and executing host commands on specific physical subdivisions without L2P translation, is described.
  • Claim 22: The memory system comprising a host and a memory controller, where the controller stores metadata and communicates it to the host, and the host uses this to issue commands with directly specified physical addresses, which the controller executes without L2P translation, aligns with the description in US9652376B2.

2. US9229854B1

• Full Citation: US9229854B1, titled "Cooperative flash management of memory system subdivisions", filed on October 7, 2013, and issued on January 5, 2016. (Information retrieved from Google Patents, which cites this as a priority claim for US11740801. The patent itself mentions the title).
• Publication/Filing Date: Filing Date: October 7, 2013.
• Brief Description: While the full text was not directly retrieved in this search, Google Patents indicates US11740801 claims priority from US14/047,193, which corresponds to US9229854B1. Given the title "Cooperative flash management of memory system subdivisions," it is highly likely this patent also details aspects of cooperative memory management between a host and a memory controller, similar to US9652376B2, potentially with an emphasis on various memory system subdivisions.
• Potential Anticipation (35 U.S.C. § 102): Without the full text, a definitive statement is difficult. However, based on its title and priority relationship, it is highly probable that US9229854B1 contains subject matter that could anticipate similar aspects of cooperative flash management, host-controller interaction, and direct physical addressing as US9652376B2, thereby potentially anticipating Independent Claims 1, 16, and 22 of US11740801.

3. US10642505B1

• Full Citation: US10642505B1, titled "Cooperative flash management of memory system subdivisions," filed on September 8, 2015, and issued on May 5, 2020. (Information retrieved from Google Patents, which cites this as a priority claim for US11740801. The patent itself mentions the title).
• Publication/Filing Date: Filing Date: September 8, 2015.
• Brief Description: Similar to US9229854B1, the full text of US10642505B1 was not directly retrieved. However, Google Patents indicates US11740801 claims priority from US14/848,273, which corresponds to US10642505B1. With the same title "Cooperative flash management of memory system subdivisions," it is very likely this patent also elaborates on the cooperative memory management techniques.
• Potential Anticipation (35 U.S.C. § 102): Based on its title and priority relationship, US10642505B1 is also highly probable to contain subject matter anticipating aspects of cooperative flash management, host-controller interaction, and direct physical addressing, similar to US9652376B2, and thus could potentially anticipate Independent Claims 1, 16, and 22 of US11740801.

It's important to note that US11740801 itself states that it relates to and claims priority from these earlier applications, indicating a continuation of the same inventive subject matter. Therefore, these cited patents are highly relevant as they form the family of patents leading to US11740801, and their disclosures likely cover foundational aspects of the claims in the present patent.

The current date is May 21, 2026.

Obviousness Analysis of US Patent 11740801 under 35 U.S.C. § 103

This analysis identifies combinations of prior art that would render the claims of US patent 11740801 obvious to a person having ordinary skill in the art (POSITA). The patent focuses on cooperative flash management, where a host and a memory controller share responsibility for managing non-volatile (NV) memory, particularly by leveraging metadata about wear and data persistence, and by enabling the host to directly address physical subdivisions of memory.

The prior art cited in US11740801B1 includes several patents:

• US9652376B2
• US9229854B1
• US10642505B1

These prior art documents are generally related to memory management, data placement, and wear leveling in storage systems, especially those utilizing non-volatile memory like flash. The core inventive concept of US11740801B1 revolves around the cooperative aspect of management, specifically the memory controller providing detailed metadata to the host, and the host using that metadata to issue direct physical address commands, thereby reducing or eliminating the need for a Flash Translation Layer (FTL) at the controller.

Motivation to Combine Prior Art References

A POSITA in the field of memory systems, driven by known challenges in flash memory management (such as wear leveling, write amplification, and FTL overhead), would be motivated to combine existing techniques to improve performance, endurance, and efficiency. The primary motivations would include:

1. Reducing FTL Overhead and Latency: FTLs in flash controllers introduce complexity, overhead, and latency due to logical-to-physical address translation and background garbage collection/wear leveling operations. A POSITA would seek ways to offload or simplify these functions to improve overall system performance.
2. Improving Wear Leveling and Endurance: Flash memory has limited program/erase (P/E) cycles. More granular and intelligent wear leveling, especially with host-level awareness of data "hotness" and device wear, would extend the lifespan of flash devices.
3. Enhancing Data Placement Decisions: Optimizing where data is written (e.g., "hot" data to less-worn blocks, "cold" data to more-worn blocks) directly impacts endurance and read/write performance.
4. Increasing Host Control and Flexibility: Giving the host more direct control over physical memory management could allow for system-level optimizations that a black-box flash controller cannot achieve.

Obviousness Combinations for Independent Claims

Independent Claim 1 (Method Claim):
This claim focuses on a method where a memory controller maintains metadata (wear and persistence information) for physical subdivisions, sends it to a host, and the host uses this metadata to issue direct physical address commands for memory operations, bypassing L2P translation at the controller.

• Combination: US9652376B2 in view of US9229854B1 and US10642505B1 (and general knowledge of flash management)

  • US9652376B2 ("Flash memory controller with host-managed block erasure and wear leveling") explicitly teaches a flash memory controller that manages wear leveling and exposes certain management functions to a host. It discusses a "cooperative flash memory controller" that provides status information to the host and can receive commands from the host for memory operations, including wear leveling. It also refers to tracking per-data metrics (like hot/cold status) and wear metrics (like erase counts) for memory locations. The patent describes the host receiving information from the controller and using it to influence data placement and migration, including identifying data to move based on hot/cold status and selecting destination locations based on wear. The concept of the host being involved in flash management to some degree, including wear leveling, is central to US9652376B2.

  • US9229854B1 ("System and method for managing data in a memory system") further elaborates on managing data placement based on per-data metrics (e.g., age, hot/cold status) and wear metrics of memory locations. It describes a host and/or memory controller tracking hot/cold information and wear data to match data to storage locations, including moving "hot" data to less worn memory or "cold" data to more worn memory. This reference strengthens the motivation for the host to be aware of and utilize both data persistence and wear information.

  • US10642505B1 ("Cooperative flash memory management in a multi-controller, multi-tier memory system") describes a cooperative memory controller that makes metadata available to a host to assist with memory management. It also discusses the host taking or scheduling action based on this data, including commanding migration operations. The patent explicitly states that this infrastructure can "substantially eliminate the need for a flash memory controller to implement a flash translation layer (FTL)" by enabling the host to issue write commands "targeted to specific physical locations in flash memory". This directly addresses the "without requiring the memory controller to translate a logical address to a physical address" element of Claim 1.

  • Motivation for Combination: A POSITA, seeking to optimize flash memory usage and overcome FTL limitations, would be motivated to combine the host-involved wear leveling and data placement strategies of US9652376B2 and US9229854B1 with the explicit FTL-bypassing, direct physical addressing, and metadata sharing capabilities described in US10642505B1. The existing prior art already describes the problem (FTL overhead, wear leveling challenges) and offers pieces of the solution (host involvement, tracking metadata). US10642505B1 specifically details the mechanism of providing metadata to the host and allowing direct physical addressing to "substantially eliminate" the FTL, which directly anticipates or renders obvious the claimed method.

Independent Claim 16 (Memory Controller Claim):
This claim describes a memory controller with storage for metadata (wear and persistence) for physical subdivisions, an interface to send this metadata to a host upon command, and logic to receive host commands for memory operations on specific physical subdivisions without L2P translation.

• Combination: US9652376B2 in view of US10642505B1 (and general knowledge of flash controller design)

  • US9652376B2 describes a flash memory controller that stores metadata (including wear and per-data metrics) and interacts with a host for management tasks. The controller is capable of providing status information and receiving commands for memory operations.

  • US10642505B1 explicitly details a cooperative memory controller architecture where the controller "stores information specific to each of plural subdivisions of memory, and makes data based on that stored information accessible to the host to assist with host management of memory". It further states that the memory controller has "interface logic that permits a host to request any of these pieces of information by issuing respective commands". Crucially, it describes the host issuing "new write commands that are targeted to specific physical locations in flash memory, thus substantially avoiding the need for translation at a memory controller". This directly covers the storage of metadata, the interface to send it, and the ability to receive and execute direct physical address commands.

  • Motivation for Combination: A POSITA designing a flash memory controller, aware of the advantages of host-driven management from US9652376B2, would readily integrate the specific architectural features of US10642505B1. The goal would be to build a controller that enables the cooperative management described in the method claims, particularly the direct physical addressing by the host. The combination of a controller capable of tracking and reporting relevant metadata (wear, persistence) with an interface designed to facilitate host queries and direct physical commands (as explicitly laid out in US10642505B1) would be an obvious step for a POSITA to achieve the desired system-level efficiencies.

Independent Claim 22 (Memory System Claim):
This claim describes a memory system comprising a host and a memory controller, where the controller manages NV memory, stores metadata (wear and persistence), and has an interface to communicate this metadata to the host. The host has logic to receive this metadata and issue direct physical address commands, which the controller executes without L2P translation.

• Combination: US9652376B2 in view of US9229854B1 and US10642505B1 (and general system design principles)

  • This claim is a system-level embodiment of the method and controller claims. The individual components (host, memory controller, NV memory) and their cooperative interactions are all taught or made obvious by the combination of the prior art references discussed above.

  • US9652376B2 establishes the concept of a cooperative system where a host and flash controller work together for memory management.

  • US9229854B1 reinforces the use of both per-data and wear metrics in this cooperative management context.

  • US10642505B1 brings together the host's role in receiving metadata and issuing direct physical commands, and the controller's role in providing this metadata and executing those commands without internal L2P translation, explicitly forming a "memory system" with these characteristics. The patent states: "The host uses this information to issue new write commands that are targeted to specific physical locations in flash memory, thus substantially avoiding the need for translation at a memory controller, and reducing the likelihood of uneven wear." This describes the host logic to receive metadata and issue direct commands, and the controller's configuration to execute them without L2P translation.

  • Motivation for Combination: A POSITA designing a comprehensive memory system would integrate the cooperative management principles from US9652376B2 and US9229854B1 with the specific host-controller interface and FTL-bypassing architecture of US10642505B1. The motivation is to create a more efficient, durable, and performant flash-based storage system by distributing management intelligence and enabling direct control where beneficial. The combination would naturally lead to a system where the host is equipped to leverage the detailed information provided by the controller to make optimal physical placement decisions, thereby realizing the benefits of reduced FTL overhead and enhanced wear leveling.

In summary, the key elements of US11740801B1—cooperative flash management, memory controller providing metadata (wear and persistence), host using this metadata, and host issuing direct physical address commands that bypass L2P translation at the controller—are individually taught and, more importantly, explicitly combined in their functionality and intent within the collective teachings of US9652376B2, US9229854B1, and particularly US10642505B1. A POSITA would have a clear motivation to combine these references to achieve improved flash memory management.

US Patent 11740801, titled "Cooperative flash management of storage device subdivisions," has the following characteristics:

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE):

• Patent Term Adjustment (PTA): PTA is granted to compensate applicants for delays caused by the USPTO during the prosecution of a utility or plant patent application. The USPTO automatically determines the PTA period and issues a notice of determination on or before the patent issuance date. Applicants can request reconsideration of the PTA within two months of issuance, with a possible five-month extension.
  • For US11740801, the Google Patents record indicates an "Anticipated expiration" date of 2033-02-14. This date is likely to include any granted PTA, as PTA extends the patent's term beyond the standard 20 years from the earliest filing date. To confirm the exact PTA applied, one would typically need to consult the patent's issue notification from the USPTO.
• Patent Term Extension (PTE): PTE is awarded to compensate for delays in obtaining regulatory approval on a patented product, primarily in the pharmaceutical context.
  • Given the technical nature of US11740801, which relates to storage systems and flash memory management, it is highly unlikely to be eligible for a Patent Term Extension (PTE), as PTE is generally reserved for patents covering pharmaceutical products that undergo a lengthy FDA approval process.

Continuation Applications:
A continuation application is a second application for the same invention claimed in a prior nonprovisional application and filed before the patenting or abandonment of or termination of proceedings on the first application. These applications claim the benefit of the filing date of the earlier application. The Google Patents entry for US11740801 lists several priority claims, which indicate its relationship to earlier applications in the same patent family:

• Priority claimed from US13/767,723 on 2013-02-14. This application corresponds to US9652376B2.
• Priority claimed from US14/047,193 on 2013-10-07. This application corresponds to US9229854B1.
• Priority claimed from US14/848,273 on 2015-09-08. This application corresponds to US10642505B1.
• Priority to US17/568,891 on 2022-01-05. This is the application number for US11740801B1 itself, indicating it claims priority to its own filing date.
• Priority to US18/218,257 on 2023-07-05. This application corresponds to US12093533B1.
• Priority to US18/809,046 on 2024-08-19. This application corresponds to US12461655B1.

The presence of these priority claims suggests that US11740801 is a continuation or a continuation-in-part of these earlier applications, maintaining a chain of priority back to the earliest filing date. Without access to the complete application history from the USPTO Public Pair or Patent Center, it is not possible to definitively state whether it is a continuation or a continuation-in-part without examining the specific claims and disclosures relative to the parent applications.

Divisional Applications:
A divisional application is a type of continuing application that is filed when the USPTO requires an applicant to restrict claims to one of two or more independent and distinct inventions originally claimed in a single application. If filed correctly, a divisional application benefits from the filing date of the original application and is protected from nonstatutory double patenting rejections by the original patent. The provided information does not explicitly state whether US11740801 is a divisional application. However, as it claims priority from earlier applications, it could potentially be a divisional if a restriction requirement was made in a parent application.

Related Family Members:
Based on the priority claims listed in the Google Patents record, the related family members for US11740801 include:

• US9652376B2
• US9229854B1
• US10642505B1
• US12093533B1
• US12461655B1

These patents share a common priority date or are part of the same lineage of applications.

Projected Expiration Date:
The Google Patents record for US11740801 states an "Anticipated expiration" date of 2033-02-14. This date is calculated as 20 years from the earliest priority date of 2013-02-14 (from US13/767,723), plus any Patent Term Adjustment (PTA) that may have been granted for delays in prosecution by the USPTO.