Summary of US Patent 11,570,034 B2 (US11570034) — "Cluster computing"

I searched for the literal number 11570034 (US Patent 11,570,034 B2). Below is what is confirmed from the authoritative Google Patents record (the full patent text you provided), the USPTO/PTAB docket, and supporting secondary sources. I flag uncertainty where the information is not verified.

Bibliographic data (high confidence — matches the Google Patents record and Dimensions)

Sources: https://patents.google.com/patent/US11570034/en ; https://app.dimensions.ai/details/patent/US-11570034-B2 ; https://wiki.golden.com/wiki/US_Patent_11570034_Cluster_computing-8J6KJZ6

Abstract (verbatim)

"In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster."

Plain-language overview of the independent claim-style embodiments

Important caveat: The full text you provided (and the search results returned) does not include the granted "What is claimed" section, so I could not verify the exact wording or numbering of the issued independent claims from an authoritative source. The five embodiments below are the independent-claim-like paragraphs set out in the patent's Summary section. They almost certainly correspond to the issued independent claims, but treat the wording as inferred from the specification, not verified against the granted claim set (USPTO Patent Center / the IPR file history, e.g., Ex. 1002, would confirm the exact claims).

1. Three-processor cluster with message-storage data structure. A computer cluster with first, second, and third processors, each paired with a kernel (translating commands into executable code) and a cluster node module. The first node module receives commands from a user interface; the second and third node modules communicate with the first (and with each other). The first node module has a data structure storing messages originating from the second and third node modules.
2. Cluster node module that impersonates a kernel to the UI. A cluster with nodes running a software package having a user interface and a single-node kernel. A cluster node module talks to the kernel and to other node modules, accepts UI instructions, and interprets them so the node modules act as a cluster — all while appearing to the user interface as if it were a single-node kernel. (Specification variants: the kernel can be a Mathematica kernel; the UI can be a Mathematica front end or command line; the module can include MPI-style library calls and high-level cluster commands.)
3. Multi-node cluster with distributed user-interface/kernel code. Each node accesses a computer-readable medium containing program code for the user interface and for a single-node kernel module. Each cluster node module communicates with its kernel and with other node modules, accepts UI instructions, and interprets them so the modules act as a cluster over a communications network; one module returns the result to the UI.
4. Method of evaluating a command on a cluster. A command (from a UI or script) is communicated to one or more cluster node modules; each module sends a message based on the command to its associated kernel; each receives a result back from that kernel; and at least one module responds to messages from other cluster node modules.
5. Mathematica multi-node peer-to-peer computing system. A system with first, second, and third node modules, each in communication with a Mathematica kernel executing on a respective node. The node modules communicate using a peer-to-peer architecture, and each module includes (a) a data structure maintaining messages originating from other node modules and (b) a data structure maintaining data specifying where a message is expected to be received and from which node.

Litigation / post-issuance status (from searches)

• District court: Two W.D. Tex. cases are associated with this patent family — Advanced Cluster Systems, Inc. v. Intel Corporation, 7:24-cv-00245 (W.D. Tex.) and Advanced Cluster Systems, Inc. v. Advanced Micro Devices, Inc., 7:24-cv-00244 (W.D. Tex.) (per Unified Patents portal links on the Google Patents record).
• IPR: IPR2025-00913 — Intel Corporation and Advanced Micro Devices, Inc. v. Advanced Cluster Systems, Inc., challenging Patent 11,570,034 B2 (this patent). The petition was filed effective April 29, 2025, and trial was instituted. Per a PTAB Order dated January 29, 2026, the proceeding was terminated as to petitioner AMD due to settlement (35 U.S.C. § 317; 37 C.F.R. § 42.74), while Intel remains as petitioner. Related IPRs in the same order: IPR2025-00914 (US 12,021,679 B2), IPR2025-00915 (US 11,563,621 B2), IPR2025-00916 (US 11,811,582 B2).
  • Sources: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2025-00913 ; https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2025-00915/... (Order, Jan. 29, 2026)
• CAFC 2026 docket: My searches of CAFC 2026 docket records returned no appeal docket tied to patent 11,570,034 as of today (April 26, 2026). It is possible an appeal exists (e.g., from the IPR final written decision or the district court cases) that is not indexed under the patent number in the sources I searched, but I have no authoritative information confirming a CAFC 2026 appeal involving this specific patent number. If you need this confirmed, the CAFC docket search (PACER/CM/ECF) and USPTO P-TACTS would be the authoritative sources.

Outstanding uncertainties

1. Exact granted claim text and numbering — not present in the supplied full text or in the search results; the independent-claim overview above is inferred from the specification's Summary and should be confirmed against the issued patent (e.g., USPTO Patent Center, or IPR Ex. 1001).
2. CAFC 2026 appeal status — no docket located; do not rely on the absence as proof that none exists.
3. The Google Patents record notes the assignee list "may be inaccurate"; the current recorded assignee per assignment records is Advanced Cluster Systems, Inc.

Based on my searches, here is the known litigation involving US Patent No. 11,570,034 ("Cluster Computing," issued January 31, 2023, assigned to Advanced Cluster Systems, Inc. / "ACS"). I found two district court cases and one PTAB inter partes review. I could not confirm any CAFC appeals as of today (April 26, 2026).

1. Advanced Cluster Systems, Inc. v. Intel Corporation

• Case No.: 7:24-cv-00245-ADA (W.D. Tex., Midland–Odessa Division)
• Plaintiff: Advanced Cluster Systems, Inc. (ACS)
• Defendant: Intel Corporation
• Filing date: September 26, 2024
• Jurisdiction: U.S. District Court for the Western District of Texas (Judge Alan D. Albright)
• Patents-in-suit: The '034 patent (US 11,570,034) is asserted along with U.S. Patent Nos. 10,333,768; 11,563,621; 11,811,582; and 12,021,679 (the original complaint). Per the First Amended Complaint, ACS asserts claims 1 and 30 of the '034 patent.
• Accused products: Intel Xeon Scalable processors, Habana AI accelerator products (Gaudi, Gaudi 2, Gaudi 3, Goya), and servers/workstations incorporating them.
• Status: Pending/active. A Markman hearing was held before Judge Albright on August 18, 2025 (D.I. 79). Intel filed IPR petitions (see below) and moved for related relief; an IPR exhibit references a trial date around November 9, 2026, indicating the case remained live into late 2025. I found no docket entry confirming a final judgment or dismissal as of April 2026. (Note: one third-party case-tracking site labels the case "Closed," but the more recent PTAB filings and docket activity indicate it was still proceeding through claim construction in late 2025; treat that "Closed" label as unverified.)

2. Advanced Cluster Systems, Inc. v. Advanced Micro Devices, Inc.

• Case No.: 7:24-cv-00244-ADA (W.D. Tex.)
• Plaintiff: Advanced Cluster Systems, Inc. (ACS)
• Defendant: Advanced Micro Devices, Inc. (AMD)
• Filing date: September 26, 2024
• Jurisdiction: U.S. District Court for the Western District of Texas (Judge Alan D. Albright)
• Patents-in-suit: Same five-patent family, including the '034 patent. Per the amended complaint, ACS asserts claims 1, 2, 3, 8, 10, 24, 25, 27, and 28 of the '034 patent.
• Accused products: AMD EPYC 7002/7003/9004/9005 series processors, AMD Instinct accelerators (MI210, MI250, MI250X, MI300X, MI325X, MI355X, MI300A, MI350A), and server platforms incorporating them.
• Status: Dismissed. Per the Unified Patents docket for 7:24-cv-00244: ACS filed a corrected amended complaint (12/08/2025), AMD answered (12/22/2025), and an ORDER OF DISMISSAL was entered on January 22, 2026. The docket text does not state whether the dismissal was with or without prejudice.

3. Intel Corporation et al. v. Advanced Cluster Systems, Inc. — IPR2025-00913

• Tribunal: PTAB (patent trial and appeal board)
• Petitioner: Intel Corporation (et al.)
• Patent Owner: Advanced Cluster Systems, Inc.
• Filing date: Petition papers and exhibits filed April 29, 2025 (petition itself is docketed around that date)
• Patent challenged: US 11,570,034 (the '034 patent is Exhibit 1001)
• Status: Pending — instituted. Google Patents' litigation feed lists IPR2025-00913 as "Pending - Instituted." The record shows: Patent Owner's Preliminary Response (Aug. 27, 2025), Patent Owner's request for discretionary denial with brief (Jul. 28, 2025), Petitioner's opposition to discretionary denial (Sep. 2, 2025), and further exhibits through September 2025. A final written decision would normally be expected roughly 12 months after institution (i.e., later in 2026), so none has been reported yet.

Notes and caveats

• Related IPRs: Intel also filed IPR2025-00915, which appears in the same docket family and relies on the Intel complaint (7:24-cv-00245). I could not confirm from the available search results whether IPR2025-00915 also challenges the '034 patent or only other family members (e.g., the '582 or '679 patents). I recommend verifying its challenged patent(s) directly on the PTAB/Unified Patents portal before relying on it as an '034 proceeding.
• Earlier NVIDIA case: ACS's earlier campaign (ACS v. NVIDIA, W.D. Tex., filed Oct. 2019, dismissed Apr. 2023) asserted only U.S. Patent Nos. 8,082,289; 8,140,612; 8,676,877; and 10,333,768. US 11,570,034 was not among them, so it is not part of the '034 litigation history.
• Sources: Unified Patents portal (7:24-cv-00244 docket; IPR2025-00913), RPX litigation coverage, PTAB filings via the USPTO PTACTS system and third-party IPR trackers, and the ex parte/ai-lab case summaries for the West Texas dockets.

If you need me to dig further into the exact institution decision date for IPR2025-00913, the with/without-prejudice character of the AMD dismissal, or whether IPR2025-00915 covers the '034 patent, I can run additional targeted searches.

Proceedings overview

The USPTO Open Data Portal's canonical list shows one AIA trial proceeding on US 11,570,034: IPR2025-00913 (Inter Partes Review, filed 2025-04-29, status "Final Written Decision" as of the last data ingest on 2026-08-26). There are no active proceedings, no institution denials, and no settlements that terminated the case in its entirety on this patent — although AMD settled and was dismissed from IPR2025-00913 mid-trial, Intel remained as petitioner and the case ran to a Final Written Decision. Bottom line: the only IPR on the '034 patent has reached a decision at the Board, but the claim-level disposition of that Final Written Decision could not be retrieved and verified in this session (see the caveat under the proceeding below). Until the FWD is pulled from PTAB E2E and read, the patent must be treated as still in force as granted — I will not guess which claims (if any) were canceled.

IPR2025-00913 — Intel Corporation & Advanced Micro Devices, Inc. v. Advanced Cluster Systems, Inc.

• Type: Inter Partes Review (35 U.S.C. § 311)
• Filed: 2025-04-29
• Status: "Final Written Decision" (verbatim from the structured data; plain-English gloss: the Board has issued its merits decision and the PTAB phase is over, subject to any appeal to the Federal Circuit — see Appeal below, which I could not confirm)
• Judge panel: Karl D. Easthom, Arthur M. Peslak, Brian P. Murphy (APJs); the Institution Decision was authored by APJ Murphy (Paper 16, 2025-11-07). The Acting Director (Coke Morgan Stewart) handled the discretionary-denial stage (Paper 13, 2025-09-19).
• Petition grounds: All 30 claims challenged (claims 1–30), both grounds under 35 U.S.C. § 103:
  • Ground 1 — claims 1–25, 27–28, and 30 obvious over Menon (MultiMATLAB, 1997) in view of Trefethen (MultiMATLAB technical report, 1996), RS6000 (IBM RS/6000 SP manual), and POEref (IBM Parallel Operating Environment manual).
  • Ground 2 — claims 26 and 29 obvious over the Ground 1 combination further in view of MPIref (1994 Message-Passing Interface standard).
  • No § 102 or § 112 grounds were presented. Petitioner's expert was Dr. Chandrajit Bajaj (Ex. 1003/1004).
• Institution decision: Instituted — 2025-11-07 (Paper 16), on all 30 claims and both grounds (SAS-style full institution). The panel found a reasonable likelihood of prevailing on at least one claim despite Patent Owner's preliminary arguments that (a) none of the references discloses a "hardware processor with a plurality of processing cores" required by every independent claim, and (b) the references were not publicly accessible before the critical date of 2006-06-13 and thus were not "printed publications." Notably, the Acting Director first denied Patent Owner's request for discretionary denial (Paper 13, 2025-09-19) — rejecting both Fintiv-style arguments (the W.D. Tex. trial was scheduled 2026-11-16, close to the projected FWD date of 2026-11-27) and § 325(d) arguments — and referred the petition to the Board for merits institution.
• Final Written Decision (if issued): The structured data reports status "Final Written Decision." ⚠ I could not retrieve the FWD text in this session (the projected due date per Paper 13 was 2026-11-27; the canonical status was last modified 2026-08-26). Accordingly, I cannot and will not state which claims were canceled, which were held patentable, or quote the panel's reasoning. This is the single most important document to pull before making any assertion/invalidity decision — it is public at PTAB E2E/PTACTS (see links below). For context, Patent Owner's Response (Paper 22, filed 2026-02-06) argued five dispositive themes the panel may have credited: (1) no multi-core processor disclosure in the art; (2) no "Eval-return" of results to the first node/user interface; (3) no claimed 1→2→3→1 three-node execution flow; (4) no legally sufficient motivation to combine / reasonable expectation of success (and teaching away); and (5) failure to prove the references were printed publications pre-2006-06-13 — plus evidentiary objections to Petitioner's expert testimony.
• Settlement / termination: AMD settled with Patent Owner after institution. The Board granted the joint motion and terminated the proceeding as to AMD only (Paper 21, 2026-01-29) under 35 U.S.C. § 317(a) and 37 C.F.R. § 42.74. The settlement agreement was treated as business-confidential under § 42.74(c) — the terms are not public. Intel remained as petitioner, so the case was not dismissed in full and the FWD issued (per the status data).
• Appeal: Not verified. I found no record of a Federal Circuit appeal (docket number or disposition) in this session. Check the CAFC docket (CourtListener / PACER) before relying on the FWD as final.
• Defensive value: Nuanced and currently uncertain. Patent Owner has so far been remarkably successful at the PTAB on this family: NVIDIA's IPRs (IPR2021-00019/-00020) were denied institution, and Intel's and AMD's earlier petitions (IPR2025-00794/-00795, IPR2025-00862/-00863) were denied. IPR2025-00913 is the only petition that made it to trial on the '034 patent — but the FWD status means the challengers either won some claims or the patent owner held the line. Read the FWD before telling any client "the patent is dead" or "the patent is hardened." If the FWD upheld all claims, Intel/AMD are now estopped (§ 315(e)(2)) from re-litigating the Menon/Trefethen/RS6000/POEref/MPIref obviousness grounds in the parallel W.D. Tex. cases — but a new, non-privity defendant is not estopped and can still deploy that art (subject to the printed-publication problem Patent Owner raised).

Key documents (public):

• Director's discretionary-denial decision (Paper 13, 2025-09-19): https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2025-00913/Intel_Corporation_v._Advanced_Cluster_Systems_Inc/09-19-2025-Board/Director_Discretionary_Decision_Refer-13-Director_Discretionary_Decision_Refer/
• Institution Decision (Paper 16, 2025-11-07): https://www.docketalarm.com/cases/PTAB/IPR2025-00913/Intel_Corporation_v._Advanced_Cluster_Systems_Inc/docs/11-07-2025-Board/Institution_Decision__Grant-16-_Decision_Granting_Institution_of_Inter_Partes_Review.pdf
• AMD termination order (Paper 21, 2026-01-29): https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2025-00913/Intel_Corporation_v._Advanced_Cluster_Systems_Inc/01-29-2026-Board/Order__Termination_as_to_one_party-21-Order__Termination_as_to_one_party_AMD/
• Patent Owner Response (Paper 22, 2026-02-06): https://gaeflexstaging-dot-docketupdate.appspot.com/cases/PTAB/IPR2025-00913/Intel_Corporation_v._Advanced_Cluster_Systems_Inc/02-06-2026-Patent_Owner/PO_Response_to_Pet-22-Patent_Owner_Response/
• Case docket/filings via USPTO PTACTS: https://ptacts.uspto.gov/ (search IPR2025-00913)

Strategic summary

Claims — CANCELED vs. SUSTAINED vs. UNTESTED. All 30 claims (1–30) of the '034 patent were challenged, and all 30 were instituted — there are no untested claims and no claims that escaped institution. However, the claim-by-claim outcome of the FWD is unverified in this session (I could not retrieve the FWD text; the status field merely reports "Final Written Decision"). Do not represent to a client that any claim is canceled or sustained until the FWD is read. What is verified: the PTAB trial phase is concluded, AMD is out via confidential settlement, and the proceeding was not terminated early — it ran to a merits decision.

Estoppel landscape (§ 315(e)(2)). With a FWD on the books, Intel and AMD (and their privies — relevant to the parallel W.D. Tex. cases ACS v. Intel, 7:24-cv-00245, and ACS v. AMD, 7:24-cv-00244, both filed 2024-09-26) are barred from asserting in district court any § 102/§ 103 ground they raised or reasonably could have raised in IPR2025-00913 — i.e., the Menon/Trefethen/RS6000/POEref/MPIref obviousness combinations. For a new defendant not in privity with Intel or AMD, those grounds remain available — with two cautions: (1) Patent Owner fought hard on the "printed publication" issue (public accessibility before 2006-06-13), so anyone reusing that art must be prepared to prove public accessibility with contemporaneous evidence; and (2) if the Board already rejected that art on the merits, the art is weakened for everyone. § 101 (subject-matter eligibility) and § 112 (indefiniteness) grounds were not IPR grounds and remain fully available — note that in the W.D. Tex. litigation the court found claim 30's "communicate a result … to the first node" phrase indefinite (per Patent Owner's own Response, citing Ex. 1085), a ruling Patent Owner says is still appealable. That indefiniteness finding is litigation, not PTAB, and could be a potent non-infringement/invalidity lever independent of the IPR.

Pattern signals. This is a heavily-contested patent from a plaintiff that is litigating aggressively: ACS has asserted it against NVIDIA (D. Del. 1:19-cv-02032, dismissed; NVIDIA's IPR2021-00019/-00020 denied institution), Intel and AMD (the two pending W.D. Tex. cases), and it faced an eight-petition Intel/AMD campaign across its family (IPR2025-00794/-00795, -00862/-00863 — all denied institution; IPR2025-00913, -00914, -00915, -00916 — the four that were instituted, three on other ACS patents). The same two petitioners (Intel/AMD) filed multiple IPRs, and IPR2025-00913 is the one that broke through to trial on this patent. The patent owner has prevailed at the institution stage repeatedly and fought discretionary denial to the Director's desk (and won — the Director referred the case to the merits panel). Unified Patents appears only as a PTAB data feed source on the Google Patents page, not as a party or defensive-aggregator petitioner — the real petitioners here are Intel and AMD directly. The takeaway: this patent owner does not fold, so a defendant should expect IPR grounds to be fought hard through FWD and likely appeal.

Recommended next steps

1. Pull the Final Written Decision immediately. It is the dispositive document and it is public. Get Paper ~25/26 from PTAB E2E (https://ptab.uspto.gov/) or PTACTS (https://ptacts.uspto.gov/, search IPR2025-00913) and read the claim-by-claim disposition. If the FWD cancels claims, quote the disposition directly in any district-court papers and move to stay/limit the parallel W.D. Tex. case; if it sustains the claims, know that Intel/AMD are estopped on the IPR art but a non-privity defendant is not.
2. Check for a Federal Circuit appeal. The statutory 12-month trial deadline ran from institution (2025-11-07 → FWD due ~2026-11-07, projected 2026-11-27 per Paper 13), and the canonical status shows the FWD as already entered. Any appeal (either side) would be docketed at the CAFC — search CourtListener/PACER before treating the FWD as final.
3. For a defendant being asserted against today: If you are Intel, AMD, or their privy, § 315(e)(2) estoppel binds you — your § 103 case on the IPR art is closed, so lean on the court's claim-30 indefiniteness ruling and § 101. If you are a new defendant, the Menon/Trefethen art is still available but must be re-proven, including its public accessibility before 2006-06-13 — expect ACS to relitigate that issue and to fight every ground through the FWD and beyond. Do not tell any client the '034 patent's claims are "dead" until the FWD's claim-level holding is confirmed — as of now, the verified record shows a single concluded IPR whose merits outcome I could not confirm, which is not the profile of a patent that has been definitively narrowed.

Inventors

• Dean E. Dauger — President and CEO of Dauger Research, Inc., a developer of "Cluster Computing, Scientific Visualization and Simulation software." Dauger Research, Inc. was the original owner of at least part of the family and is a named assignor on the recorded assignment (reel 057139/0161). Dauger is also a prolific inventor on the broader cluster-computing family (e.g., US 8,082,289; 8,140,612; 8,676,877; 10,333,768).
• Zvi Tannenbaum — Founder of Advanced Cluster Systems, Inc. (ACS) in 2004; the complaints describe ACS's mission as "building innovative parallel programming tools for high-performance computing applications running on multicore, clusters, and supercomputers." Tannenbaum is the first-named inventor on the application that issued as US 11,570,034.

Pattern note: This is a two-inventor family where one inventor is the CEO of the assignor company (Dauger Research) and the other founded the current assignee (ACS). This is an inventor-controlled setup, not a "departing inventors then portfolio fire-sale" pattern — the inventors are the ones running the asserting entity.

Original assignee

Advanced Cluster Systems, Inc. (ACS) — the entity named on the issued patent and the recorded assignee. ACS develops "Supercomputing Engine Technology (SET)" for parallelizing single-node applications, specifically "Wolfram Research Mathematica, providing it with supercomputing-level parallelization." It is a small, privately held, inventor-controlled company (California). Status: operating — it is the active plaintiff in two Western District of Texas suits (7:24-cv-00244-ADA vs. AMD; 7:24-cv-00245-ADA vs. Intel, filed 2024-09-26) and the patent owner in IPR2025-00913. Its sole enforcement campaign began in October 2019 against NVIDIA (1:19-cv-02032 D. Del.), which was dismissed in April 2023 after a settlement. Whether ACS currently ships a commercial product is not verifiable from public sources; its complaints tout development of SET rather than current sales.

Assignment timeline

USPTO Assignment Center records (as surfaced via Google Patents legal events and Dimensions) show three recorded assignments, all on 2021-08-10, all to Advanced Cluster Systems, Inc. No post-issuance assignments to any third party are recorded. Correspondents of record could not be retrieved from the available sources in this session (USPTO Assignment Center was not directly accessible); that field is flagged as unverified rather than assumed.

• 2011-10-13 (executed; per secondary-source data) / recorded 2021-08-10 — Reel 057139/0161

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Dauger Research, Inc.
  • Assignee: Advanced Cluster Systems, Inc. (California)
  • Correspondent: not retrievable from sources available in this session
  • Context: inventor-company assignment perfecting ACS's chain of title on the continuation application; executed ~2011, recorded ~a decade later alongside the 2021 continuation filings.

• 2011-10-24 (executed; per secondary-source data) / recorded 2021-08-10 — Reel 057139/0166

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Zvi Tannenbaum
  • Assignee: Advanced Cluster Systems, Inc.
  • Correspondent: not retrievable from sources available in this session
  • Context: inventor assignment to the company he founded in 2004.

• Execution date not confirmed / recorded 2021-08-10 — Reel 057139/0246

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Dauger, Dean, Dr.
  • Assignee: Advanced Cluster Systems, Inc.
  • Correspondent: not retrievable from sources available in this session
  • Context: inventor assignment completing ACS's title (Dauger's individual interest, separate from Dauger Research's interest in reel 057139/0161).

No further assignments, mergers, security agreements, or name changes appear in the record for this patent. The chain is stable: inventors / Dauger Research → ACS, and ACS remains the recorded assignee today (confirmed by its IPR mandatory notice identifying ACS as "the recorded assignee of the '034 Patent").

Timeline diagram

timeline
    title Ownership of US 11570034
    2004 : ACS founded by Tannenbaum
    2006 : Priority application filed
    2011 : Inventor assignments executed
    2019 : First suit against NVIDIA
    2021 : Continuation filed
         : Assignments recorded to ACS
    2023 : Patent issued
    2024 : Suits filed vs Intel and AMD
    2025 : IPR instituted by Intel

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The patent moved only from the inventors and Dauger Research, Inc. to Advanced Cluster Systems, Inc. (reels 057139/0161, 0166, 0246, recorded 2021-08-10). ACS is the developer entity founded in 2004 (per the complaints and Mondaq's "Inventor-Controlled Plaintiff" coverage), not a licensing-only LLC, and there is no transfer to an "IP / Holdings / Ventures" shell.
2. Known asserter in the chain — not present against the specified rosters. No assignee in the chain matches Acacia, Marathon, Intellectual Ventures, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Round Rock, Document Generation Corp., or Spangenberg entities. ACS is not a Unified Patents / RPX-listed high-frequency plaintiff; RPX's docket service tracks ACS's suits as a regular party (e.g., the W.D. Tex. complaints indexed by RPX).
3. Repeat correspondent across the chain — unclear. The correspondent of record for reels 057139/0161, 0166, and 0246 could not be retrieved from the sources available in this session. (The file history shows customer number 20995 and an "Authorized by" entry for Jordan Cox on the filing receipt, but that is prosecution-side, not an assignment correspondent, and is not a finding.) All three recordings share a single date and assignee, which is consistent with one batch filing, but I will not assert recurrence without the correspondent field.
4. Cascading transfers — not present. Three assignments recorded on the same date to the same single assignee (ACS) is the opposite of chained-LLC cascading; there are no consecutive transfers through multiple entities.
5. Pre-litigation transfer — not present. The recordings (2021-08-10) predate the first suit naming US 11,570,034 (W.D. Tex., filed 2024-09-26) by more than three years, and the earlier NVIDIA suit (2019) predates the recordings entirely. No assignment sits within six months of any infringement filing.
6. Bankruptcy fire-sale — not present. No bankruptcy proceedings involving ACS, Dauger Research, or any assignee were found.
7. Privateering — not present. No evidence that an operating company transferred the patent to an NPE to assert against competitors; ACS asserts in its own name as the developer, and both named inventors are principals of the entities in the chain.
8. Defensive aggregator (anti-NPE) — not present. The chain terminates at ACS, which is actively asserting, not at RPX, AST, LOT, Unified Patents, or OIN.

Verdict

Operating-company assertion.

The complete recorded chain consists of three assignments from the inventors and Dauger Research, Inc. to Advanced Cluster Systems, Inc. (reels 057139/0161, 057139/0166, 057139/0246, recorded 2021-08-10), with no transfers to any LLC shell, NPE, or defensive aggregator, no cascading transfers, and no assignment timed to any litigation filing. ACS is the inventor-founded developer of the SET cluster-computing software, remains the recorded assignee (as it confirmed in its IPR2025-00913 mandatory notice), and is suing Intel and AMD in its own name while defending the instituted IPR — the classic posture of an inventor-controlled operating company enforcing its own patents, albeit a small one whose only apparent commercial activity is this enforcement campaign.

Verification: search patent number 11570034 at https://assignmentcenter.uspto.gov/ (reels 057139/0161, 057139/0166, 057139/0246); cross-check legal events at https://patents.google.com/patent/US11570034/en; litigation dockets at https://dockets.justia.com/browse/court-txwdce/noscat-10/nos-830 (7:24-cv-00244, 7:24-cv-00245) and PTAB case IPR2025-00913.

Caveat: the correspondent-of-record field for the three assignments could not be verified in this session; if you can pull the Assignment Center records directly, that is the one field worth confirming before finalizing.

The searches are returning useful leads. I need the exact "References Cited" list on the face of US11570034B2 and the granted claim set. Let me dig deeper.

Prior-Art Analysis — US Patent 11,570,034 B2 ("Cluster computing")

A. Scope, sources, and confidence caveats (read first)

Per your instruction, I searched for the literal number 11570034 only (no similar numbers), and confirmed the target is US11570034B2, application 17/374,789, the patent challenged in IPR2025-00913 (Intel et al. v. Advanced Cluster Systems, Inc.). Key sources used: Google Patents family record (US20140372586A1 parent publication page), the Dimensions record for US-11570034-B2, the IPR2025-00913 docket (ipverse.greyb.com) and the PTAB petition claim-chart documents (ptacts.uspto.gov).

Three important limitations on what I could verify:

1. The "References Cited" section printed on the face of the granted '034 patent is not reproduced in the full text you supplied, and my searches did not surface the Google Patents "Patent Citations" block for US11570034B2 itself. The most reliable backward-citation list I retrieved is the 6-patent citation list shown on the parent-family publication US20140372586A1 (the 2014 publication of the same continuation family, application 14/181,112 → US10333768B2). The '034 is a later continuation in that same family and shares the same specification; its own IDS (submitted in application 17/374,789) demonstrably included additional art (e.g., the MultiMATLAB references — see IPR Ex. 2024, below), so the face-of-'034 list may be a superset of the 6 listed here.
2. The granted claim text of the '034 is not in the supplied text. The claim mapping below is reconstructed from (a) the five independent-claim-style embodiments in the Summary (which map to the asserted claims), (b) the PTAB petition's limitation-by-limitation charts, and (c) the asserted claims in the W.D. Tex. complaints (Intel: claims 1, 30; AMD: claims 1, 2, 3, 8, 10, 24, 25, 27, 28). This reconstruction is inferred, not verified against the issued claim set (USPTO Patent Center / IPR Ex. 1001 would confirm).
3. Bibliographic details of two references (US6074427, US7136924) could not be fully verified from my searches; I flag those explicitly rather than guessing.

Applicable law. The '034 claims priority to June 13, 2006 (pre-AIA). Because it is entitled to a pre-March-2013 effective filing date, pre-AIA 35 U.S.C. § 102 governs. I note the applicable subsection (a)/(b)/(e) for each reference.

B. Reconstructed claim map of US11570034 (needed for § 102 mapping)

The PTAB petition challenges at least claims 1, 8, 10, 13, 15, 16, 17, 18, 19 ("Every challenged claim recites 'cluster node modules.' Ex. 1001, claims 1, 8, 10" — PTAB petition 1542544; claim chart for claims 13–19 — PTAB petition 1557794).

C. Patent citations for the '034 family — individual analysis

The six patent citations shown on the family publication US20140372586A1 (Google Patents "Patent Citations (6)" block), plus the patent expressly cited in the '034 specification, plus patent art relied on in IPR2025-00913:

C1. US20030195938A1 — "Parallel processing systems and method" (Howard)

• Full citation: Howard, Kevin David; US Patent Application Publication US 2003/0195938 A1, published Oct. 16, 2003; priority Jun. 26, 2000.
• Brief description: A parallel-processing system/method in which tasks are distributed across multiple processing elements over a network, with a controlling processor managing execution. Relevant to the general "multiple processors each executing a kernel, coordinated as a cluster" concept.
• § 102 subsection: Pre-AIA § 102(a)/(b)/(e) (published and filed well before 2005-06-13 and 2006-06-13).
• Potential claim coverage: Broadly, the multi-processor architecture of claims 1–3, 8, 10, and method claim 24. It does not appear to disclose the "cluster node module that appears as a single-node kernel to the UI" (claim 8), the "data structure storing messages from other node modules" (claim 1), or the Mathematica peer-to-peer specifics (claim 30); those limitations would likely require combination with another reference, making it a weak stand-alone § 102 anticipation candidate for the full independent claims and a stronger § 103 (obviousness) reference.

C2. US6968359B1 — "Merge protocol for clustered computer system" (IBM)

• Full citation: International Business Machines Corporation; US Patent 6,968,359 B1, filed Aug. 14, 2000, granted Nov. 22, 2005.
• Brief description: A clustered computer system with a merge protocol for adding/merging nodes into a cluster, including cluster data services and inter-node communication for cluster membership.
• § 102 subsection: Pre-AIA § 102(a) and § 102(e) (issued and filed before 2006-06-13; issuance Nov. 2005 is within one year of the priority date, so § 102(b) by issue date does not apply — the filing date route under § 102(e) is the cleaner ground).
• Potential claim coverage: The cluster-membership/initialization aspects map best to claims 10, 15, and 16 (launching/merging cluster node modules into a cluster, establishing communication among nodes). It is less relevant to the kernel/UI impersonation of claim 8, the three-kernel message-queue structure of claim 1, or the Mathematica system of claim 30.

C3. US20050021751A1 — "Cluster data port services for clustered computer system" (IBM)

• Full citation: International Business Machines Corporation; US Patent Application Publication US 2005/0021751 A1, filed Jul. 24, 2003, published Jan. 27, 2005. (This is Ex. 1080 in IPR2025-00913.)
• Brief description: Provides "cluster data port services" — a data-port interface through which application programs running on cluster nodes access cluster services and communicate with other nodes of the cluster (a middleware/service layer between applications and cluster communications).
• § 102 subsection: Pre-AIA § 102(a)/(b)/(e) (published and filed before both 2005-06-13 and 2006-06-13).
• Potential claim coverage: The service-layer concept is close to the "cluster node module" that mediates between an application/kernel and other nodes. Strongest against claims 8, 10, 17–19 (nodes accepting and communicating user instructions to other nodes/kernels) and claim 24 (method of routing commands to kernels via node modules). Likely lacks the three-processor message-queue data structure (claim 1) and Mathematica/MPI specifics (claim 30). Its use as IPR Ex. 1080 indicates the petitioners regard it as material to the challenged claims.

C4. US8601101B1 — "Cluster communications framework using peer-to-peer connections" (Sun/Oracle)

• Full citation: Oracle America, Inc. (filed as Sun Microsystems); US Patent 8,601,101 B1, filed Jun. 28, 2004, granted Dec. 3, 2013. (This is Ex. 1062 in IPR2025-00913.)
• Brief description: A cluster communications framework in which nodes communicate using peer-to-peer connections — each node maintains direct connections to other cluster nodes rather than funneling communications through a master — enabling message passing among cluster members.
• § 102 subsection: Pre-AIA § 102(e) — the 2004-06-28 filing date precedes the '034's 2006-06-13 priority date; the 2013 issue date is after, so § 102(b) does not apply.
• Potential claim coverage: This is the most on-point patent reference for the peer-to-peer architecture that the '034 emphasizes over gridMathematica's master-slave model. Strongest against claim 30 (node modules communicating via peer-to-peer architecture) and the peer-to-peer aspects of claims 1, 8, 10 (node modules communicating with one another, messages originating from other node modules) and claim 24. Its use as IPR Ex. 1062 confirms relevance. It likely does not disclose Mathematica kernels or the kernel-impersonation/UI behavior.

C5. US20070073705A1 — "Method of dynamically linking objects operated on by a computational system" (Wolfram Research)

• Full citation: Wolfram Research, Inc.; US Patent Application Publication US 2007/0073705 A1, filed Sep. 23, 2005, published Mar. 29, 2007.
• Brief description: Methods for dynamically linking computational objects in a computational system (in the Mathematica/technical-computing environment) — i.e., establishing dynamic connections between kernels, front ends, and computational objects (MathLink-style linking).
• § 102 subsection: Pre-AIA § 102(e) (filed 2005-09-23, before the 2006-06-13 priority date; publication date is after the priority date, so § 102(a)/(b) by publication do not apply).
• Potential claim coverage: Relevant to the Mathematica context of claims 8, 24, and 30 (kernel/UI communication, kernel linking). It does not disclose cluster node modules, MPI, or multi-node peer-to-peer message passing, so it is unlikely to anticipate any full independent claim alone; it is best used as a secondary reference for the Mathematica/kernel-linking environment.

C6. US20070094532A1 — "Kernel debugging in a cluster computing system" (HP)

• Full citation: Hewlett-Packard Development Company, L.P.; US Patent Application Publication US 2007/0094532 A1, filed Oct. 25, 2005, published Apr. 26, 2007.
• Brief description: Systems/methods for debugging kernels running in a cluster computing system — i.e., multiple kernels executing on multiple cluster nodes with inter-node communication, with debugging control over those kernels.
• § 102 subsection: Pre-AIA § 102(e) (filed 2005-10-25, before 2006-06-13).
• Potential claim coverage: Discloses multiple single-node kernels running on cluster nodes — the baseline environment of claims 8, 10, 24, and (contextually) 30. It lacks the "cluster node module" abstraction, the message-queue data structures, and the UI-impersonation, so it is a weak stand-alone anticipation reference and a better § 103 building block.

C7. US7136924B2 — "Method and system for parallel operation and control of computer clusters" (Dauger) — cited in the '034 specification

• Full citation: Dauger, Dean E.; US Patent 7,136,924 B2 (the '034 specification expressly states: "U.S. Pat. No. 7,136,924, issued to Dauger discloses a method and system for parallel operation and control of computer clusters"). I could not verify its exact filing date from my searches (the issue date appears to be Nov. 2006, i.e., shortly after the '034's Jun. 13, 2006 priority date).
• Brief description: Dauger's earlier system for parallel operation and control of computer clusters, including node control/interface modules and cluster configuration — the direct technical ancestor of the '034's cluster node module and configuration module.
• § 102 subsection: Uncertain — if the application was filed more than one year before Jun. 13, 2006 (i.e., before Jun. 13, 2005), pre-AIA § 102(b) applies; if filed before Jun. 13, 2006, § 102(e) may apply (subject to the pre-AIA "by others" caveat, since Dauger is a named inventor on the '034 — a same-inventor patent is not § 102(e) art but can still be § 102(a)/(b) art, with § 103(c) implications for obviousness).
• Potential claim coverage: Potentially the closest patent prior art to the cluster node module concepts: claims 1, 8, 10, 13, 15–16, 24 (node modules, cluster initialization/configuration, control of kernels). Verify the filing date before relying on it for a § 102 ground.

C8. US6074427A — cited as Ex. 1081 in IPR2025-00913

• Full citation: US Patent 6,074,427 A (cited by IPR petitioners on Aug. 27, 2025 as Ex. 1081). I could not verify its title, dates, or content from my searches and will not guess.
• § 102 subsection / claim coverage: Not assessed — insufficient verified information. Treat as unverified until confirmed against the IPR record or USPTO.

D. Most relevant non-patent prior art (IPR2025-00913 grounds — NPL, not "patent citations")

Because your question asks for the most relevant prior art overall, the pending IPR is the best evidence of what the challengers regard as the strongest art. The institution decision (Nov. 7, 2025) and the petition rely primarily on non-patent literature, headed by the MultiMATLAB references (which were also submitted via IDS in application 17/374,789 per IPR Ex. 2024):

Per the PTAB claim chart, petitioners argue Menon/POE/Trefethen render obvious limitations such as "[15.1] launching cluster node modules," "[15.2] after launching… configuring access… to a non-transitory computer-readable medium comprising program code for a single-node kernel," and "[16.3] assigning a processor identification number." Note these are § 103 obviousness arguments, not pure § 102 anticipation — the PTAB institution decision having found a reasonable likelihood on that basis.

E. Summary table — patent references and potential § 102 anticipation

F. Bottom line

• The most on-point patent citations for the '034's core concepts are US8601101B1 (peer-to-peer cluster communications — best fit for claim 30 and the peer-to-peer aspects) and US20050021751A1 (cluster data-port services — best fit for the node-module/UI-instruction aspects of claims 8, 10, 17–19); both are already cited in IPR2025-00913 (Exs. 1062 and 1080).
• The closest overall prior art (per the live IPR) is non-patent: Menon & Trefethen's MultiMATLAB (Exs. 1005/1006) and IBM's POE/RS-6000 SP documentation (Exs. 1007/1008), directed at claims 1, 8, 10, 13, 15–19 — argued primarily as § 103 obviousness, not pure § 102 anticipation.
• None of the cited patent references appears, on the available evidence, to disclose every limitation of the full independent claims (e.g., the three-node message-queue data structure of claim 1, the kernel-impersonation of claim 8, or the Mathematica peer-to-peer system of claim 30), so a pure § 102 anticipation case against any full independent claim would be difficult on these citations alone; combinations under § 103 are the realistic path — which is precisely how the IPR petitioners are proceeding.

Outstanding verification items (do not rely without checking): (1) the exact face-of-'034 "References Cited" list and granted claim text (USPTO Patent Center or IPR Ex. 1001); (2) the filing date of US7136924B2; (3) the title/dates of US6074427A; (4) whether IPR2025-00913's final written decision (expected ~Nov. 2026) resolves the challenged claims.

I'll research the prior art landscape for US 11,570,034, starting with the most authoritative source: the instituted IPR2025-00913 petition, which necessarily identifies the strongest § 103 combinations.

The IPR record gives me the exact grounds Intel/AMD asserted. Now I need (a) the granted claim language of the '034 patent, and (b) the PTAB institution decision confirming which grounds were instituted, plus details on the primary references.

I have the instituted grounds. Now let me retrieve the actual granted claim language of the '034 patent and details on the primary prior-art references (Menon, Trefethen).

§ 103 Obviousness Analysis — US Patent 11,570,034 B2 ("Cluster Computing")

Analyst: Technical patent analyst
Date of analysis: April 26, 2026
Patent: US 11,570,034 B2 (issued January 31, 2023; priority date June 13, 2006)
Proceeding context: IPR2025-00913 (Intel Corp. and AMD v. Advanced Cluster Systems, Inc.), instituted November 7, 2025; AMD terminated via settlement January 29, 2026; Intel remains; projected final written decision ~November 27, 2026 (none issued as of this analysis).

I. Legal framework applied

Under 35 U.S.C. § 103, a patent claim is unpatentable if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSITA). The analysis follows the Graham v. John Deere factors — (1) scope and content of the prior art, (2) differences between the prior art and the claims, (3) level of ordinary skill, and (4) secondary considerations — informed by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), which permits combinations of known elements yielding predictable results, "obvious to try" rationales where the design space is small, and the common-sense incentives (design needs, market pressure) that drive a POSITA to combine references.

The most probative evidence that the asserted § 103 combinations are legitimate is procedural: the PTAB instituted IPR2025-00913 on all asserted grounds (Paper 16 at 10, 49, cited in Patent Owner Response, Paper 22), meaning the Board found a reasonable likelihood that the challenged claims are unpatentable over the combinations analyzed below. I treat that institution decision as strong corroboration, while noting the merits remain pending.

II. Claimed subject matter (as established in the IPR record)

The full granted claim text was not reproduced in the materials supplied, so I reconstruct the dispositive limitations from the PTAB Institution Decision and Patent Owner's Response (which quote the claims verbatim). All 30 claims are challenged; the independent claims are 1, 25, 28, and 30.

Key limitations common to the independent claims (per Ex. 1001, quoted in Paper 22 and the Institution Decision):

• Multi-core processor limitations: Independent claims 1, 25, and 28 require the second and third nodes to comprise "a hardware processor with a plurality of processing cores" (limitations [1.4.1], [1.5.1], [25.5.1], [25.6.1], [28.6.1], [28.7.1]); claim 30 requires "the hardware processor comprises multiple processor cores" ([30.1.2], [30.5.3.1]).
• Three-node chained evaluation flow (1→2→3→1): The second node "receive[s] calls from the first node, execute[s] at least a first mathematical expression evaluation, and communicate[s] a result… to a third node" ([1.4.2]); the third node receives that result, "execute[s] at least a second mathematical expression evaluation using the received result, and communicate[s] the result… to the first node" ([1.5.2]); the first node returns the result to the user interface ([1.6], [25.7], [28.8], [30.1.1] — the "eval-return" limitations).
• Peer-to-peer architecture (explicit in claims 1 and 30; the term was the subject of a proposed construction).
• Cluster node modules that (a) communicate with a single-node kernel (e.g., a Mathematica or MATLAB kernel) and with other cluster node modules, (b) accept instructions from a user interface, (c) impersonate a kernel to the UI, and (d) implement MPI-style calls and high-level cluster commands (per the Summary and Figures 2–3 of the specification).
• Data structures: a received-message queue (RMQ) storing messages from other node modules and a message-receiving queue (MRQ) storing expected-sender/source information.
• Claims 26 and 29 (dependent): asynchronous communication calls and creation of "data packets" containing an expression payload and a destination node.

III. Scope and content of the prior art

The IPR record identifies the primary references (exhibits in IPR2025-00913):

Supporting references in the record include Buyya, High Performance Cluster Computing (Ex. 1011, 1999); Choy et al., "Parallel MATLAB: Doing It Right," Proc. IEEE 93(2) (Ex. 1014, 2005); Maeder, Mathematica Parallel Computing Toolkit (Ex. 1015, 2005); Morrow et al., SC'98 (Ex. 1013); Miller, pyMPI (Ex. 1024, 2002); NIST DADS "Single Program Multiple Data" (Ex. 1009, 2004); Barrios et al., The RS/6000 SP Inside Out (Ex. 1010, 1999); Fineberg et al. (Ex. 1012, 1997). All of these predate the June 13, 2006 priority date (printed-publication status of Trefethen, MPIref, RS6000, and POEref is disputed by Patent Owner but was not fatal at institution).

Content of the primary references:

• Menon discloses MultiMATLAB, a functioning system that makes MATLAB (a single-node, interpreted mathematical-software kernel) run in parallel across up to 32 nodes of an IBM SP2 cluster. Each node runs a MATLAB process; MEX routines implement standard MPI calls inside MATLAB so that processes communicate directly, node-to-node (peer-to-peer); each process is assigned an identification number and waits for commands from the interactive (controlling) MATLAB process. Menon is a paper about the second-generation MultiMATLAB redesign and cites Trefethen.
• Trefethen is the companion report from the same Cornell project, providing code examples of sequential processing and point-to-point communication between MATLAB processes, including evaluation-and-return sequences among numbered nodes; it describes parallel MATLAB as "inevitable."
• RS6000 is the hardware manual for the exact platform Menon used: SP2 nodes with "Symmetric MultiProcessor (SMP)" configurations of 4/8/12/16 processors, POWER3 SMP High nodes, and network adapters (Ethernet, Token Ring, ATM, WAN).
• POEref documents IBM's Parallel Operating Environment, including the poe command used to launch and initialize parallel MATLAB processes across SP2 nodes — the initialization mechanism Menon references.
• MPIref is the definitive MPI 1.x standard, defining MPI_SEND, MPI_RECV, non-blocking MPI_ISEND/MPI_IRECV, MPI_INIT/MPI_FINALIZE, communicators, and send/receive buffers with destination fields (the "packet" creation the dependent claims recite).

IV. Combination 1 — Claims 1–25, 27–28, 30 over Menon + Trefethen + RS6000 + POEref

A. Element mapping

1. Multi-node cluster; first/second/third nodes each with a hardware processor. Menon's MultiMATLAB runs MATLAB processes on multiple nodes of an IBM SP2 cluster (up to 32 nodes); RS6000 supplies the node hardware details (SMP and uniprocessor configurations, processors, memory, network adapters). Trefethen's code examples demonstrate multi-node operation with numbered processes.
2. "A hardware processor with a plurality of processing cores." RS6000 discloses SP2 nodes with SMP configurations containing up to sixteen processors. The Petition (via Dr. Bajaj) argued that an SMP node populated with multiple processors, each having a core, satisfies this limitation (Pet. 42–43; Ex. 1003 ¶ 209). This is the most hotly contested mapping — Patent Owner (via Dr. Smith) contends RS6000 describes multiple single-core processors in a node, not a single processor with multiple cores, and that the claims (read in light of the '034 specification's Core 2 Duo discussion) require the latter. The Board instituted but ordered the parties to brief the construction of [1.4.1], [1.5.1], and [30.1.2] — i.e., the Board found this a reasonable mapping on the current record, not a settled one.
3. Single-node kernel interpreting program-code instructions. Menon's MATLAB process on each node is exactly the "kernel designed to communicate with a single node" that the '034 specification describes (the specification explicitly lists MATLAB as an alternative to Mathematica).
4. Cluster node modules communicating with the kernel, with one another, and with a user interface. Menon's MEX routines embed MPI in MATLAB, giving each MATLAB process the ability to send/receive messages to/from any other process (peer-to-peer), while each process still accepts commands from the interactive (controlling) MATLAB process. Trefethen supplies working code demonstrating the message-passing calls. This maps directly to the claimed cluster node module that "appears as a single-node kernel to the user interface" while relaying commands/results across the cluster.
5. MPI calls available from the user interface / programming environment. Menon and Trefethen make mpi_send/mpi_recv-style calls callable from within MATLAB — the analog of the '034 patent's "MPI calls added to or made available from an interactive programming environment."
6. Three-node chained evaluation (1→2→3→1) with programmatic return of results. Trefethen's code examples show sequential evaluation in which a node evaluates an expression, passes the result to another node, which evaluates further and returns results to the controlling node. The Petition mapped the claimed chain onto these point-to-point sequences (including a user-scripted demonstration). Patent Owner disputes this, arguing (a) Trefethen's Eval() forwards screen output rather than programmatically returning evaluation results, and (b) no reference discloses the specific 1→2→3→1 configured chain — the Petition's "could have" scenarios being legally insufficient. The Board instituted despite these arguments, finding the Petition's mapping adequate at the reasonable-likelihood stage.
7. Initialization of the cluster node modules. POEref's poe command (and MPI MPI_Init) launches and initializes the parallel MATLAB processes across the SP2 — the analog of the '034 patent's cluster initialization process of Figure 4.
8. Data structures (RMQ/MRQ). MPI's standard message-buffering architecture (send/receive queues, source/destination/tag envelopes) and Menon/Trefethen's MEX implementation of MPI in MATLAB provide the received-message storage and expected-source/destination tracking the claims recite. (This maps most cleanly with MPIref added — see Combination 2.)

B. Motivation to combine — Combination 1

A POSITA would have had multiple, record-supported reasons to combine:

1. Same project, same team, express cross-citation. Menon and Trefethen describe the same Cornell MultiMATLAB system; Menon expressly cites Trefethen; the references are a single body of work. Combining companion papers describing one system is the paradigm of an obvious combination (KSR, "familiar items may be combined to create a useful product").
2. Platform manuals are the routine implementation step. Menon expressly discloses implementing MultiMATLAB on an IBM SP2 using IBM's Parallel Operating Environment. A POSITA implementing that disclosure would consult the SP2 hardware manual (RS6000) for node/processor/network details and the POE manual (POEref) for the process-launch mechanism. This is a "design need" and routine engineering step, not hindsight reconstruction.
3. Predictable result and high expectation of success. The combination does not require inventing anything new — the references collectively describe an already-existing, functioning system (MultiMATLAB on SP2). Trefethen described parallel MATLAB as "inevitable," evidencing that the field knew the direction was obvious. Adding hardware details from the platform's own manuals yields the predictable result of a working parallel MATLAB cluster.
4. Same field, same problem. All references address cluster/parallel computing for mathematical software (MATLAB); the '034 patent itself concedes grid-style parallel mathematical computing was known (gridMathematica, master-slave) and that the advance is peer-to-peer intercommunication — which Menon teaches.

V. Combination 2 — Claims 26 and 29 over Combination 1 + MPIref

Claims 26 and 29 add (per the Petition's characterization) specifics of asynchronous communication calls and creation of data packets (an expression payload and a destination node, with forwarding by the local cluster node module).

• Asynchronous calls. MPIref defines non-blocking MPI_ISEND/MPI_IRECV with completion-testing (MPI_TEST/MPI_WAIT) — the direct analogs of the '034 patent's mpiISend/mpiIRecv/mpiTest/mpiWait calls. Menon discloses MPI as MultiMATLAB's communication layer, so the claimed asynchronous-call limitation is the standard's routine content.
• Packet creation. MPIref defines message envelopes (destination rank, tag, communicator) and typed send buffers — the "packet containing the Mathematica/MATLAB expression to be sent as payload and where the expression should be sent" of the specification.

Motivation: Menon states MultiMATLAB uses "the MPI communication standard"; a POSITA implementing or understanding Menon's MEX-based MPI would consult MPIref as the definitive standard for the precise syntax and semantics of the communication calls. Combining a disclosed system with the standard it implements is a routine, necessary implementation step with a high expectation of success. The Board instituted this ground as well.

VI. Additional/alternative combinations worth considering

Although the instituted grounds center on Menon + Trefethen + IBM manuals, other record art independently supports obviousness of particular limitations:

1. Maeder, Mathematica Parallel Computing Toolkit (Ex. 1015, 2005) + Menon/Trefethen. The '034 specification's own Background concedes gridMathematica (master-slave distributed computing for Mathematica) was known. Maeder documents the Mathematica-specific toolkit (kernels, MathLink, remote evaluation). A POSITA seeking Mathematica cluster functionality with peer-to-peer inter-kernel communication would combine Maeder's Mathematica infrastructure with Menon/Trefethen's peer-to-peer MPI-in-interpreted-language teachings — rendering obvious the Mathematica-kernel, Front End, and MPI-from-UI aspects of claims directed to Mathematica embodiments.
2. Choy et al., "Parallel MATLAB: Doing It Right" (Ex. 1014, 2005) — a survey of parallel-MATLAB approaches including MultiMATLAB; evidences that combining parallel-MATLAB systems with MPI was the known design space and would motivate the Menon/Trefethen combination.
3. pyMPI (Ex. 1024, 2002) — embeds MPI in the interpreted Python language; corroborates that embedding MPI calls in an interactive interpreted environment (the claimed "MPI calls from the user interface") was a known technique.
4. Buyya, High Performance Cluster Computing (Ex. 1011, 1999); Morrow et al. (Ex. 1013, 1998) — general cluster/MPI and parallel-linear-algebra-for-MATLAB references that fill any gaps in routine cluster-communication details.
5. Dauger, US 7,136,924 (cited in the '034 specification itself) — parallel operation and control of computer clusters using discoverable network services (the CNCI architecture). Caution: the '034 patent claims priority to June 13, 2006, and US 7,136,924 issued November 21, 2006; its availability as § 102 prior art depends on its own filing/publication dates (e.g., pre-AIA § 102(e)), which I have not verified. It is likely not prior art under § 102(b) (issued post-critical-date), so I flag it as secondary/uncertain rather than primary.
6. References cited on the face of the patent family (US 2003/0195938 A1; US 6,968,359 B1; US 2005/0021751 A1; US 8,601,101 B1; US 2007/0073705 A1; US 2007/0094532 A1) — general parallel-processing and cluster-communications art that the Examiner considered and allowed over; these are weaker for the core peer-to-peer-mathematical-kernel combination and are not the focus of the instituted grounds.

VII. Differences between the prior art and the claims (and why they are not patentable differences)

The genuine differences a POSITA would identify are: (a) applying peer-to-peer MPI-style communication to a single-node interpreted mathematical kernel (Mathematica/MATLAB); (b) making the cluster node module transparent to the UI (kernel impersonation); (c) the specific 1→2→3→1 evaluation chain; and (d) multi-core processor nodes. Under KSR:

• (a) is precisely what Menon/Trefethen did for MATLAB — the same problem, same solution, same field.
• (b) is inherent in Menon/Trefethen: the MATLAB user calls MPI functions as ordinary MATLAB commands; the MPI layer is transparent.
• (c) is a routine sequencing of the disclosed point-to-point primitives — the "obvious to try" of arranging a small number of known communication patterns in a known order to achieve a predictable chained evaluation.
• (d) is the only difference grounded in hardware rather than software, and it is the one the Board has flagged for claim construction — if the claims are construed to cover an SMP node with multiple processor-bearing chips (as the '034 specification's "processor cores are generally independent microprocessors" language arguably supports), RS6000's SMP nodes map directly.

The combination yields the predictable result of a parallelized mathematical-software cluster, a goal Trefethen called inevitable and that Menon had already reduced to practice.

VIII. Level of ordinary skill

Based on the expert declarations in the IPR (Dr. Bajaj for Petitioners; Dr. Melissa C. Smith for Patent Owner) and the field's nature, a POSITA would have (at minimum) a bachelor's degree in computer science/computer engineering or equivalent, plus 2–5 years of experience with parallel computing, MPI, cluster architectures (e.g., IBM SP2, Beowulf), and interpreted mathematical software (MATLAB/Mathematica). Under KSR, such a POSITA is presumed capable of integrating prior-art teachings using ordinary creativity — not an automaton.

IX. Secondary considerations (Graham factor 4)

The record before me contains no objective evidence of non-obviousness (no long-felt-need, unexpected-results, or commercial-success declarations in the IPR materials I retrieved). ACS's aggressive enforcement (NVIDIA litigation 2019–2023; Intel and AMD W.D. Tex. suits 2024; this IPR) evidences commercial interest but not objective non-obviousness. AMD's settlement and dismissal (January 2026) are consistent with business resolution and carry no weight on obviousness. I therefore find no secondary considerations that would overcome a strong prima facie case.

X. Counterarguments and litigation risk (balanced assessment)

A rigorous analyst must also weigh the Patent Owner's record arguments, which are substantial and could defeat the grounds at the final written decision (due ~November 27, 2026):

1. Multi-core limitation. If the Board construes [1.4.1]/[1.5.1]/[30.1.2] to require a single chip with multiple cores (the "Core 2 Duo" reading), RS6000's SMP nodes (multiple single-core POWER3 processors) do not meet it, and no asserted reference discloses a multi-core processor. The Board has specifically ordered briefing on this — it is the single biggest risk to the obviousness case. (Note also: the W.D. Tex. court found claim 30's "communicate a result… to the first node" phrase indefinite; indefiniteness is not before the Board.)
2. Eval-return. Patent Owner convincingly distinguishes screen-output forwarding (Trefethen's Eval()) from programmatic return of evaluation results to the first node and UI ([1.6] et seq.); if the Board agrees, the independent claims lack an essential element in the primary references.
3. Three-node chain. No reference discloses nodes configured to perform the claimed 1→2→3→1 chain; the Petition's "could have" scenarios and user-scripted demonstration may be insufficient under Arendi and the no-hindsight principle, especially since Menon describes a redesign of MultiMATLAB (arguably teaching away from naive extension of the earlier architecture).
4. Printed-publication challenges. Trefethen's web-only availability in 1996, the MPI Forum draft's status, and the IBM manuals' dissemination are contested under Blue Calypso/Klopfenstein; if any primary reference falls, the corresponding ground weakens (though Menon/SC'97 is the strongest on accessibility).
5. Motivation/hindsight. Patent Owner argues the combination rationale is generalized and hindsight-driven; the Board's institution shows this argument did not prevail at the threshold stage, but the full merits record may change the outcome.

XI. Conclusion

The strongest § 103 case against US 11,570,034 B2 is:

• Ground 1 (claims 1–25, 27–28, 30): obvious over Menon (Ex. 1005) + Trefethen (Ex. 1006) + RS6000 (Ex. 1007) + POEref (Ex. 1008) — the MultiMATLAB system (peer-to-peer MPI inside an interpreted mathematical kernel on an IBM SP2) plus the platform's hardware and launch documentation.
• Ground 2 (claims 26, 29): obvious over Ground 1 + MPIref (Ex. 1017) for asynchronous calls and packet creation.

These are the instituted grounds in IPR2025-00913, meaning the PTAB has already found a reasonable likelihood of prevailing on the merits — the strongest available indicator that the combinations are legitimate § 103 cases rather than hindsight constructs. The motivation to combine is unusually well supported: companion papers from one research team describing one functioning system, a disclosed hardware platform whose own manuals fill implementation gaps, and a disclosed communication standard that defines the claimed call semantics — all yielding the predictable result of a parallelized mathematical-software cluster.

The outcome is not certain: the multi-core processor limitation, the eval-return requirement, the 1→2→3→1 chain, and the printed-publication challenges are genuine, contested issues on which Patent Owner has marshaled expert testimony (Dr. Smith) and the Board has ordered supplemental claim construction. With the final written decision projected for late November 2026 and no decision issued as of today (April 26, 2026), the obviousness case is instituted and strong on the current record, but unresolved.

Key sources

• IPR2025-00913: Petition (Paper 3, filed Apr. 29, 2025); POPR (Paper 10, Aug. 27, 2025); Director Discretionary Decision (Paper 13, Sep. 19, 2025); Institution Decision (Paper 16, Nov. 7, 2025); AMD Termination Order (Paper 21, Jan. 29, 2026); Patent Owner Response (Paper 22, Feb. 6, 2026).
• Exhibit list (Exs. 1005–1008, 1017; supporting Exs. 1009–1016, 1024) per Petitioners' Response to PO's Discretionary-Denial Reply (Sep. 8, 2025) and the ai-lab.exparte.com case summary.
• USPTO PTACTS documents for IPR2025-00913 (institution decision excerpts quoting claims and limitations [1.4.1]–[30.5.3.1]).
• Patent record: Google Patents US11570034B2; W.D. Tex. cases 7:24-cv-00244 and 7:24-cv-00245 (per Unified Patents/Google Patents litigation feed).

Caveat: The granted claim text of the '034 patent was not included in the materials provided; claim limitations above are quoted from the PTAB Institution Decision and Patent Owner Response, which reproduce them. If exact claim language is needed for a filing, verify against USPTO Patent Center or Ex. 1001.